Intel® Xeon™ Processor and Intel® E7500 / E7501 Chipset Compatible Platform Design Guide For Use with Intel® Xeon™ Processors with 512-KB L2 Cache and Intel® Xeon™ Processors with 533 MHz System Bus For designing a single platform compatible with both the Intel® E7500 and E7501 chipsets December 2002 Document Number: 251929-001
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Contents 1 Introduction ................................................................................................................17 1.1 1.2 1.3 2 Component Quadrant Layout..............................................................................27 2.1 2.2 2.3 2.4 3 Intel® Xeon™ Processor Quadrant Layout .........................................................28 Intel® E7500/E7501 Chipset MCH Quadrant Layout ..........................................29 Intel® ICH3-S Quadrant Layout .........
5 System Bus Routing Guidelines ........................................................................ 63 5.1 5.2 5.3 5.4 5.5 5.6 6 Memory Interface Routing Guidelines............................................................. 83 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 4 Routing Guidelines for the AGTL+ Source Synchronous 2X and 4X Groups ..... 65 Routing Guidelines for Common Clock Signals .................................................. 66 5.2.1 Wired-OR Signals................................
7 Hub Interface ............................................................................................................103 7.1 7.2 7.3 8 Signal Naming Convention................................................................................103 Hub Interface 2.0 Implementation .....................................................................104 7.2.1 Hub Interface 2.0 High-Speed Routing Guidelines ..........................104 7.2.2 Hub Interface 2.
9 I/O 9.1 9.2 9.3 9.4 9.5 9.6 9.7 6 8.2.7.4 Tri-State Buffer or 2:1 Multiplexer for HPx_SLOT [2:0] ...... 132 8.2.7.5 HPx_SID Output Signal ...................................................... 132 8.2.7.6 Pull-Ups/Pull-Downs in Dual-Slot Parallel Mode ................ 132 8.2.7.7 Hot-Plug Multiplexed Signals in Dual-Slot Parallel Mode ... 133 8.2.7.8 SMBus Address Considerations ......................................... 134 8.2.7.9 Reference Schematic for Dual-Slot Parallel Mode .............
9.7.3 9.7.4 9.7.5 10 Debug Tools .............................................................................................................171 10.1 10.2 10.3 11 9.7.2.1 General Trace Routing Considerations ..............................161 9.7.2.2 Trace Geometry and Length...............................................162 9.7.2.3 Signal Isolation ...................................................................162 9.7.2.4 Power and Ground Connections.........................................162 9.
11.3 11.4 11.5 12 High-Speed Design Concerns........................................................................... 205 12.1 12.2 12.3 12.4 12.5 12.6 13 Return Path ....................................................................................................... 205 Decoupling Theory ............................................................................................ 205 12.2.1 Bulk Decoupling ............................................................................... 206 12.2.
13.5 13.6 14 Layout Checklist .....................................................................................................245 14.1 14.2 14.3 14.4 14.5 14.6 15 CK408 Schematic Checklist ..............................................................................242 SSI Schematic Checklist ...................................................................................243 Processor Checklist...........................................................................................
5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 10 BR[3:0]# Connection for DP Configuration ......................................................... 67 Topology for PWRGOOD (CPUPWRGOOD) ..................................................... 69 Topology for Asynchronous GTL+ Signals Driven by the Processor ..................
8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 8-23 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 Loop Clock Topology.........................................................................................121 IDSEL Sample Implementation Circuit ..............................................................122 Manually-Operated Retention Latch Sensor ...................
11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 11-24 11-25 11-26 11-27 11-28 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 Decoupling Example for a Microstrip Baseboard Design.................................. 192 GTLREF Divider................................................................................................ 193 Suggested GTLREF Generation ....................................................................... 194 MCH Decoupling (Backside View) ...........
4-8 4-9 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 CLK14 Routing Guidelines ..................................................................................58 USBCLK Routing Guidelines...............................................................................59 System Bus Signal Groups ..............................................................
8-14 8-15 8-16 8-17 8-18 8-19 8-20 9-1 9-2 9-3 9-4 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 13-1 13-2 13-3 13-4 13-5 13-6 14-1 14-2 14-3 14-4 14-5 14-6 14 SMBus Address Configuration .......................................................................... 122 Hot-Plug Mode .................................................................................................. 127 Frequency Matrix ..............................................................................................
Revision History Revision -001 Description Initial Release Intel® Xeon™ Processor and Intel® E7500/E7501 Chipset Compatible Platform Design Guide Date December 2002 15
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Introduction 1 Introduction This design guide documents Intel’s design recommendations for systems based on the Intel® Xeon™ processor with 512-KB L2 cache / Intel® Xeon™ processor with 533 MHz system bus and the Intel® E7500/E7501 chipset. This guide is intended for E7500/E7501 chipset compatible platforms. All new E7500 chipet platforms should use this document.
Introduction Terminology Description Core Power Core power refers to a power rail that is on only during full-power operation. These power rails are on when the active-low PSON signal is asserted to the power supply. The core power rails that are distributed directly from the power supply are: +12 V, +5 V, and +3.3 V. Crosstalk The reception on a victim network of a signal imposed by aggressor network(s) through inductive and capacitive coupling between the networks.
Introduction Terminology Description Pad The electrical contact point of a semiconductor die to the package substrate. A pad is only observable in simulations. Pin The contact point of a component package to the traces on a substrate, such as the motherboard. Signal quality and timings can be measured at the pin. Power-Good “Power-Good,” “PWRGOOD,” or “CPUPWRGOOD” (an active high signal) indicates that all of the system power supplies and clocks are stable.
Introduction 1.2 Reference Documentation Table 1-1. Reference Documents (Sheet 1 of 2) Document 20 Document Number/Source 603-Pin Socket Design Guidelines http://developer.intel.com/design/ Xeon/guides/249672.htm ITP700 Debug Port Design Guide http://developer.intel.com/design/ Xeon/guides/ Intel® Xeon™ Processor with 512-KB L2 Cache Signal Integrity Models http://developer.intel.com/design/ Xeon/devtools Intel® 82801CA I/O Controller Hub 3 (ICH3-S) Datasheet http://developer.intel.
Introduction Table 1-1. Reference Documents (Sheet 2 of 2) Document Document Number/Source Intel® Xeon™ Processor with 512-KB L2 Cache Thermal Models http://developer.intel.com/design/ Xeon/devtools/ Intel® Xeon™ Processor with 512-KB L2 Cache Mechanical Model in IGES Format http://developer.intel.com/design/ Xeon/devtools/ Intel® Xeon™ Processor with 512-KB L2 Cache Mechanical Model in ProE* Format http://developer.intel.
Introduction Table 1-3. Intel® E7500 and E7501 Chipset Lock Step Requirements Processor Installed Memory Installed Intel® Xeon™ Processor with 512-KB L2 Cache (INT-mPGA Package) Intel® Xeon™ Processor with 533 MHz System Bus (FC-mPGAs Package) DDR200 DIMM DDR200 / 400 MHz Not Supported DDR266 DIMM DDR200 / 400 MHz DDR266 / 533 MHz Unless otherwise noted, the term MCH refers to the E7500 chipset MCH and E7501 chipset MCH.
Introduction Table 1-4. Processor Feature Set Overview Feature Intel® Xeon™ Processor with 512-KB L2 Cache (INT-mPGA Package) Intel® Xeon™ Processor with 533 MHz System Bus (FC-mPGAs Package) Processor System Bus (PSB) 400 MHz 533 MHz Data Bus Transfer Rate 3.2 GB/s 4.27 GB/s Manageability Features PIROM, Scratch EEPROMs and Thermal Sensor on Package Direct Thermal Diode Access Operating Voltage Socket 1.500 V 603-Pin Socket and mPGA604 Socket mPGA604 Socket Only X-Y: 53.5 mm X-Y: 42.
Introduction 1.3.2.1 Intel® E7500/E7501 Memory Controller Hub (MCH) The MCH is a 1005-ball FC-BGA package and contains the following functionality: • System Bus — Supports dual processors at 100 MHz or 133 MHz (x4 transfers). — System bus peak bandwidth of 3.2 GB/s (400 MHz) or 4.27 GB/s (533 MHz). — Supports 36-bit system bus addressing model. — 12 deep in-order queue, 2 deep defer queue. • Memory Bus — 144-bit wide, DDR200 / DDR266 memory interface with memory peak bandwidth of 3.2 GB/s or 4.27 GB/s.
Introduction 1.3.2.2 I/O Controller Hub 3 (Intel® ICH3-S) The I/O Controller Hub 3 (ICH3-S) provides the legacy I/O subsystem for E7500 chipset-based platforms. Additionally, it integrates many advanced I/O functions. The ICH3-S includes the following features: • Provides Hub Interface 1.
Introduction 1.3.3 Peak Bandwidth Summary Table 1-5 describes the clock maximum speed, sample rate, and peak bandwidth for each of the interfaces in the E7500/E7501 chipset based platform. Table 1-5. Platform Peak Bandwidth Summary Interface 1.3.
Component Quadrant Layout Component Quadrant Layout 2 The following figures show only general quadrant information, not exact component ball count. Designers should use only the exact ball assignment to conduct routing analyses. Reference the following documents for exact ball assignment information.
Component Quadrant Layout 2.1 Intel® Xeon™ Processor Quadrant Layout Figure 2-1 shows the quadrant layout for the Intel Xeon processor with 512-KB L2 cache and Intel Xeon processor with 533 MHz system bus. Figure 2-1.
Component Quadrant Layout 2.2 Intel® E7500/E7501 Chipset MCH Quadrant Layout Figure 2-2.
Component Quadrant Layout 2.3 Intel® ICH3-S Quadrant Layout Figure 2-3.
Component Quadrant Layout 2.4 Intel® 82870P2 P64H2 Quadrant Layout Figure 2-4.
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Baseboard Requirements 3 Baseboard Requirements This chapter summarizes the stack-up used for all platform simulations, the placement of components on the motherboard, and required features to be SSI compliant. 3.1 Platform Stack-Up Figure 3-1 shows the recommended platform stack-up. All layers are 1 oz copper. The processor requires 2 oz of copper to deliver power and 2 oz of copper to deliver ground. Route signal layers as asymmetric stripline on layers 2, 4, 5, and 7.
Baseboard Requirements Table 3-1. Board Requirements Board Factor Material Impedance Requirements • Standard FR4 Tg 170 Epoxy. • 50 Ω impedance ± 10% Layers 2,4,5,7 (except lower left corner SCSI interface). • SCSI interface 83 Ω single-ended, 122 Ω differential pair ± 10% (layers 1 and 8 lower-left corner using the reference stack-up). • 5-mil trace width and space minimum inner/outer. Etch • SCSI interface: 6-mil separation within a pair, 20-mil space between adjacent pairs.
Baseboard Requirements Figure 3-2. Retention Mechanism Placement and Keep-Out Overview Socket PIN #1 Location Socket Shown For Reference Only Maximum Component Height 0.35 " Unless O therwise Specified 1.150 " . .000 " 1. 500 " ∅ .159 " 3.200 " + .002 − .
Baseboard Requirements Utilization of the DC grounding strips requires ground pads around the mounting holes for the retention mechanism. Metal inserts will be pre-assembled to the retention modules to establish DC contact between heatsink base plate and the motherboard ground. The inserts will be grounded to the baseboard at mounting hole ground pads. Fingers on top of the insert will connect to the base of the heatsink.
Baseboard Requirements 3.3 Platform Component Placement Figure 3-4 illustrates the component placement for a typical tower optimized board. Table 3-2 lists the assumptions used for the component placement. Refer to www.ssiforum.org for detailed information on the SSI (Server System Infrastructure) specification. Table 3-2.
Baseboard Requirements 3.4 SSI Compliance If your motherboard is intended to meet Server System Infrastructure (SSI) Specifications, it must meet a minimum set of requirements. All requirements from the Entry-level Electronics-Bay Specification: A Server System Infrastructure (SSI) Specification for Entry Server Version 3.0 (SSI EEB) are highlighted here. Where anything conflicts with the SSI specification, the SSI specification supersedes this document. 3.4.
Baseboard Requirements The SSI EEB specification enumerates various processor mounting locations. A board based on the Intel Xeon processor with E7501 chipset must use the hole locations as specified in Figure 3-6 (SSI EEB, Section 7.1, Figure 18). The baseboard manufacturer must work closely with the chassis manufacturer to ensure these holes are available. Figure 3-7 enumerates all holes used by the reference design. Figure 3-6.
Baseboard Requirements Figure 3-7. Baseboard Mounting Holes Used by Intel® E7501 Reference Board 11.100 7.400 0.900 13.000 3.200 Accessible I/O Connector Area K 1.500 8.811 1.500 5.561 5.112 4.900 F 12.00 E 3.100 A 0 C 8.950 7.000 0 1.125 -0.400 -0.650 0.000 -0.200 12.300, 3X D NOTE: All dimensions are in inches.
Baseboard Requirements 3.4.2 Volume Constraints for Typical General Purpose Baseboards Figure 3-8 and Figure 3-9 show the minimum outer dimensions of the Electronics Bay and the height above the baseboard that must remain clear of chassis features. The keep-out height of the core area (processor, chipset, memory) is defined for high-density servers, such as, but not limited to 2U and 3U servers. These are the volumetric constraints to which the reference board is designed.
Baseboard Requirements 3.4.3 Standard Cutout for Onboard I/O Ports The Entry Electronics-Bay Specification includes the I/O aperture of the ATX 2.03 specification and uses the same dimensions. Because the same dimensions are used, a baseboard manufacturer can create just one thin metal shield for the rear I/O connectors, a shield that works in any chassis that meets this specification.
Baseboard Requirements 3.4.4 Connectors The SSI Spec requires that your baseboard have the following connectors: Main Power Connector, +12 Volt Power Connector, Auxiliary Signal Connector, and cooling fan connectors. All of this information is in the SSI Specification, but is presented here for convenience. This information also meets the EPS12V Power Supply Design Guide Version 1.6. The Power Supply Design Guide supercedes all documentation here. 3.4.4.
Baseboard Requirements 3.4.4.3 Auxiliary Signal Connector The baseboard must have a 5-pin Molex 70545 family connector or equivalent. The header must have the pinout as enumerated in Table 3-5. The PS Alert signal has strict electrical requirements, as documented in the SSI EEB Specification, Version 3.0, Section 5.3.1.6 (PS Alert). Table 3-5. Entry Auxiliary Signal Connector Pinout Pin Signal 1 SMBus Clock 2 SMBus Data 3 PS Alert 4 ReturnS 5 3.
Platform Clock Routing Guidelines Platform Clock Routing Guidelines 4 To minimize jitter, improve routing, and reduce cost, E7500/E7501 chipset-based systems should use a single chip clock solution, the CK408B. In this configuration, the CK408B provides four, 100 MHz or 133 MHz differential outputs pairs for all of the bus agents, including the ITP connector, and five, 66 MHz speed clocks that drive all I/O buses. Figure 4-1 illustrates the clock architecture for the platform.
Platform Clock Routing Guidelines Table 4-2.
Platform Clock Routing Guidelines Figure 4-1. System Clocking Diagram CK408B CPU / CPU# (4) DDR Channel A Host_CLK Processor D I DD MI I D MMM I M M M M DIMMclk (x4 pr.) Processor ITP DDR Channel B 66BUF (5) REF0 (1) USB-48MHz (1) PCIF (3) PCI (7) MCH CLK66 CLK14 D I DD MI I D MMM I M M M M DIMMclk (x4 pr.
Platform Clock Routing Guidelines 4.1 HOST_CLK Clock Group The clock synthesizer provides four sets of 100/133 MHz differential clock outputs. The 100/133 MHz differential clocks are driven to the processors, the MCH, and the processors’ debug port as shown in Figure 4-1. The clock driver differential bus output structure is a “Current Mode Current Steering” output that develops a clock signal by alternately steering a programmable constant current to the external termination resistors “Rt.
Platform Clock Routing Guidelines Table 4-3. HOST_CLK[1:0]# Routing Guidelines Layout Guideline Value Reference Notes Figure 4-3 1,2,3,4 300 ps total budget: HOST_CLK Skew between Agents 150 ps for clock driver 150 ps for interconnect Trace Width 5 mils Figure 4-4 7 Differential Pair Spacing 20 – 25 mils Figure 4-4 5,6 Spacing to Other Traces 25 mils Figure 4-4 Serpentine Spacing Maintain a minimum S1/h ratio of > 26/5 Section 12.
Platform Clock Routing Guidelines 10.Length compensation for the processor socket and package delay is included in chipset routing to match electrical lengths between the chipset and the processor from the die pad of each. 11.Minimize L1, L2 and L3 lengths. Long lengths on L2 and L3 degrade effectiveness of source termination and contribute to ringback. 12.Do not change routed layers.
Platform Clock Routing Guidelines 4.1.2 HOST_CLK General Routing Guidelines • When routing the differential clocks, do not split up the two halves of a differential clock pair between layers. Route to all agents on the same physical routing layer referenced to ground. • Do not change routed layers.
Platform Clock Routing Guidelines 4.2 CLK66 Clock Group In the CLK66 clock group, the driver is the clock synthesizer 66 MHz clock output buffer, and the receiver is the 66 MHz clock input buffer at the MCH, ICH3-S, and P64H2. Figure 4-6. Topology for CLK66 L1 L2 R1 MCH, Intel® ICH3-S, Intel® P64H2 Clock Driver Table 4-4.
Platform Clock Routing Guidelines 4.2.1 CLK66 Skew Requirements Traces going to the P64H2 could have up to two connectors. Designers should keep in mind that all Total Lengths are referenced to the MCH length (“X”) and assume no connector. Each connector is equivalent to 0.60 inch of trace. Adding a single connector on the P64H2 trace would reduce the motherboard trace length by the card length “Z” to X – 0.34" – 0.60" – Z = X – 0.94" – Z (refer to Figure 4-8).
Platform Clock Routing Guidelines Figure 4-8. Example of Adding a Single Connector Total Length = X MCH 43 Ω CK408B Motherboard Trace Length = X - 0.34" - 0.60" - Z = X - 0.94" - Z Intel® P64H2 43 Ω Resistor must be within 500 mils of CK408B Z NOTES: 1. All lengths must be matched within 100 mils of target length. 2. 66 MHz clock lines routed with 25-mils isolation from any other signal. 3. Length from CK408B to MCH must be between 3 inches and 9.5 inches. 4. Each connector is equivalent to ~ 0.
Platform Clock Routing Guidelines 4.3 CLK33_ICH3-S Clock In the CLK33_ICH3-S case, the driver is the clock synthesizer PCIF 33 MHz clock output buffer, and the receiver is the PCICLK 33 MHz clock input buffer at the ICH3-S. Care must be taken to length match this 33 MHz clock with the ICH3-S 66 MHz clock. Figure 4-10. Topology for CLK33_ICH3-S Intel® ICH3-S CK408 L1 PCIF L2 PCICLK R1 Table 4-5.
Platform Clock Routing Guidelines 4.4 CLK33 Clock Group For the CLK33 clock group, the driver is the clock synthesizer 33 MHz clock output buffer, and the receiver is the 33 MHz clock input buffer at the PCI devices on the PCI cards. Figure 4-11. Topology for CLK33 to PCI Device Down L1 L2 R1 Clock Driver PCI Device, FWH, BMC, SIO . Table 4-6.
Platform Clock Routing Guidelines Figure 4-12. Topology for CLK33 to PCI Slot C L2 L1 Trace On PCI Card R1 Clock Driver PCI Device PCI Connector Table 4-7. CLK33 Routing Guidelines for PCI Slot Parameter Routing Guidelines Clock Group CLK33 Topology Point-to-Point Reference Plane Ground referenced (contiguous over entire length) Characteristic Trace Impedance (Z0) 50 Ω ± 10% Trace Width 5 mils Trace Spacing 10 mils Trace Length – L1 0.00” – 0.50” Trace Length – L2 3.00” – 9.
Platform Clock Routing Guidelines 4.5 CLK14 Clock Group The driver in the CLK14 clock group is the clock synthesizer 14.318 MHz clock output buffer (pin REF0), and the receiver is the 14.318 MHz clock input buffer at the ICH3-S, SIO, and LPC. Figure 4-13. Topology for CLK14 CK408 L1 REF0 L2 R1 Intel® ICH3-S SIO, and LPC Table 4-8.
Platform Clock Routing Guidelines 4.6 USBCLK Clock Group For the USBCLK clock group, the driver is the clock synthesizer USB clock output buffer (pin USB-48MHz), and the receiver is the USB clock input buffer at the ICH3-S (pin CLK48). Note that this clock is asynchronous to any other clock on the board. Figure 4-14. Topology for USB_CLK Intel® ICH3-S CK408 L1 USB48 MHz L2 CLK48 R1 Table 4-9.
Platform Clock Routing Guidelines 4.7 Clock Driver Decoupling The decoupling requirements for a CK408B compliant clock synthesizer are as follows: • One, 22 µF polarized (decoupling) capacitor placed close to the VDD generation circuitry. • Eleven, 0.1 µF high-frequency decoupling capacitors placed close to the VDD pins on the clock driver. • Three, 0.1 µF high-frequency decoupling capacitors placed close to the VDDA pins on the clock driver.
Platform Clock Routing Guidelines 4.8 Clock Driver Power Delivery Designers must take special care to provide a quiet VDDA supply to the Ref VDD, VDDA and the 48 MHz VDD. These VDDA signals are especially sensitive to switching noise induced by the other VDDs on the clock chip. They are also sensitive to switching noise generated elsewhere in the system such as the processor voltage regulator.
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System Bus Routing Guidelines System Bus Routing Guidelines 5 This chapter covers the system bus source synchronous (data, address, and associated strobes) and common clock signal routing. Table 5-1 lists the signals and their corresponding signal types. Table 5-1.
System Bus Routing Guidelines Figure 5-1. Dual Processor System Bus Topology Motherboard Trace 3.0 – 7.0" Package Trace 3.0 – 6.5" Package Traces MCH Processor 1 Processor 0 Refer to Table 5-2 for a summary of the dual-processor system bus routing recommendations. Use this as a quick reference only. The following sections provide more detailed information for each parameter. Intel strongly recommends simulation of all signals to ensure the design meets setup and hold times. Table 5-2.
System Bus Routing Guidelines 5.1 Routing Guidelines for the AGTL+ Source Synchronous 2X and 4X Groups The 4X group of signals uses four times the frequency of the base clock: 400 MHz or 533 MHz. The 2X group uses twice the frequency of the base clock: 200 MHz or 266 MHz. The 2X and 4X signals are listed in Table 5-3. Table 5-4 defines the 2X and 4X signals with their associated strobes. Table 5-3. 2X and 4X Signal Groups 2X Group 4X Group A[35:3]# HD[63:0]# REQ[4:0]# DBI[3:0]# Table 5-4.
System Bus Routing Guidelines 5.2 Routing Guidelines for Common Clock Signals Table 5-5 lists the common clock signals. Table 5-5. AGTL+ Common Clock I/O Signals Signal Types Signals RESET#1, Input BPRI#, BR[3:1]#, DEFER#, RS[2:0]#, RSP#, TRDY# I/O ADS#, AP[1:0]#, BINIT#, BNR#, BR0#, DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR# NOTES: 1. RESET# has additional requirements in the ITP700 Debug Port Design Guide.
System Bus Routing Guidelines 5.2.3 BR[3:0]# Routing Guidelines Connect BR[3:0]# as shown in Figure 5-3. The total bus length must be less than 20.2 inches. BR3# and BR2# are not used and are pulled to VCC_CPU. The designer may pull-up BR[3:2] independantly instead of tying the lines between the processors. Figure 5-3.
System Bus Routing Guidelines 5.3 Routing Guidelines for Asynchronous GTL+ and Miscellaneous Signals Table 5-7 enumerates the remainder of the processor signals discussed in this document. Table 5-7.
System Bus Routing Guidelines 5.3.1 Power Good Follow the topology shown in Figure 5-4 when routing power good. Connect the processor PWRGOOD pin to the ICH3-S CPUPWRGD pin. You may choose to isolate power good for each voltage regulator and processor pair to recognize individual voltage regulator failures. Figure 5-4. Topology for PWRGOOD (CPUPWRGOOD) VCC_CPU Processor 0 300 Ω ± 5% Processor 1 0.1" – 9.0" 0.1" – 3.0" Intel® ICH3-S 0.1" – 9.0" NOTES: 1. Trace Z0 = 50 Ω 2.
System Bus Routing Guidelines 5.3.2.1 Proper THERMTRIP# Usage To protect the processors from damage in over-temperature situations, power to the processor core must be removed within 0.5 seconds of the assertion of THERMTRIP#. If power is applied to a processor when no thermal solution is attached, normal leakage currents causes the die temperature to rapidly rise to levels at which permanent silicon damage is possible. This high temperature causes THERMTRIP# to go active.
System Bus Routing Guidelines 5.3.5 TESTHI[6:0] Routing Guidelines All TESTHI[6:0] pins must be connected to VCC_CPU via pull-up resistors with a pull-up value within 20% of the signal impedance (50 Ω ± 20%). TESTHI[3:0] may all be tied together and pulled up to VCC_CPU with a single, 50 Ω ± 20% resistor if desired. TESTHI[6:5] may also be tied together and pulled up to VCC_CPU with a single 50 Ω ± 20% resistor.
System Bus Routing Guidelines 5.3.6.1 Voltage Translation for INIT# A voltage translator circuit is required for the INIT# signal for all platforms that use the FWH. The required routing topology for INIT# is given in Figure 5-8. Do not route a stub when routing to the processors. Figure 5-9 shows the voltage translator circuit. Figure 5-8. INIT# Routing Topology VCC_CPU FW H 200 Ω ± 5% Processor 0 Processor 1 0.1" – 9.0" 0.1" – 3.0" Intel® ICH3-S 0.1" – 9.0" Voltage Translator 0.1" – 9.
System Bus Routing Guidelines 5.4 Intel® Xeon™ Processor with 533 MHz System Bus and Intel® Xeon™ Processor with 512-KB L2 Cache The following sections describe the differences between the Intel Xeon processor with 512-KB L2 cache (INT-mPGA package) and Intel Xeon processor with 533 MHz system bus (FC-mPGA2 package) that require special platform design consideration. Each section also provides design guidelines addressing how to support both processor packages. 5.4.
System Bus Routing Guidelines 5.5 SMBus Implementation Intel Xeon processors with 512-KB L2 cache contain SMBus devices (i.e., PIROM, Scratch EEPROMs, and thermal sensor). Intel Xeon processors with 533 MHz system bus do not contain these SMBus devices. The following sections provide guidelines for designing a system to operate with both processors with respect to these SMBus features. 5.5.
System Bus Routing Guidelines Table 5-9. Functionality for SMBus and Thermal Diode Pins Signal (Pin) Intel® Xeon™ Processor with 512-KB L2 Cache (INT-mPGA) Intel® Xeon™ Processor with 533 MHz System Bus (FC-mPGA2) THERMDA1 (Pin Y27) N/C: Not used by processor Output: Provides access to anode of thermal diode. THERMDC1 (Pin Y28) N/C: Not used by processor Output: Provides access to cathode of thermal diode.
System Bus Routing Guidelines Figure 5-10.
System Bus Routing Guidelines The SCLK, SDATA, and ALRT# must not exhibit increased leakage current when the VDD supply is grounded. If this is the case, then the motherboard pull-up resistance needs to be evaluated for acceptable VIHMIN levels due to the increased leakage current. Figure 5-11. Circuit Implementation for Hardware-Based SMBus Selection Using FET SM_VCC Use any Combination of resistors for addresses.
System Bus Routing Guidelines 5.5.2.2 Firmware Selection of SMBus Thermal Devices This section describes a firmware method for supporting either the Intel Xeon processor with 512-KB L2 cache or the Intel Xeon processor with 533 MHz system bus. This method is based on the thermal sensor implementation illustrated in Figure 5-12. The board designer can route each processor’s SMB_PRT to an ICH3-S GPIO pin, Baseboard Management Controller GPIO pin, or any other ASIC or microcontroller.
System Bus Routing Guidelines 5.5.3 Thermal Sensor Selection Figure 5-10 illustrates an example implementation where the same thermal sensor device used on the Intel Xeon processor with 512-KB L2 cache (See Table 5-10 for details) is also placed on the motherboard to provide equivalent thermal sensor operation between Intel Xeon processor with 512-KB L2 cache and Intel Xeon processor with 533 MHz system bus.
System Bus Routing Guidelines 5.5.5 Alternative Method to Obtain PIROM Data Since the Intel Xeon processor with 533 MHz system bus does not contain a PIROM device, systems must not rely on these data contents. However, some of the PIROM data field contents may be obtained by alternative methods using either the CPUID instruction or by reading certain processor mode-specific registers. Table 5-11 summarizes the information available and the method for obtaining the data.
System Bus Routing Guidelines 5.6.2 SKTOCC# Signal Routing Guidelines The SKTOCC# signal is an output from the processor used as an indication of whether a processor is installed or not. It is asserted low when a processor is installed in the socket, and floats when no processor is present. If this signal is used on the board, the designer can use a pull-up to prevent floating.
System Bus Routing Guidelines The BSEL0 output from the processor 0 socket is also connected to the CK408B and GPI to program both devices to operate at either 100 MHz or 133 MHz based on the processor installed. Table 5-13 summarizes the operation of the reference circuit. Figure 5-13. BSEL[1:0] Reference Circuit Processor 0 Processor 1 SKTOCC 0 VID[4:0] CK408B S1 SKTOCC 1 BSEL[0:1] VID[4:0] BSEL[0:1] 55 BSEL0 Any GPI +3.3V +3.3V 1 kΩ +3.3V 1 kΩ +3.
Memory Interface Routing Guidelines Memory Interface Routing Guidelines 6 The E7500 chipset MCH and E7501 chipset MCH memory interface consist of two DDR memory channels that operate in “lock-step.” Each channel consists of 64 data and eight ECC bits. Logically, this is one, 144-bit wide memory bus; electrically, each channel is separate. The E7501 chipset MCH supports an additional feature to the E7500 chipset MCH: DDR266.
Memory Interface Routing Guidelines 6.1 DDR Overview Figure 6-1 and Figure 6-2 show both channels being routed to a single “bank” of eight DIMMs. The DIMMs are physically interleaved. Intel recommends using this interleaving, starting with Channel B closest to the MCH, for optimal routing. The platform requires DDR DIMMs to be populated in-order, starting with the DIMMs furthest from the MCH in a “fill-farthest” approach (see Figure 6-1 and Figure 6-2).
Memory Interface Routing Guidelines Certain combinations of DIMM types in 3-DIMM and 4-DIMM per channel systems have been found to violate the JEDEC write ring back measurement specification. 1-DIMM and 2-DIMM per channel systems do not violate the JEDEC write ring back specification.
Memory Interface Routing Guidelines 6.1.1 DDR Channel Impedance Requirements The DDR channel requires different widths for different signals depending on the configuration used. Table 6-2 indicates the impedances for the trace widths used for routing the data bus. Table 6-2. Trace Width to impedance Requirements Trace Width Nominal Trace Impedance (Z0) 4 mil 55 Ω ± 10% 5 mil 50 Ω ± 10% 6 mil 45 Ω ± 10% 7.5 mil 40 Ω ± 10% Figure 6-5.
Memory Interface Routing Guidelines 6.2 Source Synchronous Signal Group Routing The MCH source synchronous signals are divided into groups consisting of data bits (DQ) and check bits (CB). An associated strobe (DQS) exists for each DQ and CB group, as shown in Table 6-3. The MCH supports both x4 and x8 devices, and the number of signals in each data group depends on the type of devices that are populated.
Memory Interface Routing Guidelines Table 6-4.
Memory Interface Routing Guidelines 6.3 Command Clock Routing Only one differential clock pair is routed to each DIMM connector because the MCH only supports registered DDR DIMMs. All CMDCLK/CMDCLK# termination is on the DIMM modules. Route each clock and its compliment adjacent to each other. The two complimentary signals (e.g., CMDCLK_x0 and CMDCLK_x0#) must be length matched to each other within ± 2 mils and must be routed on the same layer.
Memory Interface Routing Guidelines Figure 6-8. Trace Width/Spacing for CMDCLK/CMDCLK# Routing Layer 1 Dielectric 9.6 mil Dielectric CMDCLK Layer 2 Core 5.2 mil CMDCLK# Signal 1.4 mil (1 oz) Core Layer 3 Ground Dielectric Layer 4 CMDCLK# Dielectric 4.3 mil CMDCLK 1.4 mil (1 oz) Signal 1.4 mil (1 oz) Signal 1.4 mil (1 oz) Main Core Core 14.0 mil CMDCLK Layer 5 CMDCLK# Layer 6 Ground Dielectric Dielectric 4.3 mil Core 5.2 mil 1.
Memory Interface Routing Guidelines 6.4 Source Clocked Signal Group Routing The MCH drives the command clock signals and the source-clocked signals together. That is, the MCH drives the command clock in the center of the valid window, and the source-clocked signals propagate with the command clock signal. Therefore, the critical timing is the difference between the command clock flight time and the source clocked signal flight time. The absolute flight time is not as critical.
Memory Interface Routing Guidelines 6.5 Chip Select Routing The MCH provides eight chip select signals. Two chip selects must be routed to each DIMM (one for each side). Chip selects for each DIMM must be length matched to the corresponding clock within ± 875 mils and require parallel termination resistors (Rtt) to DDR VTERM. Table 6-7.
Memory Interface Routing Guidelines 6.6 Clock Enable Routing The MCH provides a single clock enable (CKE) signal. This signal is used during initialization to indicate that valid power and clocks are being applied to the DIMMs. Because the CKE signal has higher loading, it requires a lower impedance. The recommended impedance for the CKE signal is 40 Ω. This can be achieved using a 7.5-mil wide trace on the recommended stack-up (refer to Figure 6-5).
Memory Interface Routing Guidelines 6.7 DC Biasing Signals The DC Biasing signals are DDR signals which are not channel configuration specific. Table 6-9 documents all of these signals, indicating the new names for many of these signals. Many of the E7501 chipset MCH usages have been changed from the original E7500 chipset MCH recommendation. This section documents a compatibility layout for both E7500 chipset MCH and E7501 chipset MCH with stuffing options, dependant on which MCH is used. Table 6-9.
Memory Interface Routing Guidelines 6.7.1 Receive Enable Signal The E7500 chipset MCH uses the “receive enable” signal to determine the approximate round-trip flight time (command flight + data flight) to the DIMMs. Two pins exist on the MCH to facilitate the use of receive enable. RCVENOUT# is an output of the MCH and RCVENIN# is an input to the MCH. The board designer must connect RCVENOUT# to RCVENIN#. The length of the RCVEN# signal trace must be 15 inches ± 100 mils.
Memory Interface Routing Guidelines 6.7.2 DDR Comp The MCH uses DDRCOMP_x to calibrate the DDR channel buffers. This is periodically done by sampling the DDRCOMP pin on the MCH. The E7500 chipset MCH calibrates using a 6.98 Ω ± 1% pull-up to VTERM. The E7501 chipset MCH calibrates using a 24.9 Ω ± 1% pulldown to ground. This can be implemented by routing a 15-mil wide trace to a resistive network where the correct pull-up or pull-down is stuffed and the other is not populated, as depicted in Figure 6-13.
Memory Interface Routing Guidelines 6.7.3 DDRVREF and ODTCOMP The DDR system memory reference voltage (VREF) is used by the DRAM devices and the MCH to determine the logic level being driven on the data, command, and control signals. VREF of the receiving device must track changes in VTERM to maximize DDR interface margin. However, VTERM and VREF cannot be the same power plane due to the sensitivity of the DRAM VREF buffers to the termination plane noise.
Memory Interface Routing Guidelines ODTCOMP, a redefined pin on the E7501 chipset MCH, is connected to the E7500 chipset MCH DVREF_A5 pin. The E7501 chipset MCH includes active read-cycle termination for all source synchronous signals (DQ and DQS signals). This On-Die-Termination (ODT) serves to control signal swing at the MCH receiver during read cycles. It does not function during write cycles. The ODT circuit has the effect of a weak pull-up of 200 Ω ± 15% to VTT.
Memory Interface Routing Guidelines 6.7.4 DDRCVO The MCH uses a compensation signal to adjust buffer characteristics and output voltage swing over temperature, process, and voltage skew. Calibration is done periodically by sampling the DDRCVO_x pins on the MCH. Place the voltage divider network (Figure 6-17) within 1 inch of the MCH. When an E7501 chipset MCH is used on a compatible board, all of the components on the DDRCVOL circuit do not need to be stuffed, as shown in Figure 6-17.
Memory Interface Routing Guidelines 6.8 DDR Signal Termination and Decoupling Place a 1.25 V termination plane on the top layer, just beyond (within 0.5 inch) the DIMM connector furthest from the MCH on each channel, as shown in Figure 6-18. The VTERM island must be at least 50-mils wide. Use this termination plane to terminate all DIMM signals, using one Rtt resistor per signal. Decouple the VTERM plane using one 0.1 µF decoupling capacitor per two termination resistors.
Memory Interface Routing Guidelines 6.9 2.5 V Decoupling Requirements Decouple the DIMM connectors as shown in Figure 6-19. Place six ceramic 0.1 µF (0603) capacitors between each pair of DIMM connectors. Place ten Tantalum 100 µF capacitors around the DIMM connectors per channel, keeping them within 0.5 inch of the DIMM connectors. Figure 6-19. DIMM Decoupling 10 Tantulum 100 µF Capacitors/Channel Around DIMMs DIMM DIMM DIMM DIMM 2 Vias Per Capacitor to Internal Ground Plane 6 Ceram ic 0.
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Hub Interface 7 Hub Interface 7.1 Signal Naming Convention Figure 7-1 has the Hub Interface 2.0 and Hub Interface 1.5 signal naming convention for each component. This figure is intended to give a quick naming cross reference to designers. The specific guidelines and implementation on these signals are given in the following sections. Note that throughout the document, the “x” part of the MCH signal has been dropped for simplicity. Figure 7-1.
Hub Interface 7.2 Hub Interface 2.0 Implementation The MCH and P64H2 ballout assignments are optimized to simplify the hub interface routing between these devices. To allow for greater flexibility in design, a connector can be placed on the interface to access a HI2.0 agent that resides on an adapter card. The typical card implementation uses an extension to the 3.3 V PCI-64 connector that provides an additional 70 pins for HI2.0.
Hub Interface Route the Hub Interface 2.0 data signal traces 5-mils wide using the recommended stack-up. There must be 15-mils spacing between data signal traces (5/15). Each strobe signal must have a minimum of 35 mils of spacing from any adjacent signals to minimize effects that cause signal degradation. To break out of the MCH and P64H2 package, the hub interface data signals can be routed 5/5. The signals must separate to 5/15 (or strobes to 5/35) within 0.5 inch of the package. Hub Interface 2.
Hub Interface Hub Interface 2.0 has a minimum trace length requirement of 3 inches, and a maximum trace length requirement of 20 inches for a device on the motherboard implementation for all hub interface signals (using an internal routing layer on the recommended stack-up). However, for a device on an adapter card plugged in a Hub Interface 2.0 connector, the maximum motherboard trace length is 14 inches. (3 inches for card routing and 3 inches for connector skew.
Hub Interface 7.2.2 Hub Interface 2.0 Generation/Distribution of Reference Voltages The nominal Hub Interface 2.0 reference voltage is 0.350 V ± 5%. Each Hub Interface 2.0 on the MCH has a dedicated HIVREF pin to sample this reference voltage. Similarly, the P64H2 has a dedicated reference voltage pin. In addition to the reference voltage, a reference swing voltage must be supplied to control buffer voltage swing characteristics. The nominal Hub Interface 2.0 reference swing voltage should be 0.
Hub Interface 7.2.3 Hub Interface 2.0 Resistive Compensation The hub interface uses a resistive compensation signal (HIRCOMP_x) to compensate buffer characteristics across temperature, voltage, and process. The HIRCOMP_x resistor values are given in Table 7-5. Figure 7-6 shows the RCOMP_x circuits. The length of the trace from the component to the pull-up must be less than 1 inch and have a trace impedance of 50 Ω ± 10%. Table 7-5. Hub Interface 2.
Hub Interface 7.3 Hub Interface 1.5 Implementation The Hub Interface 1.5 signals HI[7:0] are associated with HI_STBS/HI_STBF. For those familiar with Hub Interface 1.0, HI_STBF and HI_STBS are called HI_STB# and HI_STB, respectively. Figure 7-7. 8-Bit Hub Interface 1.5 Routing HI_STBF HI_STBS Intel® ICH3-S MCH HI[11:0] CLK66 CLK66 CLK Synthesizer This section documents the routing guidelines for the Hub Interface 1.5 that is responsible for connecting the MCH to the ICH3-S. Hub Interface 1.
Hub Interface Route the Hub Interface 1.5 data signal traces 5 mils wide using the recommended stack-up. There must be 15 mils spacing between data signal traces (5/15). Each strobe signal must have a minimum of 35 mils of spacing from any adjacent signals to minimize effects that cause signal degradation. To break out of the MCH and ICH3-S package, the hub interface data signals can be routed 5/5. The signals must separate to 5/15 (or strobes to 5/35) within 0.5 inch of the package. For Hub Interface 1.
Hub Interface The values of R1, R2, R3, R4 and R5 must be rated at ± 1% tolerance. The selected resistor values must also ensure that the reference voltage and reference swing voltage tolerance are maintained over the input leakage specification. A 0.1 µF capacitor (C1 in Figure 7-8) should be placed within 0.5 inch of each resistor divider, and a 0.01 µF bypass capacitor (C2 in Figure 7-8) should be placed within 0.25 inch of reference voltage pins.
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Intel® 82870P2 (P64H2) Intel® 82870P2 (P64H2) 8 The 82870P2 (P64H2) is a peripheral chip that performs PCI/PCI-X bridging functions between the Hub Interface 2.0 and the PCI bus. The P64H2 is an integral part of the E7500/E7501 chipset, bridging the MCH and the PCI/PCI-X bus. On the primary bus, the P64H2 uses a 16-bit data bus to interface with the Hub Interface 2.0, and on the secondary bus, it supports two, 64-bit PCI/PCI-X bus segments.
Intel® 82870P2 (P64H2) 8.1.1 General PCI-X Routing Guidelines Most PCI-X signals are timing critical. The timing critical signals have length restrictions for propagation, setup, and hold requirements. Table 8-2 itemizes all timing critical and some of the non-critical signals. All of the topologies in the following sections itemize the lengths for the timing critical signals in configurations which Intel simulated. Table 8-2.
Intel® 82870P2 (P64H2) 8.1.2 PCI/PCI-X Routing Requirements (No Hot-Plug Switch) The P64H2 supports a large number of PCI/PCI-X configurations. The basic topology of the bus is shown in Figure 8-1. Multiple slots are connected in a daisy chain topology with the device(s) down on the motherboard at the end of the daisy chain. Table 8-4 documents the lengths for the configurations Intel simulated.
Intel® 82870P2 (P64H2) 8.1.3 PCI/PCI-X Hot-Plug Switch Routing Requirements The P64H2 supports a large number of PCI/PCI-X Hot-Plug serial mode configurations. These configurations require the usage of a Hot-Plug switch. The Hot-Plug topology of the bus is shown in Figure 8-2. Hot-Plug switches are connected in a daisy chain topology with the device(s) down on the motherboard at the end of the daisy chain. Table 8-5 documents the lengths for the configurations that Intel simulated. Figure 8-2.
Intel® 82870P2 (P64H2) 8.1.4 Riser Card Topologies The following guidelines are for systems that use a PCI-X riser card. A PCI-X riser card is a card containing PCI-X slots that is plugged into a PCI-X connector. These guidelines assume a PCI/PCI-X riser card with a 0.7 – 1.0 inch long trace length between slots. These simulations require the clocks for each device and riser card slot to be tuned within 500 ps, or 2.85 in, of each other.
Intel® 82870P2 (P64H2) Figure 8-4 shows a PCI-X channel with a device down before a riser card connector. If a one-slot riser is used, the channel can be run up to PCI-X 100 MHz. If a three-slot riser is used, the channel can be run up to PCI-X 66 MHz. Figure 8-4. Device Down before PCI-X Riser Card Topology ® Intel P64H2 P64H2 to Device Device Device to Riser Riser Table 8-7.
Intel® 82870P2 (P64H2) Figure 8-6 shows a device down before a PCI-X riser card. Place a 22 Ω series resistor on the stub to riser leg, close to the riser itself. This topology can only be run at PCI 66 MHz or below. Figure 8-6. Device Down with Stub before PCI-X Riser Card Topology P64H2 to Stub ® Intel P64H2 Stub to Riser Riser Stub to Device Device Table 8-9.
Intel® 82870P2 (P64H2) 8.1.6 Clock Configuration All PCI clocks must be disabled in the BIOS for any unused/unpopulated PCI/PCI-X slots. The PxPCLKO[5:0] pins can each be disabled by writing to the Disable PCLKOUT 5 – 0 bits (DPCLK, bits 15:10, configuration register offset 40h in each bridge). These clocks function the same in serial and dual-slot parallel modes.
Intel® 82870P2 (P64H2) 8.1.7 Loop Clock Configuration You must tie PxPCLKO6 to PxPCLKI because this clock always runs and is needed by the internal PCI PLLs to properly align output signals with the external clocks by removing clock insertion delay. The PxPCLKO6 signal does not have to be routed through a bus switch before returning to PxPCLKI. Figure 8-10. Loop Clock Topology PxPCLKO6 Lfbo Intel® P64H2 33 Ω Lfbi PxPCLKI Table 8-13.
Intel® 82870P2 (P64H2) 8.1.8 IDSEL Implementation Designers should use a 100 Ω series coupling resistor on the IDSEL signal when implementing PCI-X. Though the PCI-X Addendum PCI Local Bus Specification, Revision 1.0 calls for a 2 kΩ resistor, the current specification, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a allows for other resistor values. See Figure 8-11 for an example of how to implement the coupling resistor. IDSEL mapping per P64H2 pin is arbitrary.
Intel® 82870P2 (P64H2) 8.2 Hot-Plug Implementation The P64H2 contains two integrated Hot-Plug controllers (one per PCI/PCI-X interface) that operate independently. These integrated controllers can be individually disabled or configured to operate in one of the three defined modes of operation: single-slot parallel mode, dual-slot parallel mode, and serial mode. This section describes each of these three modes of operation, as well as switch and button implementation and the Hot-Plug Standard Usage Model.
Intel® 82870P2 (P64H2) 8.2.1.2 Hot-Insertions 1. User selects an empty, disabled slot and opens MRL. 2. User inserts add-in card, closes MRL, and attaches cables to card. 3. User requests that slot be enabled. a. User requests that slot be enabled via a software user interface. b. Power Indicator LED next to slot blinks while system software validates request. – OR – a. User presses momentary Attention Button at that slot. b. Software interprets change on HxPRSNT# pin as a push button event.
Intel® 82870P2 (P64H2) 8.2.2.1 Manually-Operated Retention Latch Sensor The HxSWITCH signal is monitored by the Hot-Plug controller to determine whether or not a slot should be powered. The MRL sensor, or slot switch, should be connected to the HxSWITCH pin such that it drives this pin low to indicate that the slot is closed and can be powered on. When the signal is driven high, it indicates that the slot should immediately be powered off.
Intel® 82870P2 (P64H2) 8.2.2.2 Optional Attention Button The Attention Button state is observed on the slot-specific HxPRSNT1# pin. An exclusive-OR (XOR) gate is inserted between the Slot Present signal and the Hot-Plug controller as shown in Figure 8-13. A momentary contact button is connected to the other input of the XOR gate. When the button is in the released state, the Slot Present signal is unaffected.
Intel® 82870P2 (P64H2) 8.2.5 Disabling/Enabling an Intel® P64H2 Hot-Plug Controller 8.2.5.1 Hot-Plug Strapping Options The HPx_SLOT [2:0] strapping pins are used to enable and disable the Hot-Plug controller. Table 8-15 lists the strapping options associated with these pins, and the modes of operation they enable. Table 8-15.
Intel® 82870P2 (P64H2) 8.2.6.3 Debounced Hot-Plug Switch Input The switch inputs (PxIRQ15 in this case—see Table 8-17) to the Hot-Plug controller do not require any debouncing logic in this mode. This logic is contained within the P64H2. The POWERON value for this input is determined by BIOS. However, it is recommended that BIOS define a logic 0 to represent that the slot can be powered on. 8.2.6.
Intel® 82870P2 (P64H2) Figure 8-15. Multiplexer Circuit Example This signal could be pulled up to VCC_3.3 depending on the strapping need. 1 kΩ 2:1 Multiplexer S1 PCIXCAP1 / PCIXCAP2 D (PCIXCAP1 / PCIXCAP2) or HPxSLOT Strap VCC_3.3 S2 C Truth Table C (PWROK) D 0 HPxSLOT Strap 1 PCIXCAP1 / PCIXCAP2 8.2 kΩ ENB PWROK 8.2.6.6 Hot-Plug Multiplexed Signals in Single-Slot Parallel Mode The Hot-Plug signals that connect to the controller are shown in Table 8-17.
Intel® 82870P2 (P64H2) Table 8-18. Hot-Plug Controller Output Signal Reset Values Signals PxGNT[5:3] 8.2.6.7 Reset Value 011 HPx_SOC 0 HPx_SIC 0 HPx_SOL 0 HPx_SOLR 0 HPx_SOD 0 HPx_SORR# 1 HPx_SOR# 0 HPx_SIL# 1 SMBus Address Considerations In single-slot parallel mode, the SMBus address strap pins listed in Table 8-14 are multiplexed with Hot-Plug control signal HxRESETA#. Therefore, it is recommended that the following technique be used for determining an SMBus address.
Intel® 82870P2 (P64H2) 8.2.6.9 Reference Schematic for Single-Slot Parallel Mode Note that the following schematic is based on definition and simulation of the P64H2. This schematic has not been fully validated. Figure 8-17. Reference Schematic for Single-Slot Parallel Mode 33 PxPCLKO [0] CLK 33 PxPCLKO [6] Intel® P64H2 PxREQ[1:2]# should be pulled to 3.3V through 8.
Intel® 82870P2 (P64H2) 8.2.7 Dual-Slot Parallel Mode Dual-slot parallel mode is used when it is desirable to have two slots that are Hot-Pluggable. No serialization/deserialization logic is required for this mode of operation. 8.2.7.1 Required Additional Logic Dual-slot parallel mode requires a power switch to be used to turn the slot power on and off. Dualslot parallel mode also requires the use of a bus and clock switch.
Intel® 82870P2 (P64H2) 8.2.7.7 Hot-Plug Multiplexed Signals in Dual-Slot Parallel Mode The Hot-Plug signals that connect to the controller are listed in Table 8-19. In Table 8-19 the “Signal” column refers to the name of the slot pin when in dual-slot mode. The “Bus A” and “Bus B” columns represent the corresponding P64H2 pins. Table 8-19.
Intel® 82870P2 (P64H2) 8.2.7.8 SMBus Address Considerations In dual-slot parallel mode, the SMBus address strap pins in Table 8-14 are multiplexed as Hot-Plug control signals HxRESETA# and HxBUSENB#. Therefore, it is recommended that the following technique be used for determining an SMBus address. Pull the PAGNT5 (RESETA#) signals to ground through a 100 kΩ ± 5% resistor. This keeps the reset signal active until the P64H2 is ready for it to become deasserted. Pull the PAGNT4 (BUSENB#) signals to 3.
Intel® 82870P2 (P64H2) 8.2.7.9 Reference Schematic for Dual-Slot Parallel Mode Note that the following schematic is based on definition and simulation of the P64H2. This schematic has not been fully validated. Figure 8-19. Reference Schematic for Dual-Slot Parallel Mode PxPCLKO [0] PxPCLKO [1] Note * All PCI signals muxed or not need to follow PCI spec 2.2 pullup requirements 33 Intel® P64H2 3.
Intel® 82870P2 (P64H2) 8.2.8 Three or More Slot Serial Mode Serial mode allows for three to six slots to be Hot-Pluggable. This mode can also be used to enable slots that are Hot-Pluggable, and others that are not on the same PCI/PCI-X bus. 8.2.8.1 Hot-Plug and Non-Hot-Plug Combinations To accomplish Hot-Plug and non-Hot-Plug combinations, put the non-Hot-Pluggable devices on their own Hot-Plug serialization logic (for M66EN and PCIXCAP), and scan them in for software to view.
Intel® 82870P2 (P64H2) Table 8-20.
Intel® 82870P2 (P64H2) 8.2.8.8 Reference Schematic for Serial Mode The following schematic is based on definition and simulation of the P64H2. This schematic has not been fully validated. Figure 8-21. Reference Schematic for Serial Mode 7 Reset [1:4] # PCI BUS SIGNALS PCI BUS SIGNALS Some signals are bidirectional, others are not. Pull-ups are not shown for PCI Control Signals. Refer to the PCI specification for these values. 3.
Intel® 82870P2 (P64H2) 8.2.9 Intel® P64H2 PCI Interface PCIXCAP and M66EN Pins 8.2.9.1 PCIXCAP Pin Requirements During all modes of the P64H2 Hot-Plug controller operation, the P64H2 PCI/PCI-X interface pin PxPCIXCAP is not used. This pin should be tied to VCC3_3 through an 8.2 kΩ resistor to avoid having this line float. The slot-specific HxPCIXCAP1 and HxPCIXCAP2 pins should be connected to their associated slot. See Section 8.2.6, Section 8.2.7, and Section 8.2.7.
Intel® 82870P2 (P64H2) M66EN Isolation Switch Solution One possible solution to the issue described in the previous paragraphs is to place a single 5 kΩ ± 5% pull-up on the P64H2 side of the isolation logic and a 5 kΩ ± 5% pull-up on the slot side after the isolation logic, but with its own isolation switch, which uses an inverted version of the bus enable control signal. This way, when the isolation logic has the bus disconnected, the slot side will be pulled up with a 5 kΩ ± 5% resistor.
Intel® 82870P2 (P64H2) M66EN Diode Solution Another possible solution to the issue described in the previous paragraphs is to use diodes to isolate the individual slots from one another while still allowing the P64H2 to drive the M66EN signals to ground. The P64H2 PCI interface PxM66EN signal should be pulled to 3.3 V through a 100 kΩ ± 5% resistor. This signal would then be connected to the individual slots through a reverse biased diode (one diode per slot).
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I/O Controller Hub 3 (Intel® ICH3-S) I/O Controller Hub 3 (Intel® ICH3-S) 9.1 9 IDE Interface This section contains guidelines for connecting and routing the ICH3-S IDE interface. The ICH3-S has two independent IDE channels. This section provides guidelines for IDE connector cabling and motherboard design, including component and resistor placement, and signal termination for both IDE channels.
I/O Controller Hub 3 (Intel® ICH3-S) 9.1.2 Cable Detection for Ultra ATA/66 and Ultra ATA/100 The ICH3-S IDE controller supports PIO, Multi-word (8237 style) DMA, and Ultra DMA modes 0 through 5. The ICH3-S must determine the type of cable that is present to configure itself for the fastest possible transfer mode the hardware can support. An 80-conductor IDE cable is required for Ultra DMA modes greater than 2 (Ultra ATA/33). This cable uses the same 40-pin connector as the old 40-pin IDE cable.
I/O Controller Hub 3 (Intel® ICH3-S) This mechanism allows the BIOS, after diagnostics, to sample PDIAG#/CBLID#. If the signal is high, then a 40-conductor cable is present in the system and Ultra DMA modes greater than Mode 2 (Ultra ATA/33) must not be enabled. If PDIAG#/CBLID# is detected low, then an 80-conductor cable may be in the system, or there may be a 40-conductor cable and a legacy slave device (Device 1) that does not release the PDIAG#/CBLID# signal as required by the ATA/ATAPI-4 standard.
I/O Controller Hub 3 (Intel® ICH3-S) 9.2 SPKR Pin Consideration SPKR is used as both the output signal to the system speaker and as a functional strap. The strap function enables or disables the “TCO Timer Reboot function” based on the state of the SPKR pin on the rising edge of PWROK. When enabled, the ICH3-S sends an SMI# to the processor upon a TCO timer timeout. The status of this strap is readable via the NO_REBOOT bit (bit 1, D31: F0, Offset D4h).
I/O Controller Hub 3 (Intel® ICH3-S) 9.4 USB The ICH3-S contains three UHCI Host controllers. Each UHCI controller includes a root hub with two separate USB ports, for a total of six USB ports. This section provides guidelines for routing USB. 9.4.1 General Routing and Placement Use the following general routing and placement guidelines when laying out a new design. These guidelines help minimize signal quality and EMI problems. USB validation efforts have focused on a ground referenced design. 1.
I/O Controller Hub 3 (Intel® ICH3-S) 9.4.2 USB Routing Parameters Use the following separation guidelines. • Recommended trace width and separation is 5-mil trace width with 6-mil spacing (90 Ω differential impedance). • Maintain parallelism between USB differential signals, with the trace spacing needed to achieve 90 Ω differential impedance. • Use at a minimum 20-mil spacing between USB signal pair and other traces on the PCB. This helps to prevent crosstalk.
I/O Controller Hub 3 (Intel® ICH3-S) Intel® ICH3-S SMBus/SMLink Interface 9.5 The SMBus interface on the ICH3-S uses two signals, SMBCLK and SMBDATA, to send and receive data from components residing on the bus. These signals are used exclusively by the SMBus host controller. The SMBus host controller resides inside the ICH3-S. If the SMBus is used only for the SPD EEPROMs (one on each DIMM), both signals should be pulled up with a 4.7 kΩ ± 5% resistor to VCC3_3.
I/O Controller Hub 3 (Intel® ICH3-S) 9.5.1 SMBus Design Considerations There is not a single SMBus design solution that will work for all platforms. One must consider the total bus capacitance and device capabilities when designing SMBus segments. Routing SMBus to the PCI slots makes the design process even more challenging since they add so much capacitance to the bus. This extra capacitance has a large affect on the bus time constant which in turn affects the bus rise and fall times.
I/O Controller Hub 3 (Intel® ICH3-S) 9.5.3 High Power/Low Power Mixed Architecture This design allows for current isolation of high and low current devices while also allowing SMBus devices to communicate while in S5. VCC_SUSPEND leakage is minimized by keeping non-essential devices on the core supply. This is accomplished by the use of a “FET” to isolate the devices powered by the core and suspend supplies. See Figure 9-8. Figure 9-8.
I/O Controller Hub 3 (Intel® ICH3-S) 9.5.4 Calculating The Physical Segment Pull-Up Resistor The following tables are provided as a reference for calculating the value of the pull-up resistor that may be used for a physical bus segment. If any physical bus segment exceeds 400 pF, then a bus bridge device like the Phillips PCA9515 must be used to separate the physical segment into two segments that individually have a bus capacitance less than 400 pF. Table 9-1. Bus Capacitance Reference Chart Device No.
I/O Controller Hub 3 (Intel® ICH3-S) 9.6 Real Time Clock (RTC) The ICH3-S contains a real time clock (RTC) with 256 bytes of battery-backed SRAM. The internal RTC module provides two key functions: keeping date and time, and storing system data in its RAM when the system is powered down. The ICH3-S uses a crystal circuit that generates a low-swing 32 kHz input sine wave. The RTCX1 input is amplified and driven back to the crystal circuit via the RTCX2 signal.
I/O Controller Hub 3 (Intel® ICH3-S) 9.6.1 RTC External Circuit The ICH3-S RTC module requires an external oscillating source of 32.768 kHz connected on the RTCX1 and RTCX2 balls. Figure 9-11 documents the external circuitry that comprises the oscillator of the ICH3-S RTC. Figure 9-11. Example RTC External Circuitry RTCRST# 8.2 kΩ 2.2 µF RTC External RTCRST# Circuit 3.3V Sus VCCRTC RTCX2 1 µF C1 18 pF R1 10 MΩ 32.768 kHz Xtal Vbatt C3 0.047 µF RTCX1 C2 18 pF R2 10 MΩ VBIAS NOTES: 1.
I/O Controller Hub 3 (Intel® ICH3-S) 9.6.3 External Capacitors To maintain the RTC accuracy, the external capacitor C3 must be 0.047 µF, and capacitor values C1 and C2 should be chosen to provide the manufacturer's specified load capacitance (Cload) for the crystal when combined with the parasitic capacitance of the trace, socket (if used), and package.
I/O Controller Hub 3 (Intel® ICH3-S) 9.6.4 RTC Layout Considerations Since the RTC circuit is very sensitive and requires high accurate oscillation, reasonable care must be taken during layout and routing of the RTC circuit. Some recommendations are: • Reduce trace capacitance by minimizing the RTC trace length. ICH3-S requires a trace length less than 1 inch on each branch (from crystal's terminal to RTCXn ball).
I/O Controller Hub 3 (Intel® ICH3-S) Probing VBIAS requires the same technique as probing the RTCX1 and RTCX2 signals (using Op-Amp). See application note AP-728, Intel® ICH Family Real Time Clock (RTC) Accuracy and Considerations Under Test Conditions, for further details on measuring techniques. Note: 9.6.7 VBIAS is also very sensitive to environmental conditions. SUSCLK SUSCLK is a square waveform signal output from the RTC oscillation circuit.
I/O Controller Hub 3 (Intel® ICH3-S) 9.7 Internal LAN Layout Guidelines The ICH3-S provides various options for integrated LAN capability. The platform supports several components depending on the target market. The guidelines use the term 82562ET to refer to both the Intel® 82562ET, and the Intel® 82562EM. The 82562EM is specified in those cases where a difference exists.
I/O Controller Hub 3 (Intel® ICH3-S) 9.7.1 LCI (LAN Connect Interface) Guidelines This section contains guidelines on how to implement a PLC (Platform LAN Connect) device on a system motherboard using LCI. It should not be treated as a specification, and the system designer must ensure through simulations or other techniques that the system meets the specified timings. Special care must be given to matching the LAN_CLK traces to those of the other signals, as shown below.
I/O Controller Hub 3 (Intel® ICH3-S) 9.7.1.2 LCI Routing Parameters Route the LCI signals carefully on the motherboard to meet the timing and signal quality requirements of this interface specification. The board designer should simulate the board routing to verify that the specifications are met for flight times and skews due to trace mismatch and crosstalk. Table 9-4. LCI Routing Parameter Summary Parameter Requirements Trace Impedance (Z0) 60 Ω ± 15% due to signal integrity requirements.
I/O Controller Hub 3 (Intel® ICH3-S) 9.7.2 General LAN Routing Guidelines and Considerations 9.7.2.1 General Trace Routing Considerations Trace routing considerations are important to minimize the effects of crosstalk and propagation delays on sections of the board where high-speed signals exist. Signal traces should be kept as short as possible to decrease interference from other signals, including those propagated through power and ground planes.
I/O Controller Hub 3 (Intel® ICH3-S) 9.7.2.2 Trace Geometry and Length The key factors in controlling trace EMI radiation are the trace length, and the ratio of trace-width to trace-height above the ground plane. To minimize trace inductance, high-speed signals and signal layers that are close to a ground or power plane should be as short and wide as practical. Ideally, this trace width to height above the ground plane ratio is between 1:1 and 3:1.
I/O Controller Hub 3 (Intel® ICH3-S) 9.7.2.5 General Power and Ground Plane Consideration To properly implement the common mode choke functionality of the magnetics module, the chassis or output ground (secondary side of transformer) should be separated from the digital or input ground (primary side) by a physical separation of 100 mils minimum. Figure 9-16. Ground Plane Separation 0.
I/O Controller Hub 3 (Intel® ICH3-S) 9.7.2.6 Board Design The following recommendations are based on a ground referenced design. • Top Layer Routing Sensitive analog signals are routed completely on the top layer without the use of vias. This allows tight control of signal integrity, and removes any impedance inconsistencies due to layer changes. • Ground Plane A layout split (100 mils) of the ground plane under the magnetics module between the primary and secondary side of the module is recommended.
I/O Controller Hub 3 (Intel® ICH3-S) • Use of an inferior magnetics module. The magnetics modules that we use have been fully tested for IEEE PLC conformance, long cable BER, and for emissions and immunity. (Inferior magnetics modules often have less common-mode rejection and/or no auto transformer in the transmit channel.) • Use of an 82555 or 82558 physical layer schematic in a PLC design. The transmit terminations and decoupling are different. There are also differences in the receive circuit.
I/O Controller Hub 3 (Intel® ICH3-S) 9.7.3 Intel® 82562ET/EM Guidelines For documentation on LAN, refer to Section 1.2. For correct LAN performance, designers must follow the general guidelines outlined in Section 9.7.2. Additional guidelines for implementing an 82562ET or 82562EM platform LAN connect component are provided in the following sections. 9.7.3.1 Guidelines for Intel® 82562ET/EM Component Placement Component placement can affect signal quality, emissions, and temperature of a board design.
I/O Controller Hub 3 (Intel® ICH3-S) 9.7.3.3 Intel® 82562ET/EM Termination Resistors The 100 Ω ± 1% resistor used to terminate the differential transmit pairs (TDP/TDN), and the 121 Ω ± 1% resistor used to terminate the differential receive pairs (RDP/RDN) should be placed as close to the Platform LAN connect component (82562ET or 82562EM) as possible. This is due to the fact that these resistors are terminating the entire impedance that is seen at the termination source (i.e.
I/O Controller Hub 3 (Intel® ICH3-S) Distance from Magnetics Module to RJ45 (Distance A) The distance A in Figure 9-18 should be given the highest priority in board layout. The distance between the magnetics module and the RJ45 connector should be kept to less than 1 inch of separation. The following trace characteristics are important and should be observed: • Differential Impedance: The differential impedance should be 100 Ω.
I/O Controller Hub 3 (Intel® ICH3-S) 9.7.5 Terminating Unused Connections In Ethernet designs, it is common practice to terminate unused connections on the RJ45 connector and the magnetics module to ground. Depending on overall shielding and grounding design, this may be done to the chassis ground, signal ground, or a termination plane. Care must be taken when using various grounding methods to insure that emission requirements are met.
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Debug Tools Debug Tools 10 The debug port design information can be found in a separate document. The routing of the signals, the signal levels, and all other information required to develop a debug port on this platform can be found in the ITP700 Debug Port Design Guide. 10.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging the system bus of Intel Xeon processors. Contact Tektronix, Inc.
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Platform Power Delivery Guidelines 11 Platform Power Delivery Guidelines This chapter provides an example for board power delivery and the power requirements for some board components. 11.1 Customer Reference Board Power Delivery Figure 11-1 shows the power delivery architecture for the E7501 Chipset Customer Reference Board. Figure 11-1. Power Delivery Example CPU VID Processor 1.175 – 1.500 V 128 A Vcc (CPU Core) Voltage(DP) = 1.30 -1.
Platform Power Delivery Guidelines 11.1.1 12 V System designs may require user access to energized areas of the system. In these cases the power supply may be required to meet regulatory 240 VA limits for any power rail. Since the +12 V rail combined power exceeds 240 VA it must be divided into separate channels to meet this requirement. Each separate rail needs to be limited to less than 20 A for each +12V rail. +12V1 is dedicated for providing power to the input of the processor voltage regulator.
Platform Power Delivery Guidelines 11.1.6 1.2 V The 1.2 V power plane powers the MCH core logic requiring 4.5 A. A switching regulator using either the 3.3 V or the 5 V power rail is the regulator’s input to power the 1.2V plane. 11.1.7 5 VSB The 5 VSB power plane comes directly off the 5 VSB power rail and has two functions, to provide power to resume functions via a 3.3 VSB regulator in I/O devices off of the ICH3-S, and to provide 1.8 VSB power through a linear regulator.
Platform Power Delivery Guidelines 11.2 Processor Power Distribution Guidelines 11.2.1 Processor Power Requirements This section describes the requirements for supplying power to an Intel Xeon processor. For detailed electrical specifications, refer to the Intel® Xeon™ Processor Datasheet. The processor allows the use of Auto HALT, Stop-Grant, and Sleep states to reduce power consumption by stopping the clock to specific internal sections of the processor and the BCLK depending on each particular state.
Platform Power Delivery Guidelines Processor VCC_CPU static and transient tolerances and the corresponding Voltage Regulator tolerances assume power distribution paths with resistances no greater than 0.4 mΩ and inductances no greater than 0.1 nH. Meeting these limits can be a challenge because of system layout constraints. Refer to Figure 3-1 for the recommended stack-up showing power and ground layer implementation. Power must be distributed as a plane.
Platform Power Delivery Guidelines The data bus must route over a uniform power plane because of signal quality constraints. Consequently, in a multiprocessor system design, a single power plane should be used for power delivery to all processors. Multiple processors operating at different voltages are not supported, and will not be validated by Intel. The processor VCCSENSE and VSSSENSE pins must be routed to vias.
Platform Power Delivery Guidelines be in the open state whenever VCC_CPU is within its specified range. At power up, the PWRGD signal must remain in the low-impedance state until the output voltage has stabilized within the required tolerance. The minimum voltage at which PWRGD is asserted should be the minimum VCC_CPU specified in the Intel® Xeon™ Processor Datasheet, minus margin to prevent false deassertion, but at least 95% of (VID minus 125 mV).
Platform Power Delivery Guidelines 11.2.4 VR Module 9.1 Recommendations Intel has defined VRM 9.1 for supplying VCC_CPU power to Intel Xeon processor based systems. The VRM 9.1 definition includes Remote-Sense, Current Share, and Output Enable features. VRM 9.1 suppliers must provide these features and must meet voltage and current requirements set forth in the VRM 9.1 DC-DC Converter Design Guidelines. The VRM 9.
Platform Power Delivery Guidelines Figure 11-5. “Row” Pattern with Voltage Regulator Module Voltage Regulator Module B Proc B North Side Input Proc B South Side Input Voltage Regulator Remote Sense Proc A North Side Input P roc A South Side Input Voltage Regulator Module A If available on the VRM, route the differential remote SENSE input signals (VO-sen+ and VO-sen-) from both VRM connectors to the middle of the VCC_CPU plane.
Platform Power Delivery Guidelines 11.2.5 VR Down Recommendations Figure 11-6 is a simplified block diagram of a four-phase, interleaved VRD implementation. Figure 11-6. Simplified VRD Circuit Example 12 V Controller VID PWRGD Driver A clks Driver B OUTEN VCC_CPU Driver C Driver D 11.2.5.1 VRD Placement Figure 11-7 and Figure 11-8 show the two recommended VRD placements.
Platform Power Delivery Guidelines Figure 11-7. “L” Pattern with Voltage Regulator Down Proc A North Side Input Voltage Regulator Remote Sense Proc A South Side Input Proc B North Side Input Voltage Regulator Dow n Output Inductors Proc B South Side Input Figure 11-8.
Platform Power Delivery Guidelines 11.2.5.2 Loadline Selection Circuitry Many OEMs require that a dual-processor VRD supplying an Intel processor’s common voltage plane operate with either one or two processors installed on the board (i.e., the design must meet the static and transient voltage characteristics of both the dual- and single-processor load lines).
Platform Power Delivery Guidelines 11.2.5.3 VRD Circuit Implementation This section contains general VRD circuit and layout implementation recommendations. For specific VRD design details, refer to the Dual Intel® Xeon™ Processor Voltage Regulator Down (VRD) Design Guidelines and VRD vendor documentation. Route the VRD’s voltage sense input signal to the middle of the VCC_CPU plane. The location of this plane connection and route is not critical.
Platform Power Delivery Guidelines 11.2.6 Voltage Sequencing When designing a system with multiple voltages, there is always the issue of ensuring that no damage occurs to the system during voltage sequencing. Voltage sequencing is the timing relationship between two or more voltages such as VCC_CPU and SM_VCC/VID_VCC. SM_VCC/VID_VCC is defined as 3.3 V for the processor. The processor’s BSEL[1:0] outputs use an active driver. A 3.3 V source connected to the processor’s 3.3 V pins supplies the VID output.
Platform Power Delivery Guidelines Figure 11-11. Power-Up Sequencing > TO + 100 ms 3.3 V 95% of 3.3 V PWR_OK / OUTEN VID[4:0] BSEL[1:0] VRx PWRGD > 10 ms Processor PWRGOOD Processor RESET# T0 T0 + 1 mS 1 ms < T < 10 ms Figure 11-12. Power-Down Sequencing 3.3 V 95% 3.
Platform Power Delivery Guidelines 11.2.7 VCCA, VCCIOPLL, and VSSA Filter Specifications VCCA and VCCIOPLL are required by the processor’s internal PLL. These voltages are created by using a low pass filter on VCC_CPU. The processor has internal analog PLL clock generators that require quiet power supplies for minimum jitter. Jitter is detrimental to a system; it degrades external I/O timings, as well as internal core timings (i.e., maximum frequency). The filter topology is shown in Figure 11-13.
Platform Power Delivery Guidelines To satisfy damping requirements, total series resistance in the filter (from VCC_CPU to the top plate of the capacitor) must be at least 0.35 Ω. This includes the DCR of the inductor and any resistance (routing or discrete components) between VCC_CPU and capacitor top plate. Keep the routing short and wide. If the total is less than 0.35 Ω, add a discrete resistor to make up the difference. For example, if the selected filter inductor has a minimum of 0.
Platform Power Delivery Guidelines 11.2.8 Power Planes VCC_CPU static and transient tolerances of the processor, and the corresponding voltage regulator tolerances assume power distribution paths with round trip resistances no greater than 300 µΩ and inductances any greater than 100 pH. Power must be distributed as a plane. This plane can be constructed as an island on a layer used for other signals, on a supply plane with other power islands, or as a dedicated layer of the PCB.
Platform Power Delivery Guidelines In either case, for controlling emissions, all planes and islands should be well decoupled. The exact board layout, and the chassis design will determine the amount of decoupling required for controlling emissions. Proper designs will incorporate additional pads for capacitors to be added in case they are found to be necessary during EMI testing. Signals routed over power islands or islands in the ground plane create a discontinuity in the return path of that signal.
Platform Power Delivery Guidelines Figure 11-16. Decoupling Example for a Microstrip Baseboard Design Cavity Under Processor 3-4 0.1 uF with 0805 body over the address and control signals and as close to the processor package as possible. 4-6 0.1 uF with 0805 body over the data signals and as close to the processor package as possible. Data Pins 11.2.9.2 Address and Control Pins Bulk Decoupling The Intel Xeon processor causes very large switching transients.
Platform Power Delivery Guidelines 11.2.10 AGTL+ Reference Voltage The processor GTLREF[3:0] and MCH HDVREF[3:0], HAVREF[1:0], and HCCVREF are low current inputs (less than 15 µA each) to the differential receivers within each of the components on the AGTL+ bus. Use a voltage divider to generate a GTLREF[3:0] of 0.63*VCC_CPU ± 2%. Figure 11-17.
Platform Power Delivery Guidelines Decouple GTLREF[3:0] at each pin with a 220 pF capacitor to ground. Decoupling GTLREF to ground at the voltage divider with a 1 µF capacitor may further enhance the ability for GTLREF to track VCC. When routing GTLREF to the pins, use a 30-mil to 50-mil trace (the wider the better), and keep it as short as possible (less than 1.5 inches). Also, keep all other signals at least 20 mils away from the GTLREF trace.
Platform Power Delivery Guidelines 11.3 MCH Power Delivery Guidelines The following guidelines are recommended for an optimal MCH power delivery. The main focus of these guidelines is to minimize chipset power noise and signal integrity problems. The guidelines are not intended to replace thorough system validation of products. 11.3.1 DDR_VTT (1.25 V) Decoupling To reduce noise on the DDR termination voltage (1.25 V) around the MCH, two 0.1 µF and two 0.01 µF capacitors per-channel are recommended.
Platform Power Delivery Guidelines Figure 11-19.
Platform Power Delivery Guidelines When designing the VCCA1_2 filter (Figure 11-20), follow these guidelines: • One 54 nH Inductor close to the edge of the package (within 1 inch of the die). • One 100 µF or 150 µF LF capacitor close to the edge of the package. • Minimum of two (four preferred) Low ESL HF capacitors, 0.22 µF or 0.1 µF, on the backside of the motherboard under the die.
Platform Power Delivery Guidelines 11.3.6 MCH Power Sequencing Requirement The MCH has only one power sequencing requirement. The MCH requires that 1.2 V rises with or before 2.5 V to avoid electrical overstress of oxide layers and possible component damage. This means that at any point during system power up, the 2.5 V power plane voltage must not be higher than the 1.2 V power plane voltage until the 1.2 V voltage is within 1.2 V regulation. This is depicted in Figure 11-23.
Platform Power Delivery Guidelines 11.4 Intel® ICH3-S Power Delivery Guidelines 11.4.1 1.8 V/3.3 V Power Sequencing The ICH3-S has two pairs of associated 1.8 V and 3.3 V supplies. These are {VCC1_8, VCC3_3} and { VCCSus1_8, VCCSus3_3}. The difference between the two associated supplies must never be greater than 2.0 V. The 1.8 V supply may come up before the 3.3 V supply without violating this rule (though this generally does not occur because the 1.8 V supply is typically derived from the 3.
Platform Power Delivery Guidelines When analyzing systems that may be “marginally compliant” to the 2 V Rule, attention must be paid to the behavior of the ICH3-S’s RSMRST# and PWROK signals because they control internal isolation logic between the various power planes: • RSMRST# controls isolation between the RTC well and the resume wells. • PWROK controls isolation between the resume wells and main wells.
Platform Power Delivery Guidelines 11.4.2 3.3 V/V5REF Sequencing V5REF is the reference voltage for 5 V tolerance on inputs to the ICH3-S. V5REF must be powered up before VCC3_3, or be no less than 0.7 V less than VCC3_3. Thus, VCC3_3 must never be more than 0.7 V higher than V5REF. Also, V5REF must power down after VCC3_3, or before VCC3_3 within 0.7 V. The rule must be followed in order to ensure the safety of the ICH3S.
Platform Power Delivery Guidelines 11.4.4 Intel® ICH3-S Decoupling Recommendations The ICH3-S is capable of generating large current swings when switching between logic high and logic low. This condition could cause the component voltage rails to drop below specified limits. To avoid this, ensure that the appropriate amount of bulk capacitance is added in parallel to the voltage input pins.
Platform Power Delivery Guidelines 11.5 Intel® P64H2 Power Requirements 11.5.1 Intel® P64H2 Current Requirements Table 11-9. Intel® P64H2 Max Sustained Currents Voltage at PCI/PCI-X Interface Max Sustained Current 1.8 V at 33 MHz PCI (both segments) 1970 mA 1.8 V at 66 MHz PCI/PCI-X (both segments) 2170 mA 1.8 V at 100 MHz PCI-X (both segments) 2550 mA 1.8 V at 133 MHz PCI-X (both segments) 2660 mA 3.3 V at 33 MHz PCI 6 loads (both segments) 930 mA 3.
Platform Power Delivery Guidelines Figure 11-28. 3.3V PCI/PCI-X (VCC3_3) Capacitor Placement on Backside A24 AD24 0.1uF A1 AD1 NOTE: The outlined area in the figure is the 3.3 V plane. Place at least five 0.1 µF capacitors in this area. 11.5.3 PCIRST# Implementation PCI-X requires a 100 ms delay from valid power (PWRGD) to reset deassertion (PCIRST#). The system design must ensure this requirement is met. The P64H2 reset must be deasserted within 60 ns of the MCH reset deassertion.
High-Speed Design Concerns High-Speed Design Concerns 12.1 12 Return Path The return path is the route current takes to return to its source. It may take a path through ground planes, power planes, other signals, or integrated circuits. The return path is based on electromagnetic field effects. It is useful to think of the return path as the path of least impedance nearest the signal conductor.
High-Speed Design Concerns 12.2.1 Bulk Decoupling Larger bulk storage components, such as electrolytic capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. Power bypassing is required due to the relatively slow speed at which a DC-to-DC converter can react.
High-Speed Design Concerns 12.3 Serpentine Routing A serpentine net is a transmission line that is routed in such a manner that sections of the net double back and couple to other segments of the same net. Figure 12-2. Serpentine Routing Serpentining a transmission line is sometimes necessary to properly match lengths between nets. It is important to properly control the serpentine to avoid signal integrity and timing problems.
High-Speed Design Concerns 12.4 EMI Design Considerations As microprocessor amperage and speeds increase, the ability to contain the corresponding electromagnetic radiation becomes more difficult. Frequencies generated by these processors will be in the low gigahertz (GHz) range, which will impact both the system design and the electromagnetic interference (EMI) test methodology.
High-Speed Design Concerns 12.4.2 EMI Regulations and Certifications Original Equipment Manufacturers (OEMs) ensure EMC compliance by meeting EMI regulatory requirements. System designers must ensure that their computer systems do not exceed the emission limit standards set by applicable regulatory agencies. Regulatory requirements referenced in this document include: • United States Federal Communication Commission (FCC) Part 15 Class B.
High-Speed Design Concerns Figure 12-5. Impact of Spread Spectrum Clocking on Radiated Emissions ∆ non-SSC SCC (1-δ)fnom fnom 12.4.4 Differential Clocking Differential clocking requires that the clock generator supply both clock and clock-bar traces. Clock-bar has equal and opposite current as the primary clock, and is also 180 degrees out of phase. To maximize the benefit of differential clocking, both clock lines must be routed parallel to each other for their entire length.
High-Speed Design Concerns Differential clocking can also reduce the amount of noise coupled to other traces, which improves signal quality and reduces EMI. I/O signals are particularly important because they often leave the system chassis (serial and parallel ports, keyboards, mouse, etc.), and radiate noise that has been induced onto them. A single-ended clock's return path is usually a reference plane, which is shared by other signals/traces.
High-Speed Design Concerns 12.5 Length Tuning Note: This section does not apply to the Processor System Bus. High speed source synchronous interfaces have very small setup and hold window.s As a result, the signals as a group are very sensitive to skew. A common way to reduce skew is to tune all of the lengths such that the setup and hold windows have the same positional relationship.
High-Speed Design Concerns 12.5.1 Signal to Strobe Flight Time Relationships High speed interfaces are commonly latched off of a strobe or a clock. Length tuning ensures that the required setup and hold times of the data signal to the strobe signal or clock signal are not violated due to motherboard routing effects. As a result, each data signal is length tuned with respect to the strobe signal or clock signal.
High-Speed Design Concerns If the strobes are the furthest apart (i.e., as far apart as allowed for signals of the same group), then their difference is the total allowed tolerance. This means that all signals must fall between them, or have a solution space which is “tolerance” wide. Longer_StrobeFlight Time = Shorter_StrobeFlight Time + Tolerance Shorter_StrobeFlight Time = Longer_StrobeFlight Time – Tolerance Figure 12-10.
High-Speed Design Concerns 12.5.2 Flight Time Segment Analysis Length matching often requires package compensation. Every time a signal changes innerconnect or layer, there is an affect on flight time. The most effective way to calculate flight time is to break up each signal into segments of “constant” flight time, analyze those segments, and then add the segments together.
High-Speed Design Concerns 12.5.3 Length Tuning Equation Derivation When routing a motherboard, only one piece of the equation is a variable: PCB trace length. For example, if signals are tuned with respect to the strobe, the final equation used by a motherboard designer is derived as follows.
High-Speed Design Concerns 12.5.4 DDR Example The DDR Source Synchronous bus requires groups of 8 signals and 2 strobes to be length tuned within 25 mils. Given that the PCB trace length for DDRA_DQS2 is 3.85 inches, what is the solution space for DDRA_DQS11 and DDRA_DQ20? To determine the PCB solution space for the signal DDRA_DQ20, you need the PCB length of the strobe DDRA_DQS11. So, we will find the length for DDRA_DQS11 first.
High-Speed Design Concerns 12.5.5 Bus Length Tuning Methodology Many buses, such as memory and processor system bus, require length tuning a group of signals. A common way to do this is by routing the bus first to determine what the approximate length range is. Then, you can pick an arbitrary signal. Sometimes this signal may be the most difficult to route or adjust to tune.
High-Speed Design Concerns To compensate for package-induced skew, all source synchronous motherboard trace lengths are adjusted by the exact amount of Package Length Compensation (PLC). Equation 12-3 defines PLC for a particular signal. Signal X is any signal in the group that does not have the longest package length. This includes the strobe signals. Equation 12-3.
High-Speed Design Concerns buffers, balancing setup and hold time requirements of the receiver, and other electrical factors verified in simulation and system bus validation. For the system bus recommendations included in this document, Equation 12-4 is used: Equation 12-4. Signal Integrity Adjustment Length Signal XSI Adj= 0.78 * SignalXPLC The 0.78 compensation factor was determined to be the optimum adjustment for the system bus recommendations given in this platform design guide. 12.6.
High-Speed Design Concerns However, it would unbalance the Processor 0/MCH path by a total length of 2*SignalXPLC since this path does not contain propagation along the Processor 1 package. The Processor 0/MCH path has the longest propagation in the system and presents the highest risk of mismatch between the signals and associated strobe due to the Processor 1 package stubs. The best pad-to-pad compensation for the Processor 0/MCH direction, excludes 2 SignalXPLC lengths at Processor 1.
High-Speed Design Concerns SignalXProcessor 0 to Processor 1 PCB Length and SignalXProcessor 1 to MCH PCB Length should be chosen to allow all signals in the same signal group to meet the specific system bus routing guidelines documented in Chapter 5 of this document. The PLC and SI Adjustment Length motherboard segments adjust the motherboard trace lengths to account for the processor and MCH package effects.
High-Speed Design Concerns Part 1 Solution: By definition, the DSTBN0# signal 5-inch route already includes the PLC and SI motherboard trace components. The PLC and SI values are determined for DSTBN0# and DSTBP0# using Equation 12-3 and Equation 12-4. DSTBN0#Processor PLC = Maximum in GroupProcessor Package Length – DSTBN0#Processor Package Length = 0.578 inch - 0.208 inch= 0.370 inch DSTBN0#SI Adj = 0.78 * DSTBN0#Processor PLC = 0.78 * 0.370 inch = 0.
High-Speed Design Concerns Part 2 Solution: By definition, the DSTBN0# signal 4-inch route already includes the PLC and SI motherboard trace components. The SI value can be used from Part 1. The MCH PLC values are determined for DSTBN0# and DSTBP0# using Equation 12-3. DSTBN0#MCH PLC = Maximum in GroupMCH Package Length - DSTBN0#MCH Package Length = 1.060 inch - 0.842 inch = 0.218 inch DSTBP0#MCH PLC = Maximum in GroupMCH Package Length - DSTBP0#MCH Package Length = 1.060 inches - 0.738 inch = 0.
Schematic Checklist 13 Schematic Checklist 13.1 Processor Schematic Checklist Table 13-1. Processor Schematic Checklist (Sheet 1 of 4) Checklist Items Recommendations Comments Intel® A20M# IGNNE# INIT# LINT0/INTR LINT1/NMI SMI# SLP# STPCLK# ICH3• Connect to both processors and S. Include 200 Ω ± 5% pull-up to VCC_CPU. • Asynchronous GTL+ Input Signal. • Refer to Section 5.3.6.
Schematic Checklist Table 13-1. Processor Schematic Checklist (Sheet 2 of 4) Checklist Items Recommendations BPM[5:0]# • For all ITP interface signal schematic, layout and routing recommendations, refer to the ITP700 Debug Port Design Guide. BR[3:0]# • Connect BR[0]# to the MCH’s BREQ0# pin, Processor 0’s BR0# pin, and Processor 1’s BR1# pin. Terminate using a 50 Ω ± 5% pullup resistor at Processor 0. • Connect BR[1]# signal to Processor 0’s BR1# pin and Processor 1’s BR0# pin.
Schematic Checklist Table 13-1. Processor Schematic Checklist (Sheet 3 of 4) Checklist Items Recommendations Comments SM_ALERT# SM_CLK SM_DAT • Connect to both processors and SMBus. • A pull-up resistor to 3.3 V. Resistor value is based on the number of devices on the SMBus. • These signals have 10 kΩ pulldowns on the Intel® Xeon™ processor with 512-KB L2 cache and are not supported on the Intel® Xeon™ processor with 533 MHz system bus • Refer to Section 5.5 and Section 9.5.4.
Schematic Checklist Table 13-1. Processor Schematic Checklist (Sheet 4 of 4) Checklist Items Recommendations Comments VCCSENSE • Leave No Connect. • Isolated low impedance connection to processor core VCC_CPU. • Refer to Section 11.2.2. VID[4:0] • Individually pull-up to 3.3 V using 1 kΩ resistor, provided a VRx 9.1 compliant regulator is used and recommended comparator is used. • Should be routed individually from each processor to the voltage regulator supplying its VCC_CPU supply.
Schematic Checklist 13.2 MCH Schematic Checklist L Table 13-2. MCH Schematic Checklist (Sheet 1 of 3) Checklist Items Recommendations Comments Host Interface ADS# AP[1:0] BINIT# BNR# BPRI# BREQ0#1 CPURST#2 DBI[3:0]# DBSY# DEFER# DP[3:0]# DRDY# HA[35:3]#3 HD[63:0]#4 HADSTB[1:0]#5 HDSTBN[3:0]#6 HDSTBP[3:0]#7 HIT# HITM# HLOCK# HREQ[4:0]#8 HTRDY#9 RS[2:0]# RSP# XERR#10 • See processor section of this checklist.
Schematic Checklist Table 13-2. MCH Schematic Checklist (Sheet 2 of 3) Checklist Items DDRCVOL_x DDRCVOH_x DDRCVO_x Recommendations Comments • Connect as shown in Figure 6-17. • Refer to Section 6.7.4. • DDRCVOL_x and DDRCVOH_x are on the E7500 chipset MCH and DDRCVO_x is on the E7501 chipset MCH. HI[11:0] HI_STBF11 HI_STBS11 • Connect to ICH3-S. • Must not have pull-up, pull-down, or series resistors. • Refer to Section 7.3.1. HIRCOMP_A • Hub Interface A 24.
Schematic Checklist Table 13-2. MCH Schematic Checklist (Sheet 3 of 3) Checklist Items Recommendations Comments Voltage References – Power Planes HDVREF[3:0] HAVREF[1:0] HCCVREF • Use one dedicated voltage divider for all these signals. • Decouple the voltage divider with a 1 µF capacitor and use a 220 pF at the MCH pins. • To provide constant and clean power delivery to the data, address and common clock signals of the host AGTL+ interface. • Refer to Section 11.2.10.
Schematic Checklist Intel® ICH3-S Schematic Checklist 13.3 Note: There are no inputs to the ICH3-S that can be left floating. Table 13-3. Intel® ICH3-S Schematic Checklist (Sheet 1 of 6) Checklist Items Recommendations Comments Processor Signals A20M# CPUPWRGD CPUSLP# (SLP#) FERR# IGNNE# INIT# LINT11 LINT01 SMI# STPCLK# • Refer to the signal recommendations under the Processor Schematic Checklist.
Schematic Checklist Table 13-3. Intel® ICH3-S Schematic Checklist (Sheet 2 of 6) Checklist Items Recommendations Comments Hub Interface HI[11:0] HI_STBS HI_STBF • No pull-up resistor required. HICOMP • 78.7 Ω ± 1% pull-up to 1.8 V. HIREF HITERM • • • • • HREF = 0.350 V + 5%. HITERM = 0.700 V ± 5%. R4 = 261 Ω ± 1%, R5 = 825 Ω ± 1%. Decouple the ICH3-S pin with a 0.01 µF. Decouple the network nodes with a 0.1 µF • Refer to Section 7.3.1. • Refer to Section 7.3.3. • Refer to Section 7.3.2.
Schematic Checklist Table 13-3. Intel® ICH3-S Schematic Checklist (Sheet 3 of 6) Checklist Items Host Side / Device Side Cable Detection Recommendations Comments • Connect IDE pin PDIAG#/CBLID# to an ICH3-S GPI pin. Connect a 10 kΩ resistor to ground on the signal line. • The 10 kΩ resistor to ground prevents GPI from floating if no devices are present on either IDE interface. Allows use of 3.3 V and 5 V tolerant GPIOs. • Refer to Section 9.1.2.1.
Schematic Checklist Table 13-3. Intel® ICH3-S Schematic Checklist (Sheet 4 of 6) Checklist Items Recommendations Comments EE_DOUT • Connect to EE_DIN of EEPROM. (Input from EEPROM perspective and output from ICH3-S perspective.) • If unused, leave No Connect. • ICH3-S contains an integrated pull-up resistor for this signal. EE_DIN • Connect to EE_DOUT of EEPROM. (Ouput from EEPROM perspective and input from ICH3-S perspective.) • If unused, leave No Connect.
Schematic Checklist Table 13-3. Intel® ICH3-S Schematic Checklist (Sheet 5 of 6) Checklist Items Recommendations Comments V5REF_Sus • If USB is implemented in the platform, V5REF_Sus must be connected to VSUS5. • Use one 0.1 µF decoupling capacitor. • Refer to Section 11.4.4. V5REF • Requires one 0.1 µF decoupling capacitor. • Refer to Section 11.4.4. Power Sequencing Requirements V5REF_Sus and VCCSus3_3 • V5REF_Sus must power up before or simultaneous to VCCSus3_3.
Schematic Checklist Table 13-3. Intel® ICH3-S Schematic Checklist (Sheet 6 of 6) Checklist Items Recommendations Comments RTC VBIAS • Use one 0.047 µF capacitor. RTCRST • For noise immunity on VBIAS signal. • Refer to Figure 9-11. • Refer to Section 9.6.8. • Connect a 32.768 kHz Crystal Oscillator across these pins with a 10 MΩ resistor. Decouple each signal dependant upon the crystal oscillator’s characteristics. • RTCX1 may optionally be driven by an external oscillator instead of a crystal.
Schematic Checklist 13.4 Intel® 82870P2 P64H2 Schematic Checklist Table 13-4. Intel® P64H2 Schematic Checklist (Sheet 1 of 4) Checklist Items Recommendations Comments Hub Interface HI_[21,20,18:0] PUSTRBF PUSTRBS PSTRBF PSTRBS • Connect to the MCH. HI_[19] • HI[19] must be left as no connect. • Refer to Section 7.2.1 HI_RCOMP • 61.9 Ω ± 1% pull-up to 1.8 V. • Refer to Section 7.2.3 HI_VREF HI_VSWING • P64H2 Hub reference swing voltage = 0.800 V ± 5%. • P64H2 Hub reference voltage = 0.
Schematic Checklist Table 13-4. Intel® P64H2 Schematic Checklist (Sheet 2 of 4) Checklist Items Recommendations Comments Interrupt Interface 8.2 kΩ ± 5% pull-up to 3.3 V. PAIRQ[15:0] PBIRQ[15:0] • APICCLK APICD[1:0] • 8.2 kΩ ± 5% pull-up to 3.3 V. Hot-Plug Interface Enabled PxPCIXCAP • 8.2 kΩ ± 5% pulled up to 3.3 V. • These PCI signals are connected to separate pins on the Intel® P64H2. See Section 8.2.6.4, Section 8.2.7.3, and Section 8.2.8.
Schematic Checklist Table 13-4. Intel® P64H2 Schematic Checklist (Sheet 3 of 4) Checklist Items Recommendations Comments Hot-Plug – Dual-Slot Parallel Mode Specific HPx_SLOT[2:0]1 SLOT[0]: 8.2 kΩ pull-down to ground. SLOT[1]: 8.2 kΩ pull-up to 3.3 V. SLOT[2]: 8.2 kΩ pull-down to ground. • This is a strapping pin for enabling single slot parallel mode which is latched during reset. SLOT[1] also functions as the HxPCIXCAP2A input when not in reset.
Schematic Checklist Table 13-4. Intel® P64H2 Schematic Checklist (Sheet 4 of 4) Checklist Items Recommendations Comments Power Decoupling Requirements VCC (1.8 V) • Eight 0.1 µF capacitors near the P64H2. • Two 4.0 µF capacitors near regulator. • Refer to Section 11.5.2. VCC1_8 • Two 1.0 µF capacitors near the P64H2. • One 100.0 µF capacitors near regulator. • Refer to Section 11.5.2. 3.3 V • • • • • Refer to Section 11.5.2. VCC5REF • Connect to 5 V Power Supply. Twenty 0.
Schematic Checklist 13.5 CK408 Schematic Checklist For additional information, refer to the CK408 Clock Synthesizer/Driver Specification and your component’s datasheet. Table 13-5. CK408 Schematic Checklist Checklist Items 242 Recommendations Reason/Impact V3_CLK, V3_CLKA • Isolate from the 3.3 V power plane and use extra decoupling. • Refer to Section 4.7. 66BUFF[2:0] • Connect to an Intel® P64H2 using a series 43 Ω ± 5% resistor. • Refer to Section 4.2. 66IN • No Connect.
Schematic Checklist 13.6 SSI Schematic Checklist For additional information, refer to the Intel® Xeon™ Processor and Intel® E7501 Chipset Server System Design Guide and the SSI EEB Specification. Table 13-6. SSI Schematic Checklist Checklist Items Recommendations Reason/Impact Main Power Connector • Use a 24 pin Molex 44472 family connector or equivalent • Refer to Table 3-3 for pinout. • SSI EEB Specification, Section 5.3.1.
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Layout Checklist 14 Layout Checklist All trace width and spacing recommendations are derived from a target impedance and crosstalk sensitivity. This is based upon the stackup defined in Section 3.1. Any deviation from this stackup must be simulated. 14.1 Processor Checklist Table 14-1. Processor Layout Checklist (Sheet 1 of 2) Checklist Items Recommendations Comments A20M# IGNNE# INIT# LINT0/INTR LINT1/NMI SMI# SLP# STPCLK# • Trace impedance = 50 Ω ± 10%. • Route traces using 5/10-mil spacing.
Layout Checklist Table 14-1. Processor Layout Checklist (Sheet 2 of 2) Checklist Items Recommendations BPM[5:0]# Comments • For all ITP interface signal schematic, layout and routing recommendations, refer to the ITP700 Debug Port Design Guide. FERR#/PBE# IERR# PROCHOT# THERMTRIP# • • • • Connect to both processors and ICH3-S. Trace impedance = 50 Ω ± 10%. Route traces using 5/15-mil spacing. Try to keep signals on the same layer for the whole bus, but not at expense of AGTL+ Source Synchronous I/O.
Layout Checklist 14.2 Processor Power Delivery Layout Checklist All recommendations in this checklist apply to the power distribution design of the processor’s “VCC_CPU” and ground supply. This checklist assumes the voltage regulator solution adheres to the guidelines documented in either the VRM 9.1 DC-DC Converter Design Guidelines or Dual Intel® Xeon™ Processor Voltage Regulator Down (VRD) Design Guidelines depending on which solution is implemented. Table 14-2.
Layout Checklist Table 14-2. Processor Power Delivery Layout Checklist (Sheet 2 of 4) Checklist Items Recommendations Comments VRM VO-sen+ / VO-sen- remote sense • If available on the VRM, route the VR’s differential remote sense input signals to the middle of the VCC_CPU plane. • Route the positive feedback line to a point on the VCC_CPU power plane in the middle of and equidistant from both processors.
Layout Checklist Table 14-2. Processor Power Delivery Layout Checklist (Sheet 3 of 4) Checklist Items Recommendations Comments Voltage Regulator Down Circuit Implementation (for VRD designs only!) Loadline Selection Circuit • For designs based on a VRD solution, the system must include loadline selection circuitry that adjusts the voltage regulator’s loadline output (offset and slope) based on whether one or two processors are installed. • Section 11.2.5.
Layout Checklist Table 14-2. Processor Power Delivery Layout Checklist (Sheet 4 of 4) Checklist Items 250 Recommendations Comments 1.0 µF and 22.0 µF decoupling capacitor quantity and placement • Use at least twenty, 22.0 µF ceramic capacitors per processor socket. • Use at least eight ,1.0 µF ceramic capacitors per processor socket.
Layout Checklist 14.3 MCH Layout Checklist Table 14-3. MCH Layout Checklist (Sheet 1 of 3) Checklist Items Recommendations Comments Host Interface ADS# AP[1:0] BINIT# BNR# BPRI# BREQ0#1 CPURST#2 DBSY# DEFER# HA[35:3]#3 HD[63:0]#4 HADSTB[1:0]#5 HDSTBN[3:0]#6 HDSTBP[3:0]#7 HIT# HITM# HLOCK# HREQ[4:0]#8 HTRDY#9 DP[3:0]# DRDY# RS[2:0]# RSP# XERR#10 DBI[3:0]# • See processor section of this checklist.
Layout Checklist Table 14-3. MCH Layout Checklist (Sheet 2 of 3) Checklist Items Recommendations Comments RAS_x# CAS_x# WE_x# MA_x[12:0] BA_x[1:0] • Place termination resistor within 800 mills from last DIMM connector. No more then 2 vias/layer transitions, not including breakout and passive devices. • Refer to Section 6.4. CS_x[7:0]# • Place termination resistor within 1.5" from the connector. • Refer to Section 6.5.
Layout Checklist Table 14-3. MCH Layout Checklist (Sheet 3 of 3) Checklist Items HIRCOMP_x HIVREF_[D:A] HISWNG_[D:A] Recommendations Comments • RCOMP, VSWING, VREF resistor networks are less than 1” away from the MCH. • VSWING, VREF trace width is greater than 15 mils. • HIRCOMP_x must have a 50 Ω impedance. • Refer to Section 7.2.2, Section 7.2.3, Section 7.3.2, and Section 7.3.3. Clocks, Reset, Miscellaneous Signals HCLKINP HLCKINN • HCLKs should be length matched to all processors BCLKs.
Layout Checklist 14.4 Intel® ICH3-S Layout Checklist Table 14-4. Intel® ICH3-S Layout Checklist (Sheet 1 of 4) Checklist Items Recommendations Comments Processor Signals A20M# CPUSLP# FERR# IGNNE# INIT# LINT[1:0] SMI# STPCLK# • See processor section of this checklist. FWH Interface Decoupling • 0.1 µF capacitors should be placed between the VCC supply balls and the VSS ground balls, and no less than 390 mils from the VCC supply balls. • 4.
Layout Checklist Table 14-4. Intel® ICH3-S Layout Checklist (Sheet 2 of 4) Checklist Items Recommendations Comments General Guidelines, cont. • Keep the total length of each differential pair under 4". • Issues found with traces longer than 4": – IEEE phy conformance failures – excessive EMI and or degraded receive BER. • Do not route the transmit differential traces closer than 100 mils to the receive differential traces. • To minimize crosstalk.
Layout Checklist Table 14-4. Intel® ICH3-S Layout Checklist (Sheet 3 of 4) Checklist Items Recommendations Comments V_CPU_IO[2:0] • Use one 0.1 µF decoupling capacitor. Locate within 100 mils of the ICH3-S processor interface balls. • Used to pull-up all processor I/F signals. VCC3_3 • Requires six 0.1 µF decoupling capacitors. Distribute around the ICH3-S package sides within 100 mils from the package balls: – Top near AUX/PCI – Left across the PCI and LPC – Bottom near IDE.
Layout Checklist Table 14-4. Intel® ICH3-S Layout Checklist (Sheet 4 of 4) Checklist Items Recommendations Comments USB General Guidelines • Route all traces over continuous planes (ground) with no interruptions. Avoid crossing over anti-etch if possible. Crossing over anti-etch (plane splits) increases inductance and radiation levels by forcing a greater loop area. Likewise, avoid changing layers with high-speed traces.
Schematics Schematics 15 This appendix contains a set of schematics for the Intel® Xeon™ processor / Intel® E7500/E7501 chipset compatible platform Customer Reference Board (CRB).
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8 7 6 5 4 3 2 1 Intel® Xeon™ Processor with 533 MHz System Bus/ Intel® Xeon™ Processor with 512-KB L2 Cache and Intel® E7500/E7501 Chipset Customer Reference Board Schematics D D Rev 2.0 11/18/02 C C THESE SCHEMATICS ARE SUBJECT TO CHANGE. LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS.
8 7 6 5 4 3 2 1 Table of Contents D D Processors............................................................................................4-8 PCI33 Slot.........................................................................................65 ITP.......................................................................................................9 Video................................................................................................66-67 MCH..................................
8 7 6 5 4 3 2 1 Simplified System Block Diagram Pages 35-41 D Gbit Ethernet Controller D Processor 0 133MHz Processor 1 Pages 4-9 PCI-X Intel® 82546EB Pages 25-28 Bus A P64H2 #1 Pages 42-43 100MHz PCI-X Slots 2:3 HI Channel B Pages 10-14 Bus B DDR DIMM HI Channel C Pages 44-51 MCH Pages 15-24 C C HI Channel D I/O Processor DDR DIMM Intel® 80321 HI Channel A Pages 52-59 Pages 66-67 Dual Channel SCSI 100MHz PCI Video PCI-X 69000 HiQVideo™ Accelerator Pages 29-32 33MHz PC
8 7 6 5 4 3 2 1 +VCC_CPU +VCC_CPU Processor 1 Connector +VCC_CPU CAD NOTE: C 1% R2 R1 49.9 AB6 D63 A35 C8 FSB_A35_N FSB_HD62_N Y9 D62 A34 C9 FSB_A34_N FSB_HD61_N AA8 D61 A33 A7 FSB_A33_N FSB_HD60_N AC5 D60 A32 A6 FSB_A32_N ITP_TDI_P1 6,10 FSB_BPRI_N D23 BPRI IERR E5 CPU1_IERR_N CPU_BREQ2_3_N D10 BR3 ADS D19 SOCKET_604 6,10 R6 ITP_TRST_N 4,6,9 R1069 40.2 1% 6 680 R1070 40.
8 7 6 5 4 3 2 1 +V3_3 Processor 1 Connector +V3_3 R33 1K 4,6 +V3_3 CPU_SMBUS_WP R31 10K NOPOP D +VCC_CPU VCC Pins M30 M28 M26 M24 M8 M6 M4 M2 L31 L29 L27 L25 L23 L9 L7 L5 L3 L1 K30 K28 K26 K24 K8 K6 K4 K2 J31 J29 J27 J25 J23 J9 J7 J5 J3 J1 H30 H28 H26 H24 H8 H6 H4 H2 G31 G29 G27 G25 G9 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VS
8 7 6 5 4 3 2 1 +VCC_CPU Processor 0 Connector FSB_HD62_N Y9 D62 A34 C9 FSB_A34_N FSB_HD61_N AA8 D61 A33 A7 FSB_A33_N FSB_HD60_N AC5 D60 A32 A6 FSB_A32_N FSB_HD59_N AC6 D59 A31 B7 FSB_A31_N FSB_HD58_N AE7 D58 A30 C11 FSB_A30_N FSB_HD57_N AD7 D57 A29 D12 FSB_A29_N FSB_HD56_N AC8 D56 A28 E13 FSB_A28_N FSB_HD55_N AB10 D55 A27 B8 FSB_A27_N FSB_HD54_N AA10 D54 A26 A9 FSB_HD53_N AA11 D53 A25 FSB_HD52_N AB13 D52 FSB_HD51_N AB12 FSB_HD50_N AC14
7 6 5 4 3 2 Processor 0 Connector VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 B30 B28 B23 B17 B15 B9 B2 A31 A29 A27 A21 A11 A5 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 Part 4 of 5 VSS Pins VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS
8 7 6 5 4 3 PROCESSOR 0 and 1 DECOUPLING +VCC_CPU C41 C42 C43 C44 C45 C46 C47 C48 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 2 1 +VCC_CPU +VCC_CPU C1 C3 C5 C7 C9 C11 C13 C15 C17 C19 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF D D C289 C290 C291 C292 C293 C294 C295 C296 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C305 C306 C307 C308 C309 C310 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.
8 7 6 5 4 3 2 1 ITP Place these termination resistors at the ends of the traces.
9 FSB_RS[2:0]_N FSB_DSTBN[3:0]_N FSB_DSTBP[3:0]_N 80 80 R140 FSB_ADSTB[1:0]_N FSB_A[35:3]_N FSB_DBI[3:0]_N FSB_DP[3:0]_N 4,6 36,79,81 4,6 4,6 4,6 FSB_H_CLKINN FSB_H_CLKINP FSB_HYCOMP FSB_HXRCOMP FSB_HYSWING FSB_HXSWING FSB_DSTBP0_N FSB_DSTBP1_N FSB_DSTBP2_N FSB_DSTBP3_N FSB_DBSY_N FSB_DEFER_N FSB_DRDY_N SYS_PWROK_1 FSB_BINIT_N FSB_DP3_N FSB_DP2_N FSB_DP1_N FSB_DP0_N FSB_DBI3_N FSB_DBI2_N FSB_DBI1_N FSB_DBI0_N FSB_A35_N FSB_A34_N FSB_A33_N FSB_A32_N FSB_A31_N FSB_A30_N FSB_A29
R159 27 100 R163 C598 0.01UF 24.
15 15 15 15 15 DDRA_DQ0 AF22 DDRA_DQ2 AH22 AE21 AN28 DDRA_DQ3 AM27 DDRA_DQ1 DDRA_DQS0 AF21 AN29 DDRA_DQS9 DDRA_DQ4 AM28 15 15 DDRA_DQ5 AL26 AL25 DDRA_DQ6 15 15 DDRA_DQ7 AN25 AM24 DDRA_DQ8 DDRA_DQ9 DDRA_DQS10 DDRA_DQS1 AK24 AM25 AK23 AL23 AG21 DDRA_DQ12 AL22 DDRA_DQ10 DDRA_DQ13 AJ22 AE20 15 DDRA_DQ14 AK19 DDRA_DQ11 15 DDRA_DQ15 AL19 DDRA_DQ24 DDRA_DQ23 DDRA_DQ22 DDRA_DQ21 DDRA_DQ20 DDRA_DQS11 DDRA_DQS2 DDRA_DQ19 DDRA_DQ18 AH19 AF19 AJ18 AL17 AM19 AN20 AK18 AG1
DDRB_DQ0 K30 F33 High Nibble Low Nibble High Nibble Low Nibble High Nibble Low Nibble High Nibble Low Nibble High Nibble Low Nibble High Nibble Low Nibble Data Group 6 Data Group 5 Data Group 5 Data Group 4 Data Group 4 Data Group 3 Data Group 3 Data Group 2 Data Group 2 Data Group 1 Data Group 1 Data Group 0 Data Group 0 DQ0_B DQ1_B WE_N_B CAS_N_B RAS_N_B MA0_B MA1_B MA2_B MA3_B MA4_B E31 E33 F31 G29 F32 G30 H30 K29 M26 V32 H28 D32 DDRB_MA10_R DDRB_MA9_R DDRB_MA8_R
VCC1_2_5 VCC1_2_4 VCC1_2_3 VCC1_2_2 VCC1_2_1 VCC2_5_8 VCC2_5_7 VCC2_5_6 VCC2_5_4 VCC2_5_5 AC17 VCC2_5_3 VCC2_5_2 VCC2_5_1 2 VCC1_2_6 AA23 VCC1_2_7 AF33 AE30 AE10 AD33 AD29 AD25 AD20 AD18 AD16 AD14 AD12 AC19 AC15 AC13 AA27 VCC1_2_8 VCC2_5_9 VCC2_5_13 VCC2_5_12 VCC2_5_11 VCC2_5_10 VCC1_2_9 VCC1_2_10 VCC1_2_11 VCC1_2_12 VCC1_2_13 VCC2_5_14 VCC2_5_15 VCC2_5_16 L26 L23 K24 H29 G27 E29 D33 B32 AN30 AM32 AJ29 AJ26 AG28 AF23 AD24 AD22 AC23 AC21 AB24 Y33 Y29
12 12 12 12 12 12 12 12 7 DDRA_DQ4_R DDRA_DQ0_R 8 6 1 RP35 2 DDRA_DQ5_R 3 DDRA_DQ2_R DDRA_DQ0 DDRA_DQ7_R DDRA_DQ4 5 DDRA_DQ3_R 10 8 4 7 DDRA_DQ5 1 DDRA_DQ2 DDRA_DQS4 DDRA_DQ34 DDRA_DQ38 DDRA_DQ33 DDRA_DQ37 DDRA_DQ36 DDRA_DQ32 DDRA_CB7 DDRA_CB3 DDRA_CB6 DDRA_CB2 DDRA_DQ25 DDRA_DQ29 DDRA_DQ28 DDRA_DQ24 DDRA_DQ26 DDRA_DQ30 DDRA_DQS12 DDRA_DQS3 DDRA_DQS11 DDRA_DQS2 DDRA_DQ21 DDRA_DQ17 DDRA_DQ19 DDRA_DQ23 DDRA_DQ22 DDRA_DQ18 DDRA_DQ16 DDRA_DQ20 DDRA_DQ11 DDRA_DQ
15,17,18,24 15,17,18,24 15,17,18,19 15,17,18,24 15,17,18,19 15,17,18,19 15,17,18,24 15,17,18,19 15,17,18,19 15,17,18,24 DDRA_DQS17_R DDRA_DQS8_R DDRA_CB3_R DDRA_CB2_R DDRA_CB1_R DDRA_CB0_R DDRA_DQ63_R DDRA_DQ62_R DDRA_DQ61_R DDRA_DQ60_R DDRA_DQS16_R DDRA_DQS7_R DDRA_DQ59_R DDRA_DQ58_R DDRA_DQ57_R DDRA_DQ56_R DDRA_DQ55_R DDRA_DQ54_R DDRA_DQ53_R DDRA_DQ52_R DDRA_DQS15_R DDRA_DQS6_R DDRA_DQ51_R DDRA_DQ50_R DDRA_DQ49_R DDRA_DQ48_R DDRA_DQ47_R DDRA_DQ46_R DDRA_DQ45_R DDRA_DQ44_R DD
15,16,18,24 15,16,18,24 15,16,18,19 15,16,18,24 15,16,18,19 15,16,18,19 15,16,18,24 15,16,18,19 15,16,18,19 15,16,18,24 DDRA_CB5_R DDRA_CB4_R DDRA_DQS17_R DDRA_DQS8_R DDRA_CB3_R DDRA_CB2_R DDRA_CB1_R DDRA_CB0_R DDRA_DQ63_R DDRA_DQ62_R DDRA_DQ61_R DDRA_DQ60_R DDRA_DQS16_R DDRA_DQS7_R DDRA_DQ59_R DDRA_DQ58_R DDRA_DQ57_R DDRA_DQ56_R DDRA_DQ55_R DDRA_DQ54_R DDRA_DQ53_R DDRA_DQ52_R DDRA_DQS15_R DDRA_DQS6_R DDRA_DQ51_R DDRA_DQ50_R DDRA_DQ49_R DDRA_DQ48_R DDRA_DQ47_R DDRA_DQ46_R DDRA
15,16,17,24 15,16,17,24 15,16,17,19 15,16,17,24 15,16,17,19 15,16,17,19 15,16,17,24 15,16,17,19 15,16,17,19 15,16,17,24 DDRA_CB6_R DDRA_CB5_R DDRA_CB4_R DDRA_DQS17_R DDRA_DQS8_R DDRA_CB3_R DDRA_CB2_R DDRA_CB1_R DDRA_CB0_R DDRA_DQ63_R DDRA_DQ62_R DDRA_DQ61_R DDRA_DQ60_R DDRA_DQS16_R DDRA_DQS7_R DDRA_DQ59_R DDRA_DQ58_R DDRA_DQ57_R DDRA_DQ56_R DDRA_DQ55_R DDRA_DQ54_R DDRA_DQ53_R DDRA_DQ52_R DDRA_DQS15_R DDRA_DQS6_R DDRA_DQ51_R DDRA_DQ50_R DDRA_DQ49_R DDRA_DQ48_R DDRA_DQ47_R DDRA_
12,16 13,21 13,21 12,16 15,16,17,18 15,16,17,18 15,16,17,18 15,16,17,18 15,16,17,18 20,21,22,23 15,16,17,18 15,16,17,18 15,16,17,18 15,16,17,18 15,16,17,18 15,16,17,18 12,16,17,18 12,16,17,18 12,16,17,18 15,16,17,18 15,16,17,18 13,21,22,23 12,16,17,18 12,16,17,18 DRAWN BY: 11/18/02 1 15,16,17,18 15,16,17,18 15,16,17,18 15,16,17,18 12,16,17,18 20,21,22,23 15,16,17,18 15,16,17,18 12,18 15,16,17,18 15,16,17,18 15,16,17,18 15,16,17,18 15,16,17,18 15,16,17,18 15,16,17,18
13 DDRB_DQ4 DDRB_DQ0 2 1 4 13 DDRB_DQ5 3 13 3 1 4 2 DDRB_DQ7 1 DDRB_DQ6 DDRB_DQ3 DDRB_DQS0 DDRB_DQ1 13 13 13 13 13 DDRB_DQ15 DDRB_DQ14 DDRB_DQS10 DDRB_DQ13 DDRB_DQ2 DDRB_DQS9 1 4 3 2 1 4 3 2 DDRB_DQ8 13 13 DDRB_DQ16 DDRB_DQ20 DDRB_DQ11 DDRB_DQ10 DDRB_DQS1 DDRB_DQ12 DDRB_DQ9 2 1 4 3 2 1 4 3 2 13 13 13 13 13 13 13 13 13 13 13 DDRB_DQS14 DDRB_DQ42 DDRB_DQS5 DDRB_DQ41 DDRB_DQ45 DDRB_DQ38 DDRB_DQS13 DDRB_DQ34 DDRB_DQS4 DDRB_DQ44 DDRB_DQ40 DDRB_D
20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22,23,24 20,22
20,21,23,24 20,21,23,24 20,21,23,24 20,21,23,24 20,21,23,24 20,21,23,24 20,21,23,24 20,21,23,24 20,21,23,24 20,21,23,24 20,21,23,24 DDRB_CB4_R DDRB_DQS17_R DDRB_DQS8_R DDRB_CB3_R DDRB_CB2_R DDRB_CB1_R DDRB_CB0_R DDRB_DQ63_R DDRB_DQ62_R DDRB_DQ61_R DDRB_DQ60_R DDRB_DQS16_R DDRB_DQS7_R DDRB_DQ59_R DDRB_DQ58_R DDRB_DQ57_R DDRB_DQ56_R DDRB_DQ55_R DDRB_DQ54_R DDRB_DQ53_R DDRB_DQ52_R DDRB_DQS15_R DDRB_DQS6_R DDRB_DQ51_R DDRB_DQ50_R DDRB_DQ49_R DDRB_DQ48_R DDRB_DQ47_R DDRB_DQ46_R DDRB
20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 19,20,21,22 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 20,21,22,24 19,20,21,22 20,21,22,24 19,20,21,22 19,20,21,22 20,21,22,24 19,20,21,22 20,21,22,24 20,21,22
DDRB_DQ52_R DDRB_DQS15_R DDRA_CS3_N_R DDRB_CS3_N_R DDRB_CS2_N_R DDRB_DQ34_R DDRB_BA0_R DDRB_DQ39_R DDRB_DQ35_R DDRB_DQS1_R DDRB_DQ13_R DDRB_DQS10_R DDRB_DQ15_R 20,21,22,23 20,21,22,23 20,21,22,23 20,21,22,23 12,17 13,22 13,22 20,21,22,23 13,21,22,23 20,21,22,23 20,21,22,23 20,21,22,23 20,21,22,23 20,21,22,23 20,21,22,23 39.
8 7 6 5 4 3 2 1 P64H2 #1 - PCI.
8 7 6 5 4 3 2 1 P64H2 #1 - PCI.
8 7 6 5 4 3 2 1 P64H2 #1 - Hot Plug Interface +V1_8 D D R262 750 1% R261 332 1% C117 R1085 0 0.01UF +V5_0 +V3_3 C115 0.1UF +V1_8 AD24 VCC5REF1 G1 VCC5REF2 P64H2 HI_VSWING G10 P64H2_1_VSWING HI_VREF F11 P64H2_1_VREF HI_RCOMP F9 C118 C116 0.01UF 0.1UF R284 261 1% R260 61.9 1% P64H2_1_RCOMP R274 R273 R272 R263 R267 PUSTRBS C14 P64H2_1_PUSTRBS 8.2K 8.2K 8.2K 8.2K 8.
P64H2 VSS32 VSS31 VSS30 VSS29 VSS28 VSS27 VSS26 VSS25 VSS24 VSS23 VSS22 VSS21 VSS20 VSS19 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS114 VSS113 VSS112 VSS111 VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104 VSS103 VSS102 VSS101 VSS100 VSS99 VSS98 VSS97 VSS96 VSS95 VSS94 VSS93 VSS92 VSS91 VSS90 VSS89 VSS88 VSS87 VSS86 VSS85 VSS84 VSS83 VSS82 VSS81 VSS33 VSS115 VSS1 VSS34 VSS136 VSS135
8 7 6 5 4 3 2 1 P64H2 #2 - PCI.
8 7 6 5 4 3 2 1 P64H2 #2 - PCI.
8 7 6 5 4 3 2 1 P64H2 #2 - Hot Plug Interface +V1_8 D D R312 750 1% +V5_0 C129 C127 R306 332 0.01UF R1086 0 0.1UF 1% +V3_3 AD24 VCC5REF1 G1 VCC5REF2 P64H2 HI_VSWING G10 P64H2_2_VSWING HI_VREF F11 P64H2_2_VREF C130 C128 0.01UF 0.1UF +V1_8 R302 261 10K R300 8.2K R301 8.2K R315 R316 8.2K R317 8.2K R305 61.
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 P64H2 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 K13 K16 K17 K2 K20 K23 K5 K8 K9 L12 L13 L16 L17 L21 L3 L24 L8 L9 M10 M11 M14 M15 M22 M4 N10 N11 N14 N15 N2 N20 N23 N5 P12 P13 P16 P17 P21 P24 P3 P8 P9 R1 R12 R13 R16 R17 R4 R22 R8 R9 T10 T11 T14 T2 T15 T20 C332 0.1UF C749 0.1UF C750 0.1UF C755 0.1UF C751 C754 0.1UF C753 0.1UF C752 0.1UF C136 0.
8 7 6 5 4 3 2 1 P64H2 #1 - PCI.X Pull-Ups +V3_3 +V3_3 RP192 D RP60 26,43 P64H2_1_PB_IRQ6 8 1 26,42 P64H2_1_PB_IRQ3 7 2 3 P64H2_1_PA_IRQ15 8 1 26 P64H2_1_PB_IRQ11 6 P64H2_1_PA_IRQ0 7 2 26 P64H2_1_PB_IRQ12 5 25 P64H2_1_PA_IRQ7 6 3 25,35 P64H2_1_PA_IRQ1 5 4 25 25,35 8.
8 7 6 5 4 3 2 1 +V3_3 RP122 30 P64H2_2_PB_IRQ13 1 8 30,60 P64H2_2_PB_IRQ5 2 7 30,60 P64H2_2_PB_IRQ1 3 6 29 P64H2_2_PA_IRQ15 4 5 8.2K D +V3_3 P64H2 #2 - PCI.
8 7 6 5 4 3 2 1 Gigabit Ethernet Controller (Part 1) D D P64H2_1_PA_CBE[7:0]_N P64H2_1_PA_AD0 T14AD0 CBE0_NY13 P64H2_1_PA_CBE0_N V14AD1 CBE1_NV10 P64H2_1_PA_CBE1_N P64H2_1_PA_AD2 Y15AD2 CBE2_NT8 P64H2_1_PA_CBE2_N P64H2_1_PA_AD3 W14AD3 CBE3_NY4 P64H2_1_PA_CBE3_N P64H2_1_PA_AD4 T13AD4 CBE4_NV16 P64H2_1_PA_CBE4_N P64H2_1_PA_AD5 V13AD5 CBE5_NY18 P64H2_1_PA_CBE5_N P64H2_1_PA_AD6 Y14AD6 CBE6_NY17 P64H2_1_PA_CBE6_N P64H2_1_PA_AD7 U12AD7 CBE7_NT15 P64H2_1_PA_CBE7_N P64H2_1_P
8 7 6 5 4 3 2 1 Gigabit Ethernet Controller (Part 2) D D +V3_3 R326 100K C B P64H2_1_PA_AD32 L16AD32 SERR_NT10 P64H2_1_PA_SERR_N P64H2_1_PA_AD33 M20AD33 PERR_NY10 P64H2_1_PA_PERR_N P64H2_1_PA_AD34 M19AD34 P64H2_1_PA_AD35 M16AD35 VIO1Y1 P64H2_1_PA_AD36 M18AD36 VIO2Y20 P64H2_1_PA_AD37 M17AD37 P64H2_1_PA_AD38 N20AD38 ZN_COMP T2 P64H2_1_PA_AD39 N16AD39 ZP_COMP R5 P64H2_1_PA_AD40 P20AD40 P64H2_1_PA_AD41 N18AD41 P64H2_1_PA_AD42 P19AD42 P64H2_1_PA_AD43 P16AD43 P64H2_1_
8 7 6 5 4 3 2 1 Gigabit Ethernet Controller (Part 3) D D +V3_3 CS1 CLK 2 C183 7NC 0.01UF 6ORG DI3 5GND DO4 EE_DI C19EE_DI SDPA0G4 EE_DO B20EE_DO SDPA1G5 EE_CS C20EE_CS SDPA6E12 EE_SK D20EE_SK SDPA7E11 +3_3V SDPB0D13 U36 F16FL_ADDR0 SDPB1B12 E18FL_ADDR1 SDPB6C12 E16FL_ADDR2 SDPB7D12 R9999 8VCC E15FL_ADDR3 E14FL_ADDR4 SMBALRT_NA16 E13FL_ADDR5 SMBDATA15 I2C_BUS2_DAT D15FL_ADDR6 SMBCLK A14 I2C_BUS2_CLK 8.
VDD18 DVDD21 DVDD20 DVDD19 DVDD18 GND30 G7 G8 G9 G12 G14 H7 H8 H13 H14 J7 J14 M7 M14 N7 N8 N13 P7 P8 P9 P12 P13 P14 A18 F2 J9 J10 J11 J12 J13 K2 K4 K5 K7 K8 XSTR_BCP69T1 DVDD0 DVDD1 DVDD5 VDD19 DVDD22 GND31 KC533 1 85 OF 38 Folsom, California 095630 11/18/02 LAST REVISED: 1900 Prairie City Road PROJECT: DRAWN BY: Intel Corporation R 1.0 Rev: INTEL (R) E7501 CHIPSET CUSTOMER REFERENCE BOARD TITLE: 10UF 10UF C196 C195 0.01UF 4.7UF C193 0.
8 7 6 5 4 3 2 1 Gigabit Ethernet Controller (Part 5) D D L19GND1 NC1A11 M4GND2 NC2A12 M8GND3 NC3F4 M9GND4 NC4F5 M10GND5 NC5F19 M11GND6 NC6F20 M12GND7 NC7G19 M13GND8 N9GND9 +V3_3 C C367 0.01UF C368 0.01UF C369 C370 0.01UF 0.01UF C371 0.01UF C372 0.01UF C373 0.01UF C374 0.
8 7 6 5 4 3 2 1 Dual RJ-45 Ethernet Connectors R339 R340 300 PORT1_ACTIVITY_N PORT1_LINK_N 37 37 300 D +V2_5 PORT1_MDI[0]- 37,41 PORT1_MDI[1]- 37,41 PORT1_MDI[2]- 37,41 PORT1_MDI[3]- 37,41 +V2_5 2727 C1759 0.01UF 2828 C1760 0.01UF 2525 PORT1_MDI[3]+ 37,41 37,41 PORT1_MDI[2]+ 37,41 PORT1_MDI[1]+ 1919 1717 2626 2222 2424 1414 1818 2020 C1761 0.01UF C1762 0.01UF 1616 PORT1_MDI[0]+ 37,41 2323 99 2121 44 1515 1212 C1765 0.01UF C1766 0.01UF C1763 0.
8 7 6 5 4 3 2 1 Ethernet Port Terminators D D 37,40 PORT2_MDI[0]+ 37,40 PORT2_MDI[0]- PORT1_MDI[3]- 37,40 PORT1_MDI[3]+ 37,40 PORT1_MDI[2]37,40 37,40 PORT2_MDI[1]+ PORT1_MDI[2]+ 37,40 37,40 PORT2_MDI[1]- C C 37,40 PORT2_MDI[2]+ 37,40 PORT1_MDI[1]- PORT2_MDI[2]- PORT1_MDI[1]+ PORT2_MDI[3]+ 37,40 37,40 PORT1_MDI[0]- PORT2_MDI[3]- 37,40 1% 1% 1% 1% 1% 1% 49.9 49.9 R355 49.9 1% R354 49.9 1% R358 49.9 1% R353 49.9 R357 49.9 1% R352 49.9 1% R351 49.
8 7 6 5 4 +V5_0 3 2 1 PCI-X 100MHz (Slot 1) +V3_3 -V12 J26 PCI_SLOTS_TCK 43,65 -12V B2 TCK +12V GND_S TMS TDO TDI B3 D +V12 B1 B4 B5 B6 26,33 P64H2_1_PB_IRQ1 B7 26,33 P64H2_1_PB_IRQ3 B8 B9 B10 B11 TRST_N +5V_E +5V_A +5V_F INTA_N INTB_N INTC_N INTD_N +5V_B PRSNT1_N RESV_A RESV_E 3_3V_A PRSNT2_N RESV_B A1 PCI_SLOTS_TRST_N 43,60,65 A2 A3 SLOT_2_TMS 42 A4 SLOT_2_TDI 42 D J26 A5 A6 P64H2_1_PB_IRQ0 26,33 A7 P64H2_1_PB_IRQ2 26,33 continued KEY B63 CL
8 +V3_3 7 6 5 +V5_0 4 3 J27 PCI_SLOTS_TCK 42,65 +V12 B1 -12V B2 TCK +12V GND_S TMS TDO TDI B3 D B4 B5 B6 26,33 P64H2_1_PB_IRQ5 B7 26,33 P64H2_1_PB_IRQ7 B8 B9 B10 B11 TRST_N +5V_E +5V_A +5V_F INTA_N INTB_N INTC_N INTD_N +5V_B PRSNT1_N RESV_A RESV_E 3_3V_A PRSNT2_N RESV_B A1 PCI_SLOTS_TRST_N 42,60,65 A2 A3 SLOT_3_TMS A4 SLOT_3_TDI 43 D J27 43 A5 A6 P64H2_1_PB_IRQ4 26,33 A7 P64H2_1_PB_IRQ6 26,33 continued KEY B63 CLK1 B64 GND_DD CBE7_N CBE6_N CB
8 7 6 5 4 3 2 1 I/O Processor (Part 1) +V2_5 D 2.
8 7 6 5 4 3 2 1 I/O Processor (Part 2) IOP DDR Interface D D C B IOP_MA[12:0] D10 DQ31 DQ63P 4 IOP_DQ63 IOP_DQ30 A11 DQ30 DQ62N1 IOP_DQ62 IOP_DQ29 B12 DQ29 DQ61M2 IOP_DQ61 IOP_DQ28 A13 DQ28 DQ60L1 IOP_DQ60 IOP_DQ27 C11 IOP_DQ26 IOP_DQ25 D11 P1 DQ59 IOP_DQ59 DQ26 D12 DQ25 DQ58N3 DQ57M1 IOP_DQ58 IOP_DQ57 IOP_DQ24 C13 DQ24 DQ56M4 IOP_DQ56 IOP_DQ23 C14 DQ23 DQ55K 4 IOP_DQ55 IOP_DQ22 E15 DQ22 DQ54K 2 IOP_DQ54 IOP_DQ21 IOP_DQ20 B16 A17 DQ21 DQ20 DQ53J4 D
8 7 6 5 4 3 2 I/O Processor (Part 3) 1 IOP_PCE0 46 IOP_PCE1 46 IOP PCI.
IOP_RS_DQS[8:0] IOP_RS_DM[8:0] IOP_RS_CB[7:0] IOP_RS_DQ0 IOP_RS_DQ1 IOP_RS_DQ2 IOP_RS_DQ3 IOP_RS_DQ4 IOP_RS_DQ5 IOP_RS_DQ6 IOP_RS_DQ7 IOP_RS_DQ8 IOP_RS_DQ9 IOP_RS_DQ10 IOP_RS_DQS0 IOP_RS_DM0 IOP_RS_DQS1 IOP_RS_DM1 IOP_RS_DQS2 IOP_RS_DM2 IOP_RS_DQS3 IOP_RS_DM3 IOP_RS_DQS4 IOP_RS_DM4 IOP_RS_DQS5 149 56 60 57 55 53 133 131 127 126 129 36 40 39 35 33 123 121 117 114 119 25 31 28 24 23 110 109 106 105 107 14 20 19 13 12 99 98 95 94 97 5 8 6 4 2 DQ37 DQ36
8 7 6 5 4 3 2 1 I/O Processor Local Memory Series Resistors D D 47,49 47,49 47,49 47,49 IOP_RS_DQ26 1 IOP_RS_DQ30 2 IOP_RS_DQ27 3 IOP_RS_DQ31 RP291 10 4 8 IOP_DQ26 7 IOP_DQ30 6 IOP_DQ27 5 45 45 IOP_DQ31 IOP_RS_DQ0 1 47,49 IOP_RS_DQ4 2 47,49 IOP_RS_DQ5 3 RP283 4 10 47,49 IOP_RS_DQ1 47,49 45 45 8 IOP_DQ0 7 IOP_DQ4 6 IOP_DQ5 5 IOP_DQ1 45 47,49 45 47,49 45 47,49 45 IOP_RS_DQ41 1 IOP_RS_DQS5 2 IOP_RS_DM5 3 IOP_RS_DQ42 4 RP300 10 8 IOP_DQ41 7
8 7 6 5 4 3 2 1 I/O Processor Local Memory Termination Resistors D D 1 2 VTT_DDR 3 RP334 4 60.4 1% 1 2 3 1 2 3 4 RP312 60.4 8 IOP_RS_DQ0 47,48 7 IOP_RS_DQ4 47,48 6 IOP_RS_DQ5 5 IOP_RS_DQ1 VTT_DDR 47,48 47,48 1 8 IOP_RS_DM0 47,48 7 IOP_RS_DQS0 47,48 3 RP313 6 IOP_RS_DQ2 47,48 4 60.4 5 IOP_RS_DQ6 47,48 8 2 3 4 7 RP322 60.4 1% 1% 1 8 IOP_RS_DQ7 2 7 IOP_RS_DQ3 3 RP314 6 IOP_RS_DQ8 4 60.4 5 IOP_RS_DQ12 1 2 3 4 RP315 60.
8 7 6 5 4 3 2 1 I/O Processor ROM D D IOP_ROM_AD[32:0] 50 IOP_BE[15:0] 46 +V3_3 H3VCC2 DQ15E7 IOP_ROM_AD15 A6VCC1 DQ14G7 IOP_ROM_AD14 G4VCC_Q DQ13H5 IOP_ROM_AD13 DQ12F5 IOP_ROM_AD12 IOP_ROM_AD[32:0] 50 U60 74LVC573A 2 D0 Q0 19 DQ11F4 IOP_ROM_AD11 C8A21 DQ10F3 IOP_ROM_AD10 IOP_ROM_AD20 C7A20 DQ9E3 IOP_ROM_AD9 IOP_ROM_AD19 B7A19 DQ8E1 IOP_ROM_AD8 DQ7H7 IOP_ROM_AD7 IOP_ROM_AD17 D8A17 DQ6G6 IOP_ROM_AD6 IOP_BE13 IOP_ROM_AD16 D7A16 DQ5G5 IOP_ROM_AD5 6 D4 7 D5
8 7 6 5 4 3 2 1 I/O Processor Decoupling D D +V3_3 C1776 C1775 0.01UF C1876 0.01UF C1875 0.01UF C1873 0.01UF 0.01UF C1874 C1878 0.01UF C1877 0.01UF 0.01UF C1880 C1879 0.01UF 0.01UF C C +V2_5 +V3_3 +V3_3 +V2_5 C1779 1000PF C1780 1000PF C1782 C1781 1000PF C1786 1000PF C1899 1000PF 10UF C1900 C1902 10UF 10UF C1901 10UF C1904 10UF C1903 C1910 10UF 10UF C1909 10UF C1908 C1907 10UF C1906 10UF C1789 C1905 10UF 0.1UF 10UF C1790 0.1UF C1791 0.
R673 0 100 R679 PCI Memory INTA AB3 INTB TDO P64H2_2_PA_AD46 AE22 AD22 AC22 SCSI_IRQ0 SCSI_IRQ1 AF16 AD15 AC15 P64H2_2_PA_FRAME_N P64H2_2_PA_PAR64 P64H2_2_PA_REQ64_N P64H2_2_PA_ACK64_N P64H2_2_PA_REQ1_N AD7 P64H2_2_PA_IRDY_N AE8 AF8 AE16 AD16 AC16 AE15 P64H2_2_PA_CBE2_N P64H2_2_PA_CBE3_N P64H2_2_PA_CBE4_N P64H2_2_PA_CBE5_N P64H2_2_PA_CBE6_N P64H2_2_PA_CBE7_N ROMOE T23 AB23 N24 BRDOE N25 T24 T25 R25 R24 T26 P25 P23 P26 R23 U23 U24 U25 U26 V23 V24 V25 W23 AA23 Y26 Y25
RP282 DIFFSENSEA_R 57,58 57,58 57,58 LVSCDAP15 LVSCDAP14 LVSCDAP13 LVSCDAP12 LVSCDAP11 LVSCDAP10 LVSCDAP9 LVSCDAP8 LVSCDAP7 LVSCDAP6 SCDAM15 SCDAP3 A20 SCDAP4 SCDAP5 A21 SCDAP6 SCDAP7 E23 SCDAP8 F25 SCDAP9 F23 SCDAP10 SCDAP11 SCDAM2 SCDAM3 SCDAM4 SCDAM5 SCDAM6 SCDAM7 SCDAM8 SCDAM9 SCDAM10 SCDAM11 SCDAM12 SCDAM13 SCDAP15 D17 SCDAP13 SCDAM14 SCSI Misc.
C1323 1UF C1321 0.01UF C1324 0.1UF SCSI_CORE_VCC C1320 1UF 0.01UF C1322 0.
8 7 6 5 4 3 2 1 Adaptec* 7902 SCSI Controller SCSI_CORE_VCC 54,56 1 + C1428 10UF D 2 C1335 0.01UF D 70OHMS SCSI_CORE_VCCA_PX 1 + FB6 10UF 2 C1333 0.
8 7 6 5 4 3 2 1 AIC-7902 SCSI Decoupling +V3_3 D C1361 0.01UF C1360 C1359 0.01UF C1358 0.01UF C1357 0.01UF C1356 0.01UF C1355 0.01UF C1354 0.01UF C1353 0.01UF C1352 0.01UF 0.01UF C1351 0.01UF C1350 C1349 0.01UF 0.01UF C1348 C1347 0.01UF C1346 0.01UF 0.01UF C1345 0.01UF C1344 0.01UF C1343 0.01UF C1342 0.01UF D CAD NOTE: +V3_3 +V3_3 +V5_0 Use flood or fat trace for SCSI_AGND 70OHMS SCSI_AGND C1368 C1367 0.01UF 0.01UF C1366 C1365 0.01UF 0.
8 7 6 5 4 3 2 1 SCSI Connectors A and B D D +V5_0 +V5_0 MBRD320 MBRD320 RT4 RT3 1 2 1 3 CR46 2 1 LVTRMPWR_A 2 POLYSWITCH 3.
8 7 6 5 4 3 2 1 LVD/SE Termination for SCSI Channel A 55,57 LVTRMPWR_A Use 40 mil trace C1434 C1668 + 0.
8 7 6 5 4 3 2 1 LVD/SE Termination for SCSI Channel B 55,57 LVTRMPWR_B 1 40 MIL trace + U96 C1388 C1441 10UF 16 0.
8 7 +V3_3 6 5 4 +12V 30,34 P64H2_2_PB_IRQ4 GND_S TMS TDO TDI B4 B5 B6 30,34 P64H2_2_PB_IRQ1 B7 30,34 P64H2_2_PB_IRQ3 B8 B9 B10 P64H2_2_PB_GNT2_N 30 B11 TRST_N +5V_E +5V_A +5V_F INTA_N INTB_N INTC_N INTD_N +5V_B PRSNT1_N RESV_A RESV_E 3_3V_A PRSNT2_N RESV_B A1 PCI_SLOTS_TRST_N 42,43,65 A2 A3 SLOT_A_TMS 60 A4 SLOT_A_TDI 60 D J28 A5 A6 P64H2_2_PB_IRQ0 30,34 A7 P64H2_2_PB_IRQ2 30,34 continued KEY P64H2_2_PB_PCLK1 A8 +VSBY3_3 A9 P64H2_2_PB_REQ1_N 30,34 3
8 7 6 5 4 3 2 1 +V3_3 +V3_3 ICH3 (PART 1 0F 4) ICH3_AD[31:0] 4 U69 5 6 74LVC125 PCIRST2_5_N 11,16,17,18,21,22,23 H5 AD4 ICH3_AD5 K4 AD5 ICH3_AD6 H3 AD6 A20M_N V23 ICH3_AD7 L1 AD7 CPUSLP_N W21 ICH3_AD8 L2 AD8 FERR_N J22 ICH3_FERR_N ICH3_AD9 G2 AD9 IGNNE_N AA21 ICH3_IGNNE_N ICH3_A20M_N 4,6,9 ICH3_CPUSLP_N 4,6,9 L4 AD10 INIT_N AB23 ICH3_AD11 H4 AD11 INTR AA23 ICH3_LINT0_INTR ICH3_AD12 M4 AD12 NMI Y21 CPU_LINT1_NMI 4,6,9 ICH3_SMI_N 4,6,9 J3 AD13 ICH3_AD14 M5
8 7 6 5 4 3 2 1 +V3_3 ICH3-S (Part 2) ICH3 (PART 2 0F 4) U5 R651 ICH3_VCC_RTC 10K D ICH3_INTRUDER_N ICH3_SMBALERT_N AB2 SMLINK1 Y6 INTRUDER_N AC5 SMBALERT_N_GPIO11 71 ICH3_SMBCLK AC4 SMBCLK 71 ICH3_SMBDATA AB5 SMBDATA +VSBY3_3 71 ICH3_SMBUS_SEL1 Y3 GPIO28 71 ICH3_SMBUS_SEL0 W4 GPIO27 6,7 CPU0_SMB_PRT W3 GPIO25 4,5 CPU1_SMB_PRT AC2 GPIO24 ICH3_GPIO23 U20 GPIO23 ICH3_GPIO22 Y20 GPIO22 +V3_3 R691 10K R690 10K ICH3_GPIO21 10K V21 GPIO20 ICH3_GPIO19 W20 GPIO19 ICH3_
8 7 6 5 4 3 2 1 ICH3-S (Part 3) +VSBY3_3 8.2K R703 ICH3 (PART 3 0F 4) +V3_3 D D VCC3_3_10 H18 VCC3_3_11 P12 78 ICH3_RSMRST_N AA7 RSMRST_N VCC3_3_12 V15 ICH3_SUS_STAT_N AB4 SUS_STAT_N VCC3_3_13 V16 ICH3_SUSCLK AA4 SUSCLK VCC3_3_14 V17 ICH3_VRDPWRGD R657 V19 VRMPWRGD VCC3_3_15 V18 VCC1_8_1 J18 VCC1_8_2 M14 4.
8 7 6 5 4 3 2 1 ICH3-S (Part 4) +V3_3 GND5 GND57 N21 A22 GND6 GND58 N23 A23 GND7 GND59 P20 GND60 B10 GND9 GND61 R3 B13 GND10 GND62 R5 GND63 B15 GND12 GND64 R23 B18 GND13 GND65 T4 B19 GND14 GND66 T20 B20 GND15 GND67 T22 B22 GND16 GND68 V3 GND20 GND72 W10 C16 GND21 GND73 W14 C17 GND22 GND74 W18 C18 GND23 GND75 W22 C19 GND24 GND76 Y8 C20 GND25 GND77 AA3 C21 GND26 GND78 AA8 C22 GND27 GND79 AA12 D9 GND28 GND80 AA16 D13 GND29 GND
8 7 6 +V3_3 5 +V5_0 +V3_3 4 3 2 1 PCI-33 (ICH3-S) Connector, Termination, and Decoupling +V3_3 +V12 A2 D 65 PCI33_TMS A3 65 PCI33_TDI A4 A5 61,65 27,61,65,66 ICH3_PIRQC_N A6 ICH3_PIRQA_N A7 A8 PCI33_CLKRUN_N +VSBY3_3 A9 A10 R725 10K A11 A16 ICH3_GNT0_N 61 ICH3_PME_N 36,42,43,60,61 A17 A18 R723 0 A19 PCI33_PME_N NOPOP ICH3_AD30 C CLK GNT- GND GND REQ- PME# +5V B12 B13 B14 PCI33_CLK33 ICH3_REQ0_N A31 ICH3_AD16 A32 A34 A36 A38 65 PCI33_SDONE A40 65 P
61,65 ICH3_AD16 61,65,66 +V3_3 80 61,65 61,65 61,65 61,65 NOPOP 80 61,65 61,65 61,65 61,65 61,65 61,65 61,65 61,64,65 ICH3_AD[31:0] R735 100 R734 4.
+V3_3 4.
8 7 6 5 4 3 2 1 FWH +V3_3 +V3_3 D D 4.7K 1 R756 R757 4.
8 7 6 5 4 3 2 1 Super I/O +V3_3 R764 62 ICH3_LDRQ0_N SIO_LDRQ0_N +V5_0 +V3_3 69 0 22 ICH3_LAD1 21 ICH3_LAD0 20 SIO_LDRQ0_N 61 80 LFRAME~ LAD3 66 LPT_INIT_N 70 67 LPT_SLCTIN_N 70 75 LPT_PD7 70 74 LPT_PD6 70 PD5 73 LPT_PD5 70 LPT_PD4 70 INIT~ SLCTIN~ LAD2 PD7 LAD1 PD6 LAD0 25 LDRQ~ PD4 72 PCIRST_2_N 26 PCI_RESET~ PD3 71 LPT_PD3 70 SIO_SUS_STAT_N 27 LPCPD~ PD2 70 LPT_PD2 70 PD1 69 LPT_PD1 70 PD0 68 LPT_PD0 70 SLCT 77 LPT_SLCT SIO_PME_
8 7 6 5 4 50OHMS RT7 2 V5_KB_RT V5_KB 1 Serial Port Header J44 C1683 C1684 RP146 2.7K 0.01UF 1 2 3 4 1000PF FB14 THRMSTR 1.
8 7 6 5 4 3 2 1 SMBus Isolation and Voltage Translation SMBus Mux +VSBY5_0 +VSBY5_0 R768 +VSBY5_0 71 I2C_BUS0_DAT_3V C1692 0.1UF 2 1A 2OE_N7 3 1B 2B 6 4 GND 2A 5 4.7K C1693 VCC8 1OE_N 4.7K 1 +VSBY3_3 R770 D SN74CBTD3306 R769 I2C_BUS0_EN_N 4.7K D 0.
8 7 6 5 4 3 2 1 +V5_0 +V5_0 +V5_0 R1576 R1582 MBRA130 2 VR_130_PRDY4 VRD_OFF_N +V5_0 1K R1581 R1575 1 CR50 10K 74 R1583 10K +V5_0 C2158 0.1UF 10K VR_130_RP_XSTR D 10K D VR_130_SMOD 8VCC BST14 7PRDY VR130_EN VR_130A_PWM4_CO 6 4 1 2N3904_DUAL 2 C2168 C2167 22PF BG9 6DELAY_C VR_130A_TGATE4 0 DSPS_DR11 10UF 73 VR_130A_DRN4 72,73 R1552 PGND10 VR_130A_BG4 VR_130A_BGATE4 5S_MOD 73 1 3GND +V5_0 35.7K R1578 C2166 10 R1559 0.
8 7 6 5 3 2 1 CPU VOLTAGE REGULATOR DOWN(2 OF 2) +V12_CPU L21 1 VR_130A_DRN_IN 2 73 C2147 + 2 2 2 270UF C2144 270UF + C2146 1 270UF 270UF C2145 + 1 1 1 200NH + 4 2 VR_130A_DRN_IN 73 D D Q92 3 3 D C2149 C2148 10UF 10UF D C2153 R1587 0 Q104 NO POP Q105 3 2 G S 2.
8 7 6 5 4 3 2 1 CPU Load Line Circuitry & VID Manual Override(Debug Only) D D +V3_3 C1707 0.
8 7 6 5 3 2 1 DDR Voltage Regulator(2.5V) +V5_0 1_2V_PWRGD 4 XREF=77,79 R1657 R1640 5% 22K R1639 0.1UF D 1K NO POP 1 1UF 1 2 2 C2224 L22 1 C2221 NO POP +V2_5 1UF + 3 2N3904 C2207 + 270UF C2206 270UF 270UF C2228 1UF R1636 1 1 2 1% 475 2 2 2 2 2 1 Q123 1% 4 VID1 PWM115 5 VID0 ISEN417 7 FB ISEN312 9 GND ISEN213 6 COMP ISEN116 C2247 R1644 1.3K 1 1UF BST14 7PRDY R1662 5% 22 IRF7811 S 1 DRN12 4CO BG9 2 G S 10UF 0.
8 7 6 5 4 3 2 1 DDR VTT Regulation +V2_5 +V5_0 +V5_0 R1671 2 D D 3 + C2271 1000PF C2272 560UF 560UF C2280 2 2 L6910 C 1 VREF 2 OSC 3 NC 16 VCC 15 OCSET LGATE 14 4 SS/INH PGND 13 5 COMP BOOT 12 6 FB HGATE 11 7 GND PHASE 10 S 9 1 EAREF PGOOD Q135 2 NO POP C2286 R1679 3 C D G C2285 8 NO POP 1K U167 IRF7811 + 10UF 1K C2266 10UF 1 1 C2267 R1678 0.2UH CR56 1 10UF 2 MMBD354LT1 2 C2269 L25 1 VTT_DDR 0.
8 7 6 5 4 3 2 1 +V12 1 + 1500UF C282 +V5_0 2 1.8V / 1.2V Voltage Regulator C279 D D 1UF 1UF G C286 S MBRS0520 MMBF170 C274 1 1 1 3 D 2 MBR0520L 2 CR3 47UF CR26 Q122 C287 C275 C275 +V1_2 2 1UF 0.1UF Q23 2 FDP6035AL D 0.1UF 1AGND ILIM218 12SS1 SS217 13DDR VREF/PWRGD216 C2187 10UF 10UF C2140 1000PF C 3 R854 316 1% PWRGD115 C280 0.1UF R865 FAN5236 U26 0.1UF 82.5K 1_2V_PWRGD 75,79 78.
8 7 6 5 4 3 2 1 Standby Voltage Regulators D D +VSBY5_0 +VSBY1_8 +VSBY3_3 C2200 C2196 7GND1 VIN2 6GND2 VO3 5GND3 ADJ4 R1620 0 0 0 C2201 10UF R1628 180 C2202 62 10UF R1624 NO POP SC1565 R1622 C 1 R1623 EN1 2 BAT54C U163 8GND0 CR53 3 10UF 10UF R1629 180 C2197 C2198 C2199 10UF 10UF 10UF R1627 1EN GND08 2VIN GND17 3VO GND26 4ADJ GND35 SC1565 C U162 187 R1626 0 107 R1621 Standby supply monitor +VSBY1_8 +VSBY5_0 1.
8 7 6 5 4 3 2 1 PWROK Circuitry D D +V3_3 CR15 BAV70LT1 1 C PS_PWROK 74,80,82 R1263 10K +VSBY3_3 +VSBY3_3 3 1_8V_PWRGD 77,80 R877 1 2 3 1_8V_PWRGD_BUFF 74LVC125 14 U99 7 74LVC14 1 ALL_VOLTAGES_OK U151 74LVC14 C R1145 4 SYS_PWROK_1 10,36,81 0 +VSBY3_3 0 1_2V_PWRGD U99 7 2 R879 75,77 14 3 +VSBY3_3 R875 10K 2 14 U99 7 74LVC14 5 R1146 6 SYS_PWROK_2 NOPOP 27,31,46,63 0 0 R876 FP_RESET_SW_N 81 76 DDR_VTT_PWRGD 75 2_5V_PWRGD 0 R883 SPST Switch 0 R
8 7 6 5 4 3 2 1 CK-408B Clock Synthesizer CAD NOTE: Place close to CK 408B <1" R911 63 +V3_3 69 V3_CLK_A ITP_BCLK0 CLK_14MHZ_SIO ITP_BCLK1 33 5% 22 4 VSS CPU_353 33 5 PCIF0 CPU052 R894 6 PCIF1 CPU_051 7 PCIF2 VDD650 8 VDD1 CPU149 9 VSS1 CPU_148 VDD446 PCI2 CPU245 13 PCI3 CPU_244 R925 14 VDD2 15 VSS2 16 PCI4 17 PCI5 18 PCI6 19 VDD3 SIO_CLK33 69 5% 33 R912 B P64H2_1_CLK66 27 20 R913 43 P64H2_2_CLK66 31 21 66BUFF0_3V66_2 VSS_48MHZ36 22 66BU
8 7 6 5 4 3 2 1 Front Panel Connector / Floppy Connector D D Floppy Connector Front Panel Connector J52 1 2 3 4 6 C DRVEN0 69 DRVEN1 69 7 8 INDEX_N 69 9 10 MTR0_N 69 11 12 13 14 DS0_N 69 15 16 17 18 DIR_N 69 19 20 STEP_N 21 22 WDATA_N 23 24 WGATE_N 25 26 TRK0_N 27 28 29 30 31 32 33 34 +VSBY5_0 79 10,36,79 69 2 3 4 SYS_PWROK_1 5 6 7 8 ICH3_PWRBTN_N 63 69 1 FP_RESET_SW_N C 9 69 11 12 69 13 WRTPRT_N 69 15 RDATA_N 69 HDSEL_N 6
8 7 6 5 4 3 2 1 Power Connectors +VSBY5_0 C1719 0.1UF C609 0.1UF C608 0.1UF C1715 0.1UF C1725 0.1UF C1724 0.1UF +V12_CPU C1720 0.1UF D D 2X4PWR 5 1 6 2 7 3 8 +V5_0 4 C1723 0.1UF C1722 0.1UF C1721 0.1UF C617 0.1UF C610 0.1UF C611 0.1UF C612 0.1UF C1718 0.1UF J14 CPU +12V Power Connector +V12_CPU C1726 0.1UF C172 0.1UF C171 C64 0.
8 7 6 5 I2C BUS 0 I2C BUS 1 Partition Select 00 SMB Address = C2h P64H2 #2 SMB Address = C0h PCI-X Slot 1 Partition Select 11 (Default) DIMM A-1 Processor 0 Thermal Sensor CPU0 IDROM = A0h SMB Address = 30h SMB Address = A0h Processor 1 Thermal Sensor CPU1 IDROM = A2h SMB Address = 32h DIMM A-2 SMB Address = A2h PCI-X Slot 2 D DIMM A-3 SMB Address = A4h SMB Address = 60h Gigabit LAN SMB Address = C8h SMB Address Resolution Protocol 1 I2C BUS 3 MCH SMB Address Resolution Protocol +VSBY5
8 7 6 5 4 3 2 1 Mounting Holes D D MH11 MH10 MH9 MH8 C C MH4 MH1 MH6 B B A A INTEL (R) E7501 CHIPSET CUSTOMER REFERENCE BOARD TITLE: R DRAWN BY: Intel Corporation LAST REVISED: Folsom, California 095630 7 6 5 4 3 1.
8 7 6 5 4 3 2 1 PCI.X INTERRUPT MAPPING D D Component C IDSEL REQ/GNT IRQ 82546EB P64H2_1_PA_AD17 P64H2_1_PA_REQ/GNT0 P64H2_1_PA_IRQ[0:3] PCI.X Slot 2 P64H2_1_PB_AD17 P64H2_1_PB_REQ/GNT0 P64H2_1_PB_IRQ[0:3] PCI.X Slot 3 P64H2_1_PB_AD18 P64H2_1_PB_REQ/GNT1 P64H2_1_PB_IRQ[4:7] P64H2_2_PA_AD17 P64H2_2_PA_REQ/GNT0 P64H2_2_PA_IRQ[0:3] I/O Processor C B B SCSI PCI.
