Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsClock & Timing ICsTSSOP 14

General Description

The DS1110 delay line is an improved replacement for

the DS1010. It has ten equally spaced taps providing

delays from 5ns to 500ns. The devices are offered in a

standard 16-pin SO or 14-pin TSSOP. The DS1110 series

delay lines provide a nominal accuracy of ±5% or ±2ns,

whichever is greater, at 5V and +25°C. The DS1110

reproduces the input logic state at the tap 10 output after

a fixed delay as specified by the dash number extension

of the part number. The DS1110 is designed to produce

both leading- and trailing-edge delays with equal preci-

sion. Each tap is capable of driving up to ten 74LS type

loads. Dallas Semiconductor can customize standard

products to meet special needs.

Features

♦ All-Silicon, 5V, 10-Tap Delay Line

♦ Improved, Drop-In Replacement for the DS1010

♦ 10 Taps Equally Spaced

♦ Delays are Stable and Precise

♦ Leading- and Trailing-Edge Accuracy

♦ Delay Tolerance ±5% or ±2ns, whichever is

Greater, at 5V and +25°C

♦ Economical

♦ Auto-Insertable, Low Profile

♦ Low-Power CMOS

♦ TTL/CMOS Compatible

♦ Vapor Phase, IR, and Wave Solderable

♦ Fast-Turn Prototypes

♦ Delays Specified Over Commercial and Industrial

Temperature Ranges

♦ Custom Delays Available

♦ Standard 16-Pin SO or 14-Pin TSSOP

DS1110

10-Tap Silicon Delay Line

_____________________________________________ Maxim Integrated Products 1

TOP VIEW

TAP1

TAP3

TAP5TAP4

TAP2

N.C.

TAP7

TAP9

TAP10GND

TAP8

TAP6

TSSOP

DS1110E

Pin Configurations

Ordering Information

Rev 1; 11/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART

TEMP RANGE

PIN-PACKAGE

DS1110E-XXX -40°C to +85°C

14 TSSOP

DS1110S-XXX -40°C to +85°C

16 SO

Applications

Communications Equipment

Medical Devices

Automated Test Equipment

PC Peripheral Devices

Selector Guide appears at end of data sheet.

Pin Configurations continued at end of data sheet.

Summary of content (8 pages)

PAGE 1
Rev 1; 11/03 10-Tap Silicon Delay Line The DS1110 delay line is an improved replacement for the DS1010. It has ten equally spaced taps providing delays from 5ns to 500ns. The devices are offered in a standard 16-pin SO or 14-pin TSSOP. The DS1110 series delay lines provide a nominal accuracy of ±5% or ±2ns, whichever is greater, at 5V and +25°C. The DS1110 reproduces the input logic state at the tap 10 output after a fixed delay as specified by the dash number extension of the part number.
PAGE 2
DS1110 10-Tap Silicon Delay Line ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground .................-0.5V to +6.0V Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature...................See IPC/JEDEC J-STD-020A Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
PAGE 3
10-Tap Silicon Delay Line DS1110 CAPACITANCE (TA = +25°C.) PARAMETER Input Capacitance Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: CONDITIONS SYMBOL MIN TYP MAX UNITS 5 10 pF CIN All voltages are referenced to ground. Measured with outputs open. Initial tolerances are ± with respect to the nominal value at +25°C and VCC = 5.0V for both leading and trailing edges.
PAGE 4
Typical Operating Characteristics (continued) (VCC = 5.0V, TA = +25°C, unless otherwise noted.) DS1110-500 DELAY vs. TAP DS1110-50 DELAY vs. TAP 400 FALLING EDGE 45 40 350 35 300 DELAY (ns) RISING EDGE 250 200 150 30 RISING EDGE 25 20 15 100 10 500kHz INPUT 50 5 0 0 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 TAP TAP DS1110-500 TAP 10 DELAY vs. VOLTAGE DS1110-50 TAP 10 DELAY vs.
PAGE 5
10-Tap Silicon Delay Line Table 1. Part Number by Delay (tPHL, tPLH) The DS1110 delay line is an improved replacement for the DS1010. It has ten equally spaced taps providing delays from 5ns to 500ns. The devices are offered in a standard 16-pin SO or 14-pin TSSOP. The DS1110 series delay lines provide a nominal accuracy of ±5% or ±2ns, whichever is greater, at 5V and +25°C.
PAGE 6
DS1110 10-Tap Silicon Delay Line Terminology Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t WI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading edge. tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the input pulse.
PAGE 7
10-Tap Silicon Delay Line Output Each output is loaded with the equivalent of one 74FO4 input gate. Delay is measured at the 1.5V level on the rising and falling edge. Chip Information TRANSISTOR COUNT: 6813 DS1110 between the input and each tap. Each tap is selected and connected to the counter by a VHF switch-control unit. All measurements are fully automated, with each instrument controlled by a central computer over an IEEE-488 bus. Table 2.
PAGE 8
DS1110 10-Tap Silicon Delay Line Pin Configurations (continued) Package Information For the latest package outline information, go to www.maxim-ic. com/packages. TOP VIEW IN1 1 16 VCC N.C. 2 15 N.C. N.C. 3 TAP2 4 14 TAP1 DS1110S 13 TAP3 TAP4 5 12 TAP5 TAP6 6 11 TAP7 TAP8 7 10 TAP9 GND 8 9 TAP10 SO (300mil) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.