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DS1859

Dual, Temperature-Controlled Resistors with

Internally Calibrated Monitors

______________________________________________ Maxim Integrated Products 1

For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

General Description

The DS1859 dual, temperature-controlled, nonvolatile

(NV) variable resistors with three monitors consists of

two 50kΩ or two 20kΩ, 256-position, linear, variable

resistors; three analog monitor inputs (MON1, MON2,

MON3); and a direct-to-digital temperature sensor. The

device provides an ideal method for setting and tem-

perature-compensating bias voltages and currents in

control applications using minimal circuitry. The vari-

able resistor settings are stored in EEPROM memory

and can be accessed over the 2-wire serial bus.

Applications

Optical Transceivers

Optical Transponders

Instrumentation and Industrial Controls

RF Power Amps

Diagnostic Monitoring

Features

♦ SFF-8472 Compatible

♦ Five Monitored Channels (Temperature, V

MON1, MON2, MON3)

♦ Three External Analog Inputs (MON1, MON2, MON3)

That Support Internal and External Calibration

♦ Scalable Dynamic Range for External Analog Inputs

♦ Internal Direct-to-Digital Temperature Sensor

♦ Alarm and Warning Flags for All Monitored

Channels

♦ Two 50kΩ or Two 20kΩ, Linear, 256-Position,

Nonvolatile Temperature-Controlled Variable

Resistors

♦ Resistor Settings Changeable Every 2°C

♦ Access to Monitoring and ID Information

Configurable with Separate Device Addresses

♦ 2-Wire Serial Interface

♦ Two Buffers with TTL/CMOS-Compatible Inputs and

Open-Drain Outputs

♦ Operates from a 3.3V or 5V Supply

♦ Operating Temperature Range of -40°C to +95°C

Ordering Information

Rev 4; 2/06

EVALUATION KIT

AVAILABLE

PART

RESISTANCE

PIN-PACKAGE

DS1859B-020 20kΩ 16 CSBGA

DS1859B-020+ 20kΩ 16 CSBGA

DS1859B-050 50kΩ 16 CSBGA

DS1859B-050+ 50kΩ 16 CSBGA

TOP VIEW

CSBGA (4mm x 4mm)

1.0mm PITCH

TSSOP

324

MON3

OUT1IN2

MON1

L0GND

WPEN

H0SDA

OUT2

SCLIN1

MON2

DS1859

SDA

SCL

OUT1

IN1

OUT2

IN2

WPEN

GND

MON3

MON2

MON1

Pin Configurations

DS1859

SDA

0.1µF

SCL

OUT1

IN1

OUT2

IN2

WPEN

GND

MON3

MON2

MON1

GROUND TO

DISABLE WRITE

PROTECT

Rx POWER*

DIAGNOSTIC

INPUTS

TO LASER

MODULATION

CONTROL

TO LASER BIAS

CONTROL

DECOUPLING

CAP

Tx POWER*

Tx BIAS*

*SATISFIES SFF-8472 COMPATIBILITY

= 3.3V

4.7kΩ4.7kΩ

Tx-FAULT

LOS

2-WIRE

INTERFACE

Typical Operating Circuit

+Denotes lead-free package.

Ordering Information continued at end of data sheet.

Summary of content (28 pages)

PAGE 1
Rev 4; 2/06 KIT ATION EVALU E L B A AVAIL Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors The DS1859 dual, temperature-controlled, nonvolatile (NV) variable resistors with three monitors consists of two 50kΩ or two 20kΩ, 256-position, linear, variable resistors; three analog monitor inputs (MON1, MON2, MON3); and a direct-to-digital temperature sensor.
PAGE 2
DS1859 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors ABSOLUTE MAXIMUM RATINGS Voltage Range on VCC Relative to Ground ...........-0.5V to +6.0V Voltage Range on Inputs Relative to Ground* ................................................-0.5V to VCC + 0.5V Voltage Range on Resistor Inputs Relative to Ground* ................................................-0.5V to VCC + 0.5V Current into Resistors............................................................
PAGE 3
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859 ANALOG RESISTOR CHARACTERISTICS (VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS kΩ Position 00h Resistance (50kΩ) TA = +25°C 0.65 1.0 1.35 Position FFh Resistance (50kΩ) TA = +25°C 40 50 60 kΩ Position 00h Resistance (20kΩ) TA = +25°C 0.20 0.40 0.
PAGE 4
DS1859 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors AC ELECTRICAL CHARACTERISTICS (VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted. See Figure 6.
PAGE 5
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors Typical Operating Characteristics (VCC = 5.0V, TA = +25°C, for both 50kΩ and 20kΩ versions, unless otherwise noted.) SDA = SCL = VCC 560 550 500 450 -20 0 20 40 60 80 3.5 4.0 4.5 5.0 TEMPERATURE (°C) VOLTAGE (V) RESISTANCE vs. SETTING ACTIVE SUPPLY CURRENT vs. SCL FREQUENCY 15 10 5 0 50 100 150 200 250 SETTING (DEC) 760 RESISTOR 0 INL (LSB) 1.0 SDA = VCC 720 0.8 0.
PAGE 6
Typical Operating Characteristics (continued) (VCC = 5.0V, TA = +25°C, for both 50kΩ and 20kΩ versions, unless otherwise noted.) RESISTOR 1 INL (LSB) 0.8 0.6 0.4 0.2 0 -0.2 -0.4 0.8 0.6 RESISTOR 1 DNL (LSB) RESISTOR 1 INL (LSB) 0.4 0.2 0 -0.2 -0.4 0.2 0 -0.2 -0.4 -0.6 -0.6 -0.6 -0.8 -0.8 -0.8 -1.0 -1.0 0 -1.0 0 25 50 75 100 125 150 175 200 225 250 25 50 75 100 125 150 175 200 225 250 RESISTANCE vs.
PAGE 7
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors POSITION FFh RESISTANCE vs. TEMPERATURE 0.37 50kΩ VERSION 0.35 0.34 20kΩ VERSION 19.80 RESISTANCE (kΩ) RESISTANCE (kΩ) 51.80 0.36 20.00 DS1859 toc14 20kΩ VERSION 51.60 51.40 51.20 0.33 35 50 65 80 95 19.
PAGE 8
DS1859 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors Pin Description PIN BALL NAME 1 B2 SDA 2-Wire Serial Data I/O Pin. Transfers serial data to and from the device. FUNCTION 2 A2 SCL 2-Wire Serial Clock Input. Clocks data into and out of the device.
PAGE 9
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors PROT MAIN AD PROT MAIN MD DS1859 PROT AUX MD AD (AUXILIARY DEVICE ENABLE A0h) TABLE SELECT DEVICE ADDRESS MD (MAIN DEVICE ENABLE) DEVICE ADDRESS EEPROM 128 x 8 BIT 00h-7Fh ADDRESS R/W ADDRESS ADEN ADFIX SDA EEPROM 72 x 8 BIT 80h-C7h ADDRESS TABLE 02 RESISTOR 0 LOOK-UP TABLE R/W STANDARDS TABLE SELECT EEPROM 72 x 8 BIT 80h-C7h TABLE 03 RESISTOR 1 LOOK-UP TABLE R/W DATA BUS SCL TEMP INDEX TEMP INDEX REGISTER
PAGE 10
DS1859 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors Table 1. Scales for Monitor Channels at Factory Setting Table 3. Look-up Table Address for Corresponding Temperature Values SIGNAL +FS SIGNAL +FS (hex) -FS SIGNAL -FS (hex) Temperature 127.984°C 7FFC -128°C 8000 VCC 6.5528V FFF8 0V 0000 MON1 2.4997V FFF8 0V 0000 MON2 2.4997V FFF8 0V 0000 MON3 2.4997V FFF8 0V 0000 TEMPERATURE (°C) Table 2.
PAGE 11
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors ADEN (ADDRESS ENABLE) NO. OF SEPARATE DEVICE ADDRESSES ADDITIONAL INFORMATION 0 2 See Figure 2 1 1 (Main Device only) See Figure 3 Table 5.
PAGE 12
DS1859 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors MAIN DEVICE ENABLE 0 DEC MAIN DEVICE 0 EN 5Fh 60h EN 7Fh 95 96 TABLE SELECT DECODER TABLE 00 80h 127 128 TABLE 01 TABLE 02 TABLE 03 EN EN EN 80h 80h 80h MON LOOK-UP TABLE CONTROL R1 LOOK-UP R0 LOOK-UP TABLE TABLE SEL 8Fh SEL C7h AUXILIARY DEVICE EN 143 F0h F0h RESERVED 199 SEL C7h FFh RESERVED FFh FFh 255 MEMORY PARTITION WITH ADEN BIT = 1 Figure 3.
PAGE 13
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors Bytes designated as "Reserved" have been set aside for added functionality in future revisions of this device. A description of the registers is below. The registers are read only (R) or read/write (R/W). The R/W registers are writable only if write protect has not been asserted (see the Memory Description section).
PAGE 14
DS1859 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors Main Device (continued) MEMORY LOCATION (hex) EEPROM/ SRAM R/W DEFAULT SETTING (hex) NAME OF LOCATION 12 to 13 EEPROM R/W 00 MON1limlo (MSB to LSB) Contains lower limit settings for MON1. If the limit is violated, an alarm flag in Main Device byte 70h is set. 14 to 15 EEPROM R/W 00 MON1wrnhi (MSB to LSB) Contains upper limit settings for MON1.
PAGE 15
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859 Main Device (continued) MEMORY LOCATION (hex) EEPROM/ SRAM R/W DEFAULT SETTING (hex) NAME OF LOCATION 68 to 69 SRAM R — Measured MON3 (MSB to LSB) FUNCTION Digitized measured value for MON3. See Table 1. 6A to 6D SRAM — — Reserved — 6E SRAM — — Logic states — Bit 7 — R X HIZSTA Resistor status bit. A high indicates that both resistors are in high-impedance mode.
PAGE 16
DS1859 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors Main Device (continued) MEMORY LOCATION (hex) 4 16 EEPROM/ SRAM — R/W R/W DEFAULT SETTING (hex) 0 NAME OF LOCATION FUNCTION MON2U This bit goes high after a MON2 update has occurred for the corresponding measurement in bytes 66h to 67h. This bit can be written to a 0 by the user and monitored to verify that a conversion has occurred.
PAGE 17
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859 Main Device (continued) MEMORY LOCATION (hex) EEPROM/ SRAM R/W DEFAULT SETTING (hex) NAME OF LOCATION FUNCTION 3 — — — X — 2 — — — X — 1 — — — X — 0 — MINT A mask of all flags located in Table 01 byte 88h determines the value of MINT. MINT is maskable to 0 if no interrupt is desired by setting Table 01 byte 88h to 0.
PAGE 18
DS1859 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors Main Device (continued) MEMORY LOCATION (hex) EEPROM/ SRAM R/W DEFAULT SETTING (hex) NAME OF LOCATION 75 SRAM R — Warning Flags — Bit 7 — — 0 MON3hi This warning flag goes high when the upper limit of the MON3 setting is violated. 6 — — 0 MON3lo This warning flag goes high when the lower limit of the MON3 setting is violated.
PAGE 19
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859 Table 01h MEMORY EEPROM/ LOCATION SRAM (hex) R/W DEFAULT SETTING (hex) NAME OF LOCATION FUNCTION 80 SRAM R/W Mode — Bit 7 — — 0 X — 6 — — 0 X — 5 — — 0 X — 4 — — 0 X — 3 — — 0 X — 2 — — 0 X — 1 — — 1 TEN If TEN = 0, the resistors can be controlled manually.
PAGE 20
DS1859 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors Table 01h (continued) MEMORY EEPROM/ LOCATION SRAM (hex) 20 R/W DEFAULT SETTING (hex) NAME OF LOCATION FUNCTION 5 — — 0 ADEN Controls if the device responds to one or two device addresses (see the Memory Description section and Table 5). 4 — — 0 ADFIX Controls the means by which Main and Auxiliary Device addresses are set (see the Memory Description section and Table 5).
PAGE 21
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859 Table 01h (continued) MEMORY EEPROM/ LOCATION SRAM (hex) R/W DEFAULT SETTING (hex) NAME OF LOCATION 0 Reserved 90 to 91 EEPROM — 92 to 93 EEPROM R/W Gain Cal VCC 94 to 95 EEPROM R/W Gain Cal Mon1 96 to 97 EEPROM R/W Gain Cal Mon2 98 to 99 EEPROM R/W Gain Cal Mon3 9A to 9F EEPROM — A0 to A1 EEPROM — A2 to A3 EEPROM R/W Offset Cal VCC A4 to A5 EEPROM R/W Offset Cal Mon1 A6 to A7 EEPROM R
PAGE 22
Programming the Look-up Table (LUT) The following equation can be used to determine which resistor position setting, 00h to FFh, should be written in the LUT to achieve a given resistance at a specific temperature. 2 R − u • 1 + v • (C − 25) + w • (C − 25)    −α pos(α, R, C) = 2  (x) • 1 + y • (C − 25) + z • (C − 25)  α = 3.852357 for the 20kΩ resistor α = 4.
PAGE 23
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors CNT1 = 0.5 / 50E-6; /* 10000 */ CNT2 = 0.90 x FS / 50E-6; /* 58981.5 */ /* Thus the null input 0.5V and the 90% of FS input is 2.949075V. */ Set the trim-offset-register to zero; Set Right-Shift register to zero (typically zero. See Right-Shifting section); gain_result = 0h; Clamp = FFF8h/2^(Right_Shift_Register); For n = 15 down to 0 begin gain_result = gain_result + 2^n; Force the 90% FS input (2.
PAGE 24
DS1859 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors Main Device address. The control of write privileges through the Auxiliary Device address depends on the value of APEN. Care should be taken with the setting of MPEN, once set to a 1, assuming WPEN is high. Access through the Main Device is thereafter denied unless WPEN is taken to a low level. By this means, inadvertent end-user write access can be denied.
PAGE 25
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors Acknowledge Polling: Once the internally timed write has started and the DS1859 inputs are disabled, acknowledge polling can be initiated. The process involves transmitting a START condition followed by the device address. The R/W bit signifies the type of operation that is desired. The read or write sequence will only be allowed to proceed if the internal write cycle has completed and the DS1859 responds with a zero.
PAGE 26
DS1859 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors SDA tBUF tHD:STA tLOW tR tSP tF SCL tHD:STA STOP tSU:STA tHIGH tSU:DAT START REPEATED START tSU:STO tHD:DAT Figure 6. 2-Wire AC Characteristics operation, incremented by one. This data is maintained as long as VCC is valid. If the most recent address was the last byte in memory, then the register resets to the first address.
PAGE 27
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. Start data transfer: A change in the state of the data line from high to low while the clock is high defines a START condition. Stop data transfer: A change in the state of the data line from low to high while the clock line is high defines the STOP condition.
PAGE 28
DS1859 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors Ordering Information (continued) PART RESISTANCE PIN-PACKAGE DS1859B-050+T&R 50kΩ 16 CSBGA DS1859B-050/T&R 50kΩ 16 CSBGA DS1859E-020 20kΩ 16 TSSOP DS1859E-020+ 20kΩ 16 TSSOP DS1859E-020/T&R 20kΩ 16 TSSOP DS1859E-020+T&R 20kΩ 16 TSSOP DS1859E-050 50kΩ 16 TSSOP DS1859E-050+ 50kΩ 16 TSSOP DS1859E-050+T&R 50kΩ 16 TSSOP DS1859E-050/T&R 50kΩ 16 TSSOP Chip Information TRANSISTOR COUNT: 47,191 SUBSTRA