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SPECIAL FEATURES

 16384 bits Electrically Programmable Read Only

Memory (EPROM) communicates with the

economy of one signal plus ground

 EPROM partitioned into 64 256-bit pages for

randomly accessing packetized data records

 Each memory page can be permanently write

protected to prevent tampering

 Device is an “add only” memory where additional

data can be programmed into EPROM without

disturbing existing data

 Architecture allows software to patch data by

superseding an old page in favor of a newly

programmed page

 Reduces control, address, data, power, and

programming signals to a single data pin

 8-bit family code specifies DS1985

communications requirements to reader

 Reads over a wide voltage range of 2.8V to 6.0V

from -40°C to +85°C; programs at 11.5V to 12.0V

from -40°C to +85°C

F3 MicroCan

F5 MicroCan

COMMON iButton FEATURES

 Unique, factory-lasered and tested 64-bit

registration number (8-bit family code +

48-bit serial number + 8-bit CRC tester)

assures absolute traceability because no two

parts are alike

 Multidrop controller for MicroLAN

 Digital identification and information by

momentary contact

 Chip-based data carrier compactly stores

information

 Data can be accessed while affixed to object

 Economically communicates to bus master

with a single digital signal at 16.3kbps

 Standard 16mm diameter and 1-Wire

protocol ensure compatibility with iButton

family

 Button shape is self-aligning with cup-shaped

probes

 Durable stainless steel case engraved with

registration number withstands harsh

environments

 Easily affixed with self-stick adhesive

backing, latched by its flange, or locked with

a ring pressed onto its rim

 Presence detector acknowledges when reader

first applies voltage

ORDERING INFORMATION

PART PIN-PACKAGE

DS1985-F3+ F3 MicroCan

DS1985-F5+ F5 MicroCan

+Denotes a lead(Pb)-free/RoHS-compliant package.

EXAMPLES OF ACCESSORIES

DS9096P Self-Stick Adhesive Pad

DS9101 Multi-Purpose Clip

DS9093RA Mounting Lock Ring

DS9093F Snap-In Fob

DS9092 iButton Probe

iButton and 1-Wire are registered trademarks of Maxim Integrated Products, Inc.

19-4892; Rev 8/09

DS1985

16Kb Add-Only i

Button

Summary of content (26 pages)

PAGE 1
9-4892; Rev 8/09 DS1985 16Kb Add-Only iButton SPECIAL FEATURES COMMON iButton FEATURES          16384 bits Electrically Programmable Read Only Memory (EPROM) communicates with the economy of one signal plus ground EPROM partitioned into 64 256-bit pages for randomly accessing packetized data records Each memory page can be permanently write protected to prevent tampering Device is an “add only” memory where additional data can be programmed into EPROM without disturbing existing data Archit
PAGE 2
DS1985 iButton DESCRIPTION The DS1985 16Kb Add-Only iButton is a rugged read/write data carrier that identifies and stores relevant information about the product or person to which it is attached. This information can be accessed with minimal hardware, for example a single port pin of a microcontroller. The DS1985 consists of a factorylasered registration number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (0BH) plus 16Kb of EPROM that is user-programmable.
PAGE 3
DS1985 DS1985 BLOCK DIAGRAM Figure 1 64-BIT LASERED ROM Each DS1985 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 3.) The 64-bit ROM and ROM Function Control section allow the DS1985 to operate as a 1-Wire device and follow the 1-Wire protocol detailed in the section “1-Wire Bus System.
PAGE 4
DS1985 HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 64-BIT LASERED ROM Figure 3 8-Bit CRC Code MSB 48- Bit Serial Number LSB MSB 8-Bit Family Code (0BH) LSB 4 of 26 MSB LSB
PAGE 5
DS1985 16384 BITS EPROM The memory map in Figure 4 shows the 16384 bits EPROM section of the DS1985 which is configured as 64 pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when programming the memory. Data is first written to the scratchpad and then verified by reading a 16-bit CRC from the DS1985 that confirms proper receipt of the data and address.
PAGE 6
DS1985 If a Page Address Redirection Byte has a FFH value, the data in the main memory that corresponds to that page is valid. If a Page Address Redirection Byte has some other hex value, the data in the page corresponding to that redirection byte is invalid, and the valid data can now be found at the one’s complement of the page address indicated by the hex value stored in the associated Page Address Redirection Byte.
PAGE 7
DS1985 The Status Memory address range of the DS1985 extends from 000 to 13FH. The memory locations 008H to 01FH, 028H to 03FH, 048H to 0FFH and 140H to 7FFH are physically not implemented. Reading these locations will usually result in FFH bytes. Attempts to write to these locations will be ignored. If the bus master sends a starting address higher than 7FFH, the five most significant address bits are set to 0s by the internal circuitry of the chip.
PAGE 8
DS1985 READ STATUS [AAH] The Read Status command is used to read data from the EPROM Status data field. The bus master follows the command byte with a 2-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. With every subsequent read data time slot the bus master receives data from the DS1985 starting at the supplied address and continuing until the end of an 8-byte page of the EPROM Status data field is reached.
PAGE 9
DS1985 MEMORY FUNCTION FLOW CHART Figure 5 9 of 26
PAGE 10
DS1985 MEMORY FUNCTION FLOW CHART (cont’d) Figure 5 10 of 26
PAGE 11
DS1985 MEMORY FUNCTION FLOW CHART (cont’d) Figure 5 11 of 26
PAGE 12
DS1985 EXTENDED READ MEMORY [A5H] The Extended Read Memory command supports page redirection when reading data from the 16384-bit EPROM data field. One major difference between the Extended Read Memory and the basic Read Memory command is that the bus master receives the Redirection Byte first before investing time in reading data from the addressed memory location.
PAGE 13
DS1985 WRITE MEMORY [0FH] The Write Memory command is used to program the 16384–bit EPROM data field. The bus master will follow the command byte with a two byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte of data (D7:D0). A 16-bit CRC of the command byte, address bytes, and data byte is computed by the DS1985 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received. The highest starting address within the DS1985 is 07FFH.
PAGE 14
DS1985 For both of these cases, the decision to continue (to apply a Program Pulse to the DS1985) is made entirely by the bus master, since the DS1985 will not be able to determine if the 16-bit CRC calculated by the bus master agrees with the 16-bit CRC calculated by the DS1985. If an incorrect CRC is ignored and a Program Pulse is applied by the bus master, incorrect programming could occur within the DS1985.
PAGE 15
DS1985 As the DS1985 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator that has been preloaded with the current address, and the result is a 16-bit CRC of the new data byte and the new address. After supplying the data byte, the bus master will read this 16-bit CRC from the DS1985 with 16 read time slots to confirm that the address incremented properly and the data byte was received correctly.
PAGE 16
DS1985 The bus master requires a pullup resistor at the master end of the bus, with the bus master circuit equivalent to the one shown in Figures 7a and 7b. The value of the pullup resistor should be approximately 5 k for short line lengths. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of 16.3kbps.
PAGE 17
DS1985 DS1985 EQUIVALENT CIRCUIT Figure 6 BUS MASTER CIRCUIT Figure 7 VP0300L OR VP0106N3 OR BSS110 TO DATA CONNECTION OF DS2505 CAPACITOR ADDED TO REDUCE COUPLING ON DATA LINE DUE TO PROGRAMMING SIGNAL SWITCHING 17 of 26
PAGE 18
DS1985 ROM FUNCTIONS FLOW CHART Figure 8 (See Figure 5) 18 of 26
PAGE 19
DS1985 Match ROM [55H] The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1985 on a multidrop bus. Only the DS1985 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a Reset Pulse. This command can be used with a single or multiple devices on the bus.
PAGE 20
DS1985 (Figure 11) should be applied for 480 s, after which the bus master returns the data line to an idle high state controlled by the pullup resistor. Note that due to the high voltage programming requirements for any 1-Wire EPROM device, it is not possible to multidrop non-EPROM based 1-Wire devices with the DS1985 during programming. An internal diode within the non-EPROM based 1-Wire devices will attempt to clamp the data line at approximately 8 volts and could potentially damage these devices.
PAGE 21
DS1985 READ/WRITE TIMING DIAGRAM (cont’d) Figure 10 Write-0 Time Slot 60 s  tLOW0 < tSLOT < 120 s 1 s  tREC <  Read-Data Time Slot RESISTOR MASTER DS1985 60 s  tSLOT < 120 s 1 s  tLOWR < 15 s 0  tRELEASE < 45 s 1 s  tREC <  tRDV = 15 s tSU < 1 s 21 of 26
PAGE 22
DS1985 PROGRAM PULSE TIMING DIAGRAM Figure 11 LINE TYPE LEGEND: Bus master active high (12V @ 10 mA) Resistor pullup CRC GENERATION With the DS1985 there are two different types of CRCs (Cyclic Redundancy Checks). One CRC is an 8bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS1985 to determine if the ROM data has been received error-free by the bus master.
PAGE 23
DS1985 When reading the data memory of the DS1985 with the Extended Read Memory command, there are two situations where a 16-bit CRC is transmitted. One 16-bit CRC follows each Redirection Byte, another 16bit CRC is received after the last byte of a memory data page is read. The CRC at the end of the memory page is always the result of clearing the CRC generator and shifting in the data bytes beginning at the first addressed memory location of the EPROM data page until the last byte of this page.
PAGE 24
DS1985 ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature  -0.5V to +12.0V -40°C to +85°C -55°C to +125°C This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
PAGE 25
DS1985 NOTES: 1. All voltages are referenced to ground. 2. VPUP = external pullup voltage. If VPUP is lower than 3.0V the first byte read (any read command) may not reproduce the correct memory contents. Therefore, under low voltage conditions, it is recommended to set either the most significant bit or all five most significant bits of TA2 to 1. Internal circuitry of the chip will force these five bits back to 0 before they are shifted in the address counter and CRC generator. 3. Input load is to ground.
PAGE 26
DS1985 REVISION HISTORY REVISION DATE 071508 8/09 DESCRIPTION Updated the F3 MicroCan and F5 MicroCan face brands with the latest per PCN H020201. Added the + sign to the PART numbers in the Ordering Information table, indicating lead(Pb)-free/RoHS-compliant packages. Removed the UL#913 bullet from the Common iButton Features section. PAGES CHANGED 1 1 1 26 of 26 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product.