Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsIntegrated Circuits (ICs)TO 92 3 1 kBit 256 x 4

General Description

The DS2431 is a 1024-bit, 1-Wire

EEPROM chip orga-

nized as four memory pages of 256 bits each. Data is

written to an 8-byte scratchpad, verified, and then copied

to the EEPROM memory. As a special feature, the four

memory pages can individually be write protected or

put in EPROM-emulation mode, where bits can only be

changed from a 1 to a 0 state. The DS2431 communi-

cates over the single-conductor 1-Wire bus. The com-

munication follows the standard 1-Wire protocol. Each

device has its own unalterable and unique 64-bit ROM

registration number that is factory lasered into the chip.

The registration number is used to address the device in

a multidrop, 1-Wire net environment.

Applications

● Accessory/PCB Identication

● Medical Sensor Calibration Data Storage

● Analog Sensor Calibration Including IEEE P1451.4

Smart Sensors

● Ink and Toner Print Cartridge Identication

● After-Market Management of Consumables

Features

● 1024 Bits of EEPROM Memory Partitioned Into Four

Pages of 256 Bits

● Individual Memory Pages Can Be Permanently Write

Protected or Put in EPROM-Emulation Mode (“Write

to 0”)

● Switchpoint Hysteresis and Filtering to Optimize

Performance in the Presence of Noise

● IEC 1000-4-2 Level 4 ESD Protection (±8kV Contact,

±15kV Air, Typical)

● Reads and Writes Over a Wide Voltage Range from

2.8V to 5.25V from -40°C to +85°C

● Communicates to Host with a Single Digital Signal at

15.4kbps or 125kbps Using 1-Wire Protocol

Pin Configurations appear at end of data sheet.

1-Wire is a registered trademark of Maxim Integrated Products,

Inc.

19-4675; Rev 14; 11/14

Note: The leads of TO-92 packages on tape and reel are

formed to approximately 100-mil (2.54mm) spacing. For details,

refer to the package outline drawing.

+Denotes a lead(Pb)-free/RoHS-compliant package.

T&R = Tape and reel.

*EP = Exposed pad.

PART TEMP RANGE PIN-PACKAGE

DS2431+ -40°C to +85°C 3 TO-92

DS2431+T&R -40°C to +85°C 3 TO-92

DS2431P+ -40°C to +85°C 6 TSOC

DS2431P+T&R -40°C to +85°C 6 TSOC

DS2431G+U -40°C to +85°C 2 SFN (6mm x 6mm)

DS2431G+T&R -40°C to +85°C

2 SFN (6mm x 6mm)

(2.5k pcs)

DS2431GA+U -40°C to +85°C 2 SFN (3.5mm x 6.5mm)

DS2431GA+T&R -40°C to +85°C

2 SFN (3.5mm x 6.5mm)

(2.5k pcs)

DS2431Q+T&R -40°C to +85°C 6 TDFN-EP* (2.5k pcs)

DS2431X-S+ -40°C to +85°C 3x3 UCSPR (2.5k pcs)

DS2431X+ -40°C to +85°C 3x3 UCSPR (10k pcs)

PUP

µC

GND

DS2431

DS2431 1024-Bit, 1-Wire EEPROM

Typical Operating Circuit

Ordering Information

Summary of content (27 pages)

PAGE 1
DS2431 1024-Bit, 1-Wire EEPROM General Description The DS2431 is a 1024-bit, 1-Wire® EEPROM chip organized as four memory pages of 256 bits each. Data is written to an 8-byte scratchpad, verified, and then copied to the EEPROM memory. As a special feature, the four memory pages can individually be write protected or put in EPROM-emulation mode, where bits can only be changed from a 1 to a 0 state. The DS2431 communicates over the single-conductor 1-Wire bus.
PAGE 2
DS2431 1024-Bit, 1-Wire EEPROM Absolute Maximum Ratings IO Voltage Range to GND........................................-0.5V to +6V IO Sink Current....................................................................20mA Operating Temperature Range.............................-40°C to +85°C Junction Temperature........................................................+150°C Storage Temperature Range..............................-55°C to +125°C Lead Temperature (excluding UCSP, soldering, 10s).......
PAGE 3
DS2431 1024-Bit, 1-Wire EEPROM Electrical Characteristics (continued) (TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN: 1-Wire WRITE Write-Zero Low Time (Notes 2, 16, 17) Write-One Low Time (Notes 2, 17) tW0L tW1L Standard speed 60 120 Overdrive speed, VPUP > 4.5V 5 15.5 Overdrive speed 6 15.
PAGE 4
DS2431 1024-Bit, 1-Wire EEPROM Note 19: Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO during the programming interval should be such that the voltage at IO is greater than or equal to VPUPMIN. If VPUP in the system is close to VPUPMIN, a lowimpedance bypass of RPUP, which can be activated during programming, may need to be added.
PAGE 5
DS2431 1024-Bit, 1-Wire EEPROM Pin Description PIN NAME TSOC TO-92 TDFN-EP SFN UCSPR 3, 4, 5, 6 3 1, 4, 5, 6 — A2, A3, C2, C3 N.C. 2 2 2 1 C1 IO 1 1 3 2 A1 GND — — — — — EP FUNCTION Not Connected 1-Wire Bus Interface. Open-drain signal that requires an external pullup resistor. Ground Reference Exposed Pad (TDFN only). Solder evenly to the board’s ground plane for proper operation. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information.
PAGE 6
DS2431 1024-Bit, 1-Wire EEPROM AVAILABLE COMMANDS: DATA FIELD AFFECTED: DS2431 COMMAND LEVEL: 1-Wire ROM FUNCTION COMMANDS (SEE FIGURE 9) DS2431-SPECIFIC MEMORY FUNCTION COMMANDS (SEE FIGURE 7) READ ROM MATCH ROM SEARCH ROM SKIP ROM RESUME OVERDRIVE-SKIP ROM OVERDRIVE-MATCH ROM 64-BIT REG. #, RC-FLAG 64-BIT REG. #, RC-FLAG 64-BIT REG. #, RC-FLAG RC-FLAG RC-FLAG RC-FLAG, OD-FLAG 64-BIT REG.
PAGE 7
DS2431 1024-Bit, 1-Wire EEPROM POLYNOMIAL = X8 + X5 + X4 + 1 1ST STAGE X0 2ND STAGE X1 3RD STAGE X2 4TH STAGE X3 5TH STAGE 6TH STAGE X4 X5 7TH STAGE X6 8TH STAGE X7 X8 INPUT DATA Figure 4. 1-Wire CRC Generator Memory Access Data memory and registers are located in a linear address space, as shown in Figure 5. The data memory and the registers have unrestricted read access. The DS2431 EEPROM array consists of 18 rows of 8 bytes each.
PAGE 8
DS2431 1024-Bit, 1-Wire EEPROM Contact the factory to set up and register a custom manufacturer ID. The last row is reserved for future use. It is undefined in terms of R/W functionality and should not be used. The copy-protection byte is used for a higher level of security and should only be used after all other protection control bytes, user bytes, and write-protected pages are set to their final value.
PAGE 9
DS2431 Writing with Verification To write data to the DS2431, the scratchpad must be used as intermediate storage. First, the master issues the Write Scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. Note that Copy Scratchpad commands must be performed on 8-byte boundaries, i.e., the three LSBs of the target address (T2, T1, T0) must be equal to 000b. If T[2:0] are sent with nonzero values, the copy function is blocked.
PAGE 10
DS2431 1024-Bit, 1-Wire EEPROM FROM ROM FUNCTIONS FLOWCHART (FIGURE 9) BUS MASTER Tx MEMORY FUNCTION COMMAND 0Fh WRITE SCRATCHPAD? AAh READ SCRATCHPAD? N Y BUS MASTER Rx TA1 (T[7:0]), TA2 (T[15:8]), AND E/S BYTE DS2431 SETS PF = 1 CLEARS AA = 0 SETS E[2:0] = T[2:0] DS2431 SETS SCRATCHPAD BYTE COUNTER = T[2:0] MASTER Tx DATA BYTE TO SCRATCHPAD MASTER Tx RESET? APPLIES ONLY IF THE MEMORY AREA IS NOT PROTECTED.
PAGE 11
DS2431 FROM FIGURE 7a 1024-Bit, 1-Wire EEPROM 55h COPY SCRATCHPAD? Y Y N BUS MASTER Tx TA1 (T[7:0]), TA2 (T[15:8]) ADDRESS < 90h? Y T[15:0] < 0090h? N Y APPLICABLE TO ALL R/W MEMORY LOCATIONS. BUS MASTER Tx TA1 (T[7:0]), TA2 (T[15:8]) AND E/S BYTE AUTH.
PAGE 12
DS2431 Read Scratchpad [AAh] The Read Scratchpad command allows verifying the target address and the integrity of the scratchpad data. After issuing the command code, the master begins reading. The first two bytes are the target address. The next byte is the ending offset/data status byte (E/S) followed by the scratchpad data, which may be different from what the master originally sent.
PAGE 13
DS2431 1024-Bit, 1-Wire EEPROM VPUP BUS MASTER DS2431 1-Wire PORT RPUP DATA Rx Tx OPEN-DRAIN PORT PIN Rx = RECEIVE Tx = TRANSMIT Rx IL Tx 100 MOSFET Figure 8. Hardware Configuration Initialization All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s).
PAGE 14
DS2431 1024-Bit, 1-Wire EEPROM BUS MASTER Tx RESET PULSE FROM FIGURE 9b FROM MEMORY FUNCTIONS FLOWCHART (FIGURE 7) OD RESET PULSE? N OD = 0 Y BUS MASTER Tx ROM FUNCTION COMMAND 33h READ ROM COMMAND? DS2431 Tx PRESENCE PULSE N 55h MATCH ROM COMMAND? F0h SEARCH ROM COMMAND? N N CCh SKIP ROM COMMAND? Y Y Y Y RC = 0 RC = 0 RC = 0 RC = 0 DS2431 Tx FAMILY CODE (1 BYTE) MASTER Tx BIT 0 DS2431 Tx BIT 0 MASTER Tx BIT 0 N N BIT 0 MATCH? Y Y DS2431 Tx BIT 1 MASTER Tx BIT 1 DS2431 Tx BIT
PAGE 15
DS2431 1024-Bit, 1-Wire EEPROM TO FIGURE 9a FROM FIGURE 9a A5h RESUME COMMAND? 3Ch OVERDRIVESKIP ROM? N Y Y RC = 1? N N Y RC = 0; OD = 1 N 69h OVERDRIVEMATCH ROM? RC = 0; OD = 1 Y MASTER Tx BIT 0 MASTER Tx RESET? N Y BIT 0 MATCH? N OD = 0 Y MASTER Tx BIT 1 MASTER Tx RESET? N Y BIT 1 MATCH? N OD = 0 Y MASTER Tx BIT 63 BIT 63 MATCH? N OD = 0 Y FROM FIGURE 9a RC = 1 TO FIGURE 9a Figure 9b. ROM Functions Flowchart (continued) www.maximintegrated.
PAGE 16
DS2431 Resume [A5h] To maximize the data throughput in a multidrop environment, the Resume command is available. This command checks the status of the RC bit and, if it is set, directly transfers control to the memory function commands, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM, or Overdrive-Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the Resume command.
PAGE 17
DS2431 1024-Bit, 1-Wire EEPROM MASTER Tx "RESET PULSE" MASTER Rx "PRESENCE PULSE" ε tMSP VPUP VIHMASTER VTH VTL VILMAX 0V tRSTL tPDH tF tPDL tREC tRSTH RESISTOR MASTER DS2431 Figure 10. Initialization Procedure: Reset and Presence Pulse Read/Write Time Slots Data communication with the DS2431 takes place in time slots that carry a single bit each. Write time slots transport data from bus master to slave. Read time slots transfer data from slave to master.
PAGE 18
DS2431 1024-Bit, 1-Wire EEPROM WRITE-ONE TIME SLOT tW1L VPUP VIHMASTER VTH VTL VILMAX 0V ε tF tSLOT RESISTOR MASTER WRITE-ZERO TIME SLOT tW0L VPUP VIHMASTER VTH VTL VILMAX 0V ε tF tSLOT RESISTOR READ-DATA TIME SLOT tRL VPUP VIHMASTER VTH VTL VILMAX 0V tREC MASTER tMSR MASTER SAMPLING WINDOW δ tF tSLOT RESISTOR MASTER tREC DS2431 Figure 11. Read/Write Timing Diagrams www.maximintegrated.
PAGE 19
DS2431 1024-Bit, 1-Wire EEPROM Improved Network Behavior (Switchpoint Hysteresis) In a 1-Wire environment, line termination is possible only during transients controlled by the bus master (1-Wire driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and topology of the network, reflections from end points and branch points can add up or cancel each other to some extent.
PAGE 20
DS2431 1024-Bit, 1-Wire EEPROM POLYNOMIAL = X16 + X15 + X2 + 1 1ST STAGE 3RD STAGE 2ND STAGE X0 X2 X1 9TH STAGE X8 4TH STAGE 10TH STAGE X9 11TH STAGE X10 X3 12TH STAGE X11 5TH STAGE 6TH STAGE X4 13TH STAGE X12 X5 14TH STAGE X13 7TH STAGE X6 8TH STAGE X7 15TH STAGE X14 16TH STAGE X15 X16 CRC OUTPUT INPUT DATA Figure 13. CRC-16 Hardware Description and Polynomial and all the data bytes as they were sent by the bus master. The DS2431 transmits this CRC only if E[2:0] = 111b.
PAGE 21
DS2431 1024-Bit, 1-Wire EEPROM Command-Specific 1-Wire Communication Protocol—Color Codes Master to Slave Slave to Master Programming 1-Wire Communication Examples Write Scratchpad (Cannot Fail) RST PD Select WS TA <8–T[2:0] bytes> CRC-16 FF Loop Read Scratchpad (Cannot Fail) RST PD Select RS TA-E/S <8–T[2:0] bytes> CRC-16 FF Loop Copy Scratchpad (Success) RST PD Select CPS TA-E/S Programming AA Loop Copy Scratchpad (Invalid Address or PF = 1 or Copy Protected) RST PD Select CPS T
PAGE 22
DS2431 1024-Bit, 1-Wire EEPROM Memory Function Example Write to the first 8 bytes of memory page 1. Read the entire memory.
PAGE 23
DS2431 1024-Bit, 1-Wire EEPROM Pin Configurations SIDE VIEW FRONT VIEW GND 1 1 IO 2 2 N.C. 3 3 FRONT VIEW (T&R VERSION) TO-92 1 2 3 TOP VIEW TOP VIEW TOP VIEW + 1 IO 2 N.C. 3 6 N.C. DS2431 GND N.C. N.C. A1 A2 A3 DS2431 5 N.C. 4 N.C. C1 IO TSOC C2 C3 N.C. N.C. N.C. 1 IO 2 GND 3 + 2431 ymrrF GND DS2431 *EP UCSPR *EXPOSED PAD BOTTOM VIEW 1 DS2431G 6 N.C. 5 N.C. 4 N.C. TDFN (3mm x 3mm) BOTTOM VIEW 2 GND 2 IO 1 DS2431GA IO GND SFN (6mm x 6mm x 0.
PAGE 24
DS2431 1024-Bit, 1-Wire EEPROM SFN Package Orientation on Tape and Reel USER DIRECTION OF FEED LEADS FACE UP IN ORIENTATION SHOWN ABOVE. SFN (6mm x 6mm x 0.9mm) USER DIRECTION OF FEED LEADS FACE UP IN ORIENTATION SHOWN ABOVE. SFN (3.5mm x 6.5mm x 0.75mm) www.maximintegrated.
PAGE 25
DS2431 1024-Bit, 1-Wire EEPROM Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
PAGE 26
DS2431 1024-Bit, 1-Wire EEPROM Revision History REVISION NUMBER REVISION DATE 0 050704 1 081604 PAGES CHANGED DESCRIPTION Initial release —— Replaced Pin Configuration 1 In the Electrical Characteristics table, changed VTL(MIN) from 0.5V to 0.46V and VTL(MAX) from 4.1V to 4.4V; changed VHY(MIN) from 0.22V to 0.21V 2 In the Copy Scratchpad [55h] section, corrected the copy time from 13ms to 12.
PAGE 27
DS2431 1024-Bit, 1-Wire EEPROM Revision History (continued) REVISION NUMBER REVISION DATE PAGES CHANGED 11 1/12 Updated Note 1 in the Electrical Characteristics section; specified the data memory default status and added a note that the memory must be programmed to FFh for the EPROM mode to function to the Memory Access section 12 2/12 Added the 3.5mm x 6.