LE AVAILAB DS24B33 1-Wire 4Kb EEPROM General Description The DS24B33 is a 4096-bit, 1-Wire® EEPROM organized as 16 memory pages of 256 bits each. Data is written to a 32-byte scratchpad, verified, and then copied to the EEPROM memory. The DS24B33 communicates over a single-conductor 1-Wire bus. The communication follows the standard 1-Wire protocol. Each device has its own unalterable and unique 64-bit registration number that is factory programmed into the chip.
DS24B33 1-Wire 4Kb EEPROM ABSOLUTE MAXIMUM RATINGS IO Voltage Range to GND ........................................-0.5V to +6V IO Sink Current....................................................................20mA Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-55°C to +125°C Lead Temperature (soldering, 10s) .................................
DS24B33 1-Wire 4Kb EEPROM ELECTRICAL CHARACTERISTICS (continued) (TA = -40°C to +85°C.
DS24B33 1-Wire 4Kb EEPROM ELECTRICAL CHARACTERISTICS (continued) (TA = -40°C to +85°C.) (Note 1) Note 19: The tPROG interval begins after the trailing rising edge on IO for the last time slot of the E/S byte for a valid copy scratchpad sequence. The interval ends once the device’s self-timed EEPROM programming cycle is complete and the current drawn by the device has returned from IPROG to IL. Note 20: Write-cycle endurance is degraded as TA increases.
DS24B33 1-Wire 4Kb EEPROM Pin Description PIN SFN TDFN-EP TO-92 SO NAME 2 3 1 4 GND 1 2 2 3 IO — 1, 4, 5, 6 3 1, 2, 5–8 N.C. — — — — EP FUNCTION Ground Reference 1-Wire Bus Interface. Open-drain pin that requires external pullup Not Connected Exposed Pad (TDFN only). Solder evenly to the board’s ground plane for proper operation. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information.
DS24B33 1-Wire 4Kb EEPROM registration number, 32-byte scratchpad, sixteen 32-byte pages of EEPROM, and a CRC-16 generator. Figure 2 shows the hierarchical structure of the 1-Wire protocol. The bus master must first provide one of the seven ROM (network) function commands: Read ROM, Match ROM, Search ROM, Skip ROM, Resume, Overdrive-Skip ROM, or Overdrive-Match ROM.
DS24B33 1-Wire 4Kb EEPROM Memory The shift register bits are initialized to 0. Then, starting with the LSB of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, the serial number is entered. After the last bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of the CRC returns the shift register to all 0s.
DS24B33 1-Wire 4Kb EEPROM Memory Access Address Registers and Transfer Status The DS24B33 employs three address registers: TA1, TA2, and E/S (Figure 6). Registers TA1 and TA2 must be loaded with the target address to which the data is written or from which data is read. Register E/S is a read-only transfer status register used to verify data integrity with write commands. ES bits E[4:0] are loaded with the incoming T[4:0] on a Write Scratchpad command and increment on each subsequent data byte.
DS24B33 1-Wire 4Kb EEPROM Memory Function Commands The Memory Function Flowchart (Figure 7) describes the protocols necessary for accessing the memory of the DS24B33. The target address registers TA1 and TA2 are used for both read and write. The communication between the master and the DS24B33 takes place either at standard speed (default, OD = 0) or at overdrive speed (OD = 1). If not explicitly set into the overdrive mode, the DS24B33 assumes standard speed.
DS24B33 1-Wire 4Kb EEPROM FROM ROM FUNCTIONS FLOWCHART (FIGURE 9) BUS MASTER Tx MEMORY FUNCTION COMMAND 0Fh WRITE SCRATCHPAD? AAh READ SCRATCHPAD? N Y BUS MASTER Rx TA1 (T[7:0]), TA2 (T[15:8]), AND E/S BYTE BUS MASTER Tx EEPROM ARRAY TARGET ADDRESS TA1 (T[7:0]), TA2 (T[15:8]) DS24B33 SETS SCRATCHPAD OFFSET = (T[4:0]) DS24B33 SETS SCRATCHPAD OFFSET = (T[4:0]) BUS MASTER Rx DATA BYTE TO SCRATCHPAD OFFSET MASTER Tx DATA BYTE TO SCRATCHPAD OFFSET DS24B33 INCREMENTS SCRATCHPAD OFFSET MASTER Tx RESET
DS24B33 1-Wire 4Kb EEPROM FROM FIGURE 7a 55h COPY SCRATCHPAD? F0h READ MEMORY? N Y Y BUS MASTER Tx TA1 (T[7:0]), TA2 (T[15:8]) BUS MASTER Rx TA1 (T[7:0]), TA2 (T[15:8]), AND E/S BYTE AUTHORIZATION CODE MATCH? N BUS MASTER Rx "1"s Y N N MASTER Tx RESET? Y N AA = 1 DS24B33 COPIES SCRATCHPAD DATA TO ADDRESS DS24B33 SETS MEMORY ADDRESS = (T[15:0]) * BUS MASTER Rx DATA BYTE FROM MEMORY ADDRESS DS24B33 INCREMENTS ADDRESS COUNTER DS24B33 Tx "0" Y MASTER Tx RESET? MASTER Tx RESET? N N BUS MAS
DS24B33 1-Wire 4Kb EEPROM 1-Wire Bus System Read Memory [F0h] The Read Memory command is the general function to read from the DS24B33. After issuing the command, the master must provide a 2-byte target address, which should be in the range of 0000h to 01FFh. If the target address is higher than 01FFh, the DS24B33 changes the upper 7 address bits to 0. After the address is transmitted, the master reads data starting at the (modified) target address and can continue until address 01FFh.
DS24B33 1-Wire 4Kb EEPROM A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The DS24B33 supports both a standard and overdrive communication speed of 15.4kbps (maximum) and 125kbps (maximum), respectively, over the full pullup voltage range. For pullup voltages of +4.75V and higher, the DS24B33 also supports the legacy communication speed of 16.3kbps and overdrive speed of 142kbps.
DS24B33 1-Wire 4Kb EEPROM Skip ROM [CCh] This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a read command is issued following the Skip ROM command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result).
DS24B33 1-Wire 4Kb EEPROM BUS MASTER Tx RESET PULSE FROM FIGURE 9b FROM MEMORY FUNCTIONS FLOWCHART (FIGURE 7) OD RESET PULSE? N OD = 0 Y BUS MASTER Tx ROM FUNCTION COMMAND 33h READ ROM COMMAND? DS24B33 Tx PRESENCE PULSE N 55h MATCH ROM COMMAND? F0h SEARCH ROM COMMAND? N N CCh SKIP ROM COMMAND? Y Y Y Y RC = 0 RC = 0 RC = 0 RC = 0 DS24B33Tx FAMILY CODE (1 BYTE) MASTER Tx BIT 0 TO FIGURE 9b DS24B33 Tx BIT 0 DS24B33 Tx BIT 0 MASTER Tx BIT 0 BIT 0 MATCH? N N BIT 0 MATCH? Y Y DS24B3
DS24B33 1-Wire 4Kb EEPROM TO FIGURE 9a FROM FIGURE 9a A5h RESUME COMMAND? 3Ch OVERDRIVESKIP ROM? N N Y Y N Y RC = 0; OD = 1 RC = 1? 69h OVERDRIVEMATCH ROM? RC = 0; OD = 1 N Y MASTER Tx RESET? Y MASTER Tx BIT 0 N (SEE NOTE) MASTER Tx RESET? N Y BIT 0 MATCH? N OD = 0 Y MASTER Tx BIT 1 (SEE NOTE) BIT 1 MATCH? N OD = 0 Y MASTER Tx BIT 63 (SEE NOTE) BIT 63 MATCH? N OD = 0 Y FROM FIGURE 9a RC = 1 TO FIGURE 9a NOTE: THE OD FLAG REMAINS AT 1 IF THE DEVICE WAS ALREADY AT OVERDRIV
DS24B33 1-Wire 4Kb EEPROM 1-Wire Signaling After the bus master has released the line it goes into receive mode. Now the 1-Wire bus is pulled to VPUP through the pullup resistor, or in case of a DS2482-x00 or DS2480B driver, by active circuitry. When the threshold VTH is crossed, the DS24B33 waits for tPDH and then transmits a presence pulse by pulling the line low for tPDL. To detect a presence pulse, the master must test the logical state of the 1-Wire line at tMSP.
DS24B33 1-Wire 4Kb EEPROM voltage on the data line should not exceed VILMAX during the entire tW0L or tW1L window. After the VTH thresh- old has been crossed, the DS24B33 needs a recovery time tREC before it is ready for the next time slot.
DS24B33 1-Wire 4Kb EEPROM Slave-to-Master A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below VTL until the read low time tRL is expired. During the tRL window, when responding with a 0, the DS24B33 starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again.
DS24B33 1-Wire 4Kb EEPROM POLYNOMIAL = X16 + X15 + X2 + 1 1ST STAGE 3RD STAGE 2ND STAGE X0 X2 X1 9TH STAGE X8 10TH STAGE X9 11TH STAGE X10 4TH STAGE X3 12TH STAGE X11 5TH STAGE 6TH STAGE X4 13TH STAGE X12 X5 14TH STAGE X13 7TH STAGE X6 8TH STAGE X7 15TH STAGE X14 16TH STAGE X15 X16 CRC OUTPUT INPUT DATA Figure 13.
DS24B33 1-Wire 4Kb EEPROM Command-Specific 1-Wire Communication Protocol—Color Codes Master-to-Slave Slave-to-Master Programming 1-Wire Communication Examples Write Scratchpad, Reaching the End of the Scratchpad RST PD Select WS TA CRC-16 FF loop Read Scratchpad RST PD Select RS TA-E/S FF loop Copy Scratchpad (Success) RST PD Select CPS TA-E/S Programming AA loop Copy Scratchpad (Fail TA-E/S) RST PD Select CPS TA-E/S FF loop Read Memory RST PD Select RM Maxim Integ
DS24B33 1-Wire 4Kb EEPROM SFN Package Orientation on Tape and Reel USER DIRECTION OF FEED LEADS FACE UP IN ORIENTATION SHOWN ABOVE. SFN (6mm × 6mm × 0.9mm) Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
DS24B33 1-Wire 4Kb EEPROM Revision History REVISION NUMBER REVISION DATE 0 2/11 DESCRIPTION PAGES CHANGED Initial release — 1 1 5/11 Implemented text changes to better market the document 2 3/12 Revised the Electrical Characteristics table notes 1, 5, and 15. 3 5/12 Added the SFN (6mm x 6mm x 0.9mm) and TDFN (3mm x 3mm) packages 3 1, 2, 4, 5, 22 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product.
