Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsIntegrated Circuits (ICs)TO 92 3 1 kBit 1 K x 1

FEATURES

 1024 bits Electrically Programmable Read

Only Memory (EPROM) communicates with

the economy of one signal plus ground

 Unique, factory-lasered and tested 64-bit

registration number (8-bit family code + 48-

bit serial number + 8-bit CRC tester) assures

absolute traceability because no two parts are

alike

 Built-in multidrop controller ensures

compatibility with other MicroLAN products

 EPROM partitioned into four 256-bit pages

for randomly accessing packetized data

 Each memory page can be permanently

write-protected to prevent tampering

 Device is an “add only” memory where

additional data can be programmed into

EPROM without disturbing existing data

 Architecture allows software to patch data by

superseding an old page in favor of a newly

programmed page

 Reduces control, address, data, power, and

programming signals to a single data pin

 Directly connects to a single port pin of a

microprocessor and communicates at up to

16.3 kbits per second

 8-bit family code specifies DS2502

communications requirements to reader

 Presence detector acknowledges when the

reader first applies voltage

 Low cost TO-92, SFN, or 8-pin SO, SOT-23

(3-pin), TSOC and WLP surface mount

package

 Reads over a wide voltage range of 2.8V to

6.0V from -40°C to +85°C; programs at

11.5V to 12.0V from -40°C to +50°C

PIN ASSIGNMENT

+09rrd

WLP, Top View with

Laser Mark, Contacts

Not Visible.

“rrd” = Revision/Date

1A, 1B = DATA

2A, 2B = GND

SFN (APPROX. 6.0mm x 6.0mm x 0.9mm)

BOTTOM VIEW

SIDE VIEW

1 2

SFN PINOUT:

PIN 1: IO

PIN 2: GND

NOTE: THE SFN PACKAGE IS QUALIFIED FOR ELECTRO-MECHANICAL

CONTACT APPLICATIONS ONLY, NOT FOR SOLDERING. FOR MORE

INFORMATION, REFER TO APPLICATION NOTE 4132: ATTACHMENT

METHODS FOR THE ELECTRO-MECHANICAL SFN PACKAGE.

DATA

TOP VIEW

TSOC PACKAGE

GND

DATA

GND

8-PIN SO (150 MIL)

DS2502

1Kb Add-Only Memory

GND

DATA

BOTTOM VIEW

TO-92

DS2502

SOT-23 Package

Top View

1 2

09rr

1 = DATA; 2, 3 = GND

“rr” = Revision

19-5075; Rev 8/14

1 of 24

Summary of content (24 pages)

PAGE 1
9-5075; Rev 8/14 DS2502 1Kb Add-Only Memory PIN ASSIGNMENT FEATURES           NC 1 8 NC DS2502 NC 2 7 NC DATA 3 6 NC GND 4 5 NC 8-PIN SO (150 MIL) TSOC PACKAGE GND DATA 1 6 2 5 NC NC NC 3 4 NC TOP VIEW NC  TO-92 DATA  1024 bits Electrically Programmable Read Only Memory (EPROM) communicates with the economy of one signal plus ground Unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48bit serial number + 8-bit CRC tester) assur
PAGE 2
DS2502 ORDERING INFORMATION PART DS2502+ DS2502+T&R DS2502G+T&R DS2502P+ DS2502P+T&R DS2502R+T&R DS2502S+ DS2502S+T&R DS2502X1+ TEMP RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C PIN-PACKAGE 3 TO-92 (straight leads) 3 TO-92 (formed leads, 2k pieces) 2 SFN (2.5k pieces) 6 TSOC 6 TSOC (4k pieces) 3 SOT-23 (3k pieces) 8 SO 8 SO (2.5k pieces) 4 WLP (10k pieces) +Denotes a lead(Pb)-free/RoHS-compliant package.
PAGE 3
DS2502 the 1-Wire line as well as indicate to the bus master how many and what types of devices are present. The protocol required for these ROM Function Commands is described in Figure 9. After a ROM Function Command is successfully executed, the memory functions that operate on the EPROM portions of the DS2502 become accessible and the bus master may issue any one of the five Memory Function Commands specific to the DS2502 to read or program the various data fields.
PAGE 4
DS2502 HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 64-BIT LASERED ROM Figure 3 8–Bit CRC Code MSB 48–Bit Serial Number LSB MSB 1-WIRE CRC GENERATOR Figure 4 4 of 24 8–Bit Family Code (09h) LSB MSB LSB
PAGE 5
DS2502 1024-BITS EPROM The memory map in Figure 5 shows the 1024-bit EPROM section of the DS2502 which is configured as four pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when programming the memory. Data is first written to the scratchpad and then verified by reading an 8-bit CRC from the DS2502 that confirms proper receipt of the data.
PAGE 6
DS2502 written. Writing data involves not only issuing the correct command sequence by also providing a 12-volt programming voltage at the appropriate times. To execute a write sequence, a byte of data is first loaded into the scratchpad and then programmed into the selected address. Write sequences always occur a byte at a time.
PAGE 7
DS2502 MEMORY FUNCTION FLOW CHART Figure 6 7 of 24
PAGE 8
DS2502 MEMORY FUNCTION FLOW CHART Figure 6 (cont’d) LEGEND: DECISION MADE BY THE MASTER DECISION MADE BY DS2502 8 of 24
PAGE 9
DS2502 MEMORY FUNCTION FLOW CHART Figure 6 (cont’d) 9 of 24
PAGE 10
DS2502 READ MEMORY [F0h] The Read Memory command is used to read data from the 1024-bit EPROM data field. The bus master follows the command byte with a 2-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. An 8-bit CRC of the command byte and address bytes is computed by the DS2502 and read back by the bus master to confirm that the correct command word and starting address were received.
PAGE 11
DS2502 eight additional read time slots and receive an 8-bit CRC that is the result of shifting into the CRC generator all of the data bytes from the initial starting byte to the last byte of the current page. Once the 8bit CRC has been received, data is again read from the 1024-bit EPROM data field starting at the next page. This sequence will continue until the final page and its accompanying CRC are read by the bus master.
PAGE 12
DS2502 significant byte of the new two-byte address will also be loaded into the 8-bit CRC generator as a starting value. The bus master will issue the next byte of data using eight write time slots. As the DS2502 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator that has been preloaded with the LSB of the current address; the result is an 8-bit CRC of the new data byte and the LSB of the new address.
PAGE 13
DS2502 issued and the current byte address should be programmed again. If the DS2502 EPROM Status Byte contains 0s in the same bit positions as the data byte, the programming was successful and the DS2502 will automatically increment its address counter to select the next byte in the EPROM Status data field. The least significant byte of the new 2-byte address will also be loaded into the 8-bit CRC generator as a starting value. The bus master will issue the next byte of data using eight write time slots.
PAGE 14
DS2502 A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At regular speed the 1-Wire bus has a maximum data rate of 16.3 kbits per second. If the bus master is also required to perform programming of the EPROM portions of the DS2502, a programming supply capable of delivering up to 10 milliamps at 12 volts for 480 µs is required. The idle state for the 1-Wire bus is high.
PAGE 15
DS2502 DS2502 EQUIVALENT CIRCUIT Figure 7 BUS MASTER CIRCUIT Figure 8 15 of 24
PAGE 16
DS2502 ROM FUNCTIONS FLOW CHART Figure 9 16 of 24
PAGE 17
DS2502 Skip ROM [CCh] This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result).
PAGE 18
DS2502 CRC GENERATION The DS2502 has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS2502 to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial function of this CRC is: X8 + X5 + X4 +1.
PAGE 19
DS2502 READ/WRITE TIMING DIAGRAM Figure 11 Write-one Time Slot DS2502 SAMPLING WINDOW 60 µs ≤ tSLOT < 120 µs 1 µs ≤ tLOW1 < 15 µs 1 µs ≤ tREC < ∞ Write-zero Time Slot DS2502 SAMPLING WINDOW 60 µs ≤ tLOW0 < tSLOT < 120 µs 1 µs ≤ tREC < ∞ Read-data Time Slot RESISTOR MASTER DS2502 60 µs ≤ tSLOT < 120 µs 1 µs ≤ tLOWR < 15 µs 0 ≤ tRELEASE < 45 µs 1 µs ≤ tREC < ∞ tRDV = 15 µs tSU < 1 µs 19 of 24
PAGE 20
DS2502 PROGRAM PULSE TIMING DIAGRAM Figure 12 20 of 24
PAGE 21
DS2502 ABSOLUTE MAXIMUM RATINGS Voltage on any Pin Relative to Ground -0.5V to +12.0V Operating Temperature -40°C to +85°C Storage Temperature -55°C to +125°C Lead Temperature (TO-92, TSOC, SOT23-3, SOIC only, soldering 10s) +300°C Soldering Temperature (reflow) TO-92 +250°C TSOC, SOT-23, SOIC, WLP +260°C SFN Refer to Application Note 4132: Attachment methods for the electro-mechanical SFN package.
PAGE 22
DS2502 NOTES: 1. All voltages are referenced to ground. 2. VPUP = external pullup voltage. 3. Input load is to ground. 4. An additional reset or communication sequence cannot begin until the reset high time has expired. 5. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 1 µs of this falling edge and will remain valid for 14 µs minimum. (15 µs total from falling edge on 1-Wire bus.) 6.
PAGE 23
DS2502 PACKAGE INFORMATION For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 3 TO-92 (straight leads) 3 TO-92 (formed leads) 2 SFN 6 TSOC 3 SOT-23 8 SO 4 WLP PACKAGE CODE Q3+1 Q3+4 G266N+1 D6+1 U3+5 S8+2 N40D1+1 23 of 24 OUTLINE NO.
PAGE 24
DS2502 REVISION HISTORY REVISION DATE 102199 030806 032307 071107 12/09 12/11 8/14 DESCRIPTION Conversion to new template. SOT-23 package added, lead (Pb)-free part numbers added. Flip chip package added. Note added that TO-92 tape & reel has formed leads. Added note to Figure 10 that changed tRSTL to 960µs maximum. Added VEPR specification. Changed tRSTL to 960µs maximum. Added notes 13 and 14 to Electrical Characteristics table. Added SFN package, cleaned up ordering information; typo corrections.