Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsIntegrated Circuits (ICs)TSOC 6 16 kBit 16 K x 1

1 of 24 071107

FEATURES

 16384 bits Electrically Programmable Read

Only Memory (EPROM) communicates with

the economy of one signal plus ground

 Unique, factory-lasered and tested 64-bit

registration number (8-bit family code +

48-bit serial number + 8-bit CRC tester)

assures absolute traceability because no two

parts are alike

 Built-in multidrop controller ensures

compatibility with other 1-Wire Net

products

 EPROM partitioned into sixty-four 256-bit

pages for randomly accessing packetized data

records

 Each memory page can be permanently write-

protected to prevent tampering

 Device is an “add only” memory where

additional data can be programmed into

EPROM without disturbing existing data

 Architecture allows software to patch data by

superseding an old page in favor of a newly

programmed page

 Reduces control, address, data, power, and

programming signals to a single data pin

 Directly connects to a single port pin of a

microprocessor and communicates at up to

16.3 kbits per second

 8-bit family code specifies DS2505

communications requirements to reader

 Presence detector acknowledges when the

reader first applies voltage

 Low cost TO-92 or 6-pin TSOC surface

mount package

 Reads over a wide voltage range of 2.8V to

6.0V from -40°C to +85°C; programs at

11.5V to 12.0V from -40°C to +50°C

DS2505

PIN ASSIGNMENT

NOTE: The leads of TO-92 packages on tape-

and-reel are formed to approximately 100 mil

(2.54 mm) spacing. For details see the Package

Information section.

ORDERING INFORMATION

DS2505 TO-92 Package

DS2505/T&R TO-92 Package, Tape & Reel

DS2505P TSOC Package

DS2505P/T&R TSOC Package, Tape & Reel

DS2505+ TO-92 Package

DS2505+T&R TO-92 Package, Tape & Reel

DS2505P+ TSOC Package

DS2505P+T&R TSOC Package, Tape & Reel

+ Denotes a lead(Pb)-free/RoHS-compliant

package.

Top View

3.7 X 4.0 X 1.5 mm

DATA

Side View

See Mech.

Drawing Section

TSOC PACKAGE

GND

16Kb Add-Only Memory

www.maxim-ic.com

1-Wire is a registered trademark of Maxim Integrated Products, Inc.

TO-92

DALLAS

DS2505

GND

DATA

2 3

Bottom View

Summary of content (24 pages)

PAGE 1
DS2505 16Kb Add-Only Memory www.maxim-ic.com            PIN ASSIGNMENT TSOC PACKAGE TO-92 DALLAS DS2505 GND 1 6 NC DATA 2 5 NC NC 3 4 NC Top View 3.7 X 4.0 X 1.5 mm Side View See Mech.
PAGE 2
DS2505 SILICON LABEL DESCRIPTION The DS2505 16Kb Add–Only Memory identifies and stores relevant information about the product to which it is associated. This lot or product specific information can be accessed with minimal interface, for example a single port pin of a microcontroller. The DS2505 consists of a factory-lasered registration number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (0BH) plus 16Kb of user-programmable EPROM.
PAGE 3
DS2505 protocol has been satisfied. This protocol is described in the ROM functions flow chart (Figure 8). The 1-Wire bus master must first provide one of four ROM function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, or 4) Skip ROM. After a ROM function sequence has been successfully executed, the bus master may then provide any one of the memory function commands specific to the DS2505 (Figure 5). The 1-Wire CRC of the lasered ROM is generated using the polynomial X8 + X5 + X4 + 1.
PAGE 4
DS2505 HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 64-BIT LASERED ROM Figure 3 8-Bit CRC Code MSB 48-Bit Serial Number LSB MSB 8-Bit Family Code (0BH) LSB MSB LSB 16384-BITS EPROM The memory map in Figure 4 shows the 16384-bit EPROM section of the DS2505 which is configured as 64 pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when programming the memory.
PAGE 5
DS2505 EPROM STATUS BYTES In addition to the 16384 bits of data memory the DS2505 provides 704 bits of Status Memory accessible with separate commands. The EPROM Status Bytes can be read or programmed to indicate various conditions to the software interrogating the DS2505.
PAGE 6
DS2505 The Status Memory address range of the DS2505 extends from 000 to 13FH. The memory locations 008H to 01FH, 028H to 03FH, 048H to 0FFH and 140H to 7FFH are physically not implemented. Reading these locations will usually result in FFH bytes. Attempts to write to these locations will be ignored. If the bus master sends a starting address higher than 7FFH, the five most significant address bits are set to 0s by the internal circuitry of the chip.
PAGE 7
DS2505 MEMORY FUNCTION COMMANDS The “Memory Function Flow Chart” (Figure 5) describes the protocols necessary for accessing the various data fields within the DS2505. The Memory Function Control section, 8-bit scratchpad, and the Program Voltage Detect circuit combine to interpret the commands issued by the bus master and create the correct control signals within the device. A 3-byte protocol is issued by the bus master.
PAGE 8
DS2505 MEMORY FUNCTION FLOW CHART Figure 5 8 of 24
PAGE 9
DS2505 MEMORY FUNCTION FLOW CHART Figure 5 (cont’d) 9 of 24
PAGE 10
DS2505 MEMORY FUNCTION FLOW CHART Figure 5 (cont’d) 10 of 24
PAGE 11
DS2505 Note that the initial pass through the Read Status flow chart will generate a 16-bit CRC value that is the result of clearing the CRC generator and then shifting in the command byte followed by the 2 address bytes, and finally the data bytes beginning at the first addressed memory location and continuing through to the last byte of the addressed EPROM Status data page. The last byte of a Status data page always has an ending address of xx7 or xxFH.
PAGE 12
DS2505 With the next 24 read data time slots the master will receive the Redirection Byte of the next page followed by a 16-bit CRC of the Redirection Byte. After this, data is again read from the 16,384-bit EPROM data field starting at the beginning of the new page. This sequence will continue until the final page and its accompanying CRC are read by the bus master.
PAGE 13
DS2505 As the DS2505 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator that has been preloaded with the current address and the result is a 16-bit CRC of the new data byte and the new address. After supplying the data byte, the bus master will read this 16-bit CRC from the DS2505 with sixteen read time slots to confirm that the address incremented properly and the data byte was received correctly.
PAGE 14
DS2505 responds with the data from the selected EPROM Status address sent least significant bit first. This byte contains the logical AND of all bytes written to this EPROM Status Byte address. If the EPROM Status Byte contains 1s in bit positions where the byte issued by the master contained 0s, a Reset Pulse should be issued and the current byte address should be programmed again.
PAGE 15
DS2505 Hardware Configuration The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have an open drain connection or 3-state outputs. The DS2505 is an open drain part with an internal circuit equivalent to that shown in Figure 6. The bus master can be the same equivalent circuit.
PAGE 16
DS2505 DS2505 EQUIVALENT CIRCUIT Figure 6 BUS MASTER CIRCUIT Figure 7 16 of 24
PAGE 17
DS2505 ROM FUNCTIONS FLOW CHART Figure 8 17 of 24
PAGE 18
DS2505 Match ROM [55H] The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS2505 on a multidrop bus. Only the DS2505 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus.
PAGE 19
DS2505 (Figure 11) should be applied for 480 µs, after which the bus master returns the data line to an idle high state controlled by the pullup resistor. Note that due to the high voltage programming requirements for any 1-Wire EPROM device, it is not possible to multidrop non-EPROM based 1-Wire devices with the DS2505 during programming. An internal diode within the non-EPROM based 1-Wire devices will attempt to clamp the data line at approximately 8 volts and could potentially damage these devices.
PAGE 20
DS2505 READ/WRITE TIMING DIAGRAM Figure 10 (cont’d) NOTE: For read-data time slots the optimal sampling point for the master is as close as possible to the end of the tRDV period without exceeding the 15 µs window. For the case of a read-one time slot, this maximizes the amount of time for the pull-up resistor to recover the line to a high land. For a read-zero time slot it ensures that a read will occur before the fastest 1-Wire device releases the line (tRELEASE = 0).
PAGE 21
DS2505 PROGRAM PULSE TIMING DIAGRAM Figure 11 CRC GENERATION With the DS2505 there are two different types of CRCs (Cyclic Redundancy Checks). One CRC is an 8-bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS2505 to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial function of this CRC is: X8 + X5 + X4 + 1.
PAGE 22
DS2505 When reading the data memory of the DS2505 with the Extended Read Memory command, there are two situations where a 16-bit CRC is transmitted. One 16-bit CRC follows each Redirection Byte; another 16-bit CRC is received after the last byte of a memory data page is read. The CRC at the end of the memory page is always the result of clearing the CRC generator and shifting in the data bytes beginning at the first addressed memory location of the EPROM data page until the last byte of this page.
PAGE 23
DS2505 ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.5V to +12.0V -40°C to +85°C -55°C to +125°C See J-STD-020A specification * This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
PAGE 24
DS2505 NOTES: 1. All voltages are referenced to ground. 2. VPUP = external pullup voltage. If VPUP is lower than 3.0V the first byte read (any read command) may not reproduce the correct memory contents. Therefore, under low voltage conditions, it is recommended to set either the most significant bit or all five most significant bits of TA2 to 1. Internal circuitry of the chip will force these 5 bits back to 0 before they are shifted in the address counter and CRC generator. 3. Input load is to ground. 4.