Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal QSOP 24

General Description

The MAX1167/MAX1168 low-power, multichannel, 16-

bit analog-to-digital converters (ADCs) feature a suc-

cessive-approximation ADC, integrated +4.096V

reference, a reference buffer, an internal oscillator,

automatic power-down, and a high-speed SPI™/

QSPI™/MICROWIRE™-compatible interface. The

MAX1167/MAX1168 operate with a single +5V analog

supply and feature a separate digital supply, allowing

direct interfacing with +2.7V to +5.5V digital logic.

The MAX1167/MAX1168 consume only 3.6mA (AV

= +5V) at 200ksps when using an external reference.

AutoShutdown™ reduces the supply current to 185µA at

10ksps and to less than 10µA at reduced sampling rates.

The MAX1167 includes a 4-channel input multiplexer, and

the MAX1168 accepts up to eight analog inputs.

In addition, digital signal processor (DSP)-initiated con-

versions are simplified with the DSP frame-sync input and

output featured in the MAX1168. The MAX1168 includes

a data-bit transfer input to select between 8-bit-wide or

16-bit-wide data-transfer modes. Both devices feature a

scan mode that converts each channel sequentially or

one channel continuously.

Excellent dynamic performance and low power, com-

bined with ease of use and an integrated reference, make

the MAX1167/MAX1168 ideal for control and data-acqui-

sition operations or for other applications with demanding

power consumption and space requirements. The

MAX1167 is available in a 16-pin QSOP package and the

MAX1168 is available in a 24-pin QSOP package. Both

devices are guaranteed over the commercial (0°C to

+70°C) and extended (-40°C to +85°C) temperature

ranges. Use the MAX1168 evaluation kit to evaluate the

MAX1168.

Applications

Motor Control

Industrial Process Control

Industrial I/O Modules

Data-Acquisition Systems

Thermocouple Measurements

Accelerometer Measurements

Features

♦ 16-Bit Resolution, No Missing Codes

♦ +5V Single-Supply Operation

♦ Adjustable Logic Level (+2.7V to +5.25V)

♦ Input Voltage Range: 0 to V

REF

♦ Internal (+4.096V) or External (+3.8V to AV

)

Reference

♦ Internal Track/Hold, 4MHz Input Bandwidth

♦ Internal or External Clock

♦ SPI/QSPI/MICROWIRE-Compatible Serial

Interface, MAX1168 Performs DSP-Initiated

Conversions

♦ 8-Bit-Wide or 16-Bit-Wide Data-Transfer Mode

(MAX1168 Only)

♦ 4-Channel (MAX1167) or 8-Channel (MAX1168)

Input Mux

Scan Mode Sequentially Converts Multiple

Channels or One Channel Continuously

♦ Low Power

3.6mA at 200ksps

1.85mA at 100ksps

185µA at 10ksps

0.6µA in Full Power-Down Mode

♦ Small Package Size

16-Pin QSOP (MAX1167)

24-Pin QSOP (MAX1168)

MAX1167/MAX1168

Multichannel, 16-Bit, 200ksps Analog-to-Digital

Converters

________________________________________________________________

Maxim Integrated Products

Ordering Information

19-2956; Rev 1; 10/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE

PIN-

PACKAGE

INL

(LSB)

MAX1167BCEE 0°C to +70°C 16 QSOP ±3

MAX1167BEEE -40°C to +85°C 16 QSOP ±3

MAX1168BCEG 0°C to +70°C 24 QSOP ±3

MAX1168BEEG -40°C to +85°C 24 QSOP ±3

SPI/QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

AutoShutdown is a trademark of Maxim Integrated Products, Inc.

Pin Configurations appear at end of data sheet.

Summary of content (30 pages)

PAGE 1
9-2956; Rev 1; 10/09 KIT ATION EVALU LE B A IL A AV Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters The MAX1167/MAX1168 low-power, multichannel, 16bit analog-to-digital converters (ADCs) feature a successive-approximation ADC, integrated +4.096V reference, a reference buffer, an internal oscillator, automatic power-down, and a high-speed SPI™/ QSPI™/MICROWIRE™-compatible interface.
PAGE 2
MAX1167/MAX1168 Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters ABSOLUTE MAXIMUM RATINGS AVDD to AGND .........................................................-0.3V to +6V DVDD to DGND.........................................................-0.3V to +6V DGND to AGND.....................................................-0.3V to +0.3V AIN_, REF, REFCAP to AGND..................-0.3V to (AVDD + 0.3V) SCLK, CS, DSEL, DSPR, DIN to DGND ...................-0.3V to +6V DOUT, DSPX, EOC to DGND...........
PAGE 3
Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters (AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF = +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Internal Clock Frequency SYMBOL f INTCLK Aperture Delay tAD Aperture Jitter tAJ Sample Rate (Note 7) fS CONDITIONS Internal clock MIN TYP MAX 3.2 4.0 MHz 15 ns <50 ps 8-bit-wide data-transfer mode 4.17 200.
PAGE 4
MAX1167/MAX1168 Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF = +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL OUTPUT (DOUT, DSPX, EOC) (DVDD = +2.7V to +5.
PAGE 5
Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters (AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF = +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 6
MAX1167/MAX1168 Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters TIMING CHARACTERISTICS (Figures 1, 2, 8, and 16) (AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF = +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 7
Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters 1.0 0 0 -0.5 -0.5 -1.0 -1.0 -1.5 -1.5 0 -20 AMPLITUDE (dB) 0.5 DNL (LSB) 0.5 20 MAX1167/68 toc02 MAX1167/68 toc01 1.0 INL (LSB) FFT AT fAIN = 1kHz DNL vs. CODE 1.5 MAX1167/68 toc03 INL vs. CODE 1.5 -40 -60 -80 -100 -120 -140 16384 32768 49152 65536 -160 0 16384 32768 CODE 100 70 40 30 20 fSAMPLE = 200kbps 0.1 1 10 60 fSAMPLE = 200kbps -60 40 -80 20 -100 fSAMPLE = 200ksps 0 100 0.1 1 10 -120 0.
PAGE 8
Typical Operating Characteristics (continued) (AVDD = DVDD = +5V, fSCLK = 4.8MHz, CDOUT = 30pF, external VREF = +4.096V, TA = +25°C, unless otherwise noted.) 0.57 1.03 0.6 1.02 0.5 1.01 0.55 1.0 0.54 0.6 0.53 IDVDD 0.4 1.00 0.3 0.99 0.2 0.98 0.1 1.01 IAVDD IDVDD 0.52 0.2 2.70 3.21 3.72 4.23 4.75 5.25 4.74 4.85 4.95 5.05 5.25 5.15 4.23 SHUTDOWN SUPPLY CURRENT vs. DVDD SUPPLY VOLTAGE (EXTERNAL REFERENCE) MAX1167/68 toc13 0.58 3.72 DVDD (V) SHUTDOWN SUPPLY CURRENT vs.
PAGE 9
Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters GAIN ERROR vs. SUPPLY VOLTAGE -200 -300 0.02 0.01 0 50 0 -50 -100 -0.02 4.95 5.05 5.15 -150 4.75 5.25 4.85 4.95 5.05 5.15 5.25 -40 -15 10 35 85 60 AVDD (V) AVDD (V) TEMPERATURE (°C) GAIN ERROR vs. TEMPERATURE CHANNEL-TO-CHANNEL ISOLATION vs. FREQUENCY INTERNAL +4.096V REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE -20 -0.002 -0.003 DVDD = +5V 4.100 -40 -60 TA = +70°C 4.096 TA = +25°C -80 4.092 -0.
PAGE 10
MAX1167/MAX1168 Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters Pin Description PIN NAME FUNCTION MAX1167 MAX1168 1 3 DOUT Serial Data Output. Data changes state on SCLK’s falling edge in SPI/QSPI/MICROWIRE mode and on SCLK’s rising edge in DSP mode (MAX1168 only). DOUT is high impedance when CS is high. 2 4 SCLK Serial Clock Input. SCLK drives the conversion process in external clock mode and clocks data out. 3 5 DIN Serial Data Input.
PAGE 11
Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters PIN NAME FUNCTION MAX1167 MAX1168 — 13 AIN6 Analog Input 6 — 14 AIN7 Analog Input 7 — 23 DSPX DSP Frame-Sync Transmit Output. A frame-sync pulse at DSPX notifies the DSP that the MSB data is available at DOUT. Leave DSPX unconnected when not in DSP mode. — 24 N.C. No Connection. Not internally connected.
PAGE 12
MAX1167/MAX1168 Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters AVDD REFCAP DVDD BUFFER REFERENCE REF AGND MAX1167 AIN0 AIN1 ANALOG-INPUT MULTIPLEXER DAC COMPARATOR AIN2 AZ RAIL AIN3 ANALOG-SWITCH FINE TIMING BIAS SCLK MULTIPLEXER SUCCESSIVE-APPROXIMATION REGISTER OUTPUT DOUT OSCILLATOR ACCUMULATOR CONTROL CS EOC MEMORY INPUT REGISTER DIN AGND DGND Figure 3.
PAGE 13
Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168 AVDD REFCAP DVDD BUFFER REFERENCE REF AGND MAX1168 AIN0 AIN1 AIN2 AIN3 AIN4 ANALOG-INPUT MULTIPLEXER DAC COMPARATOR AIN5 AIN6 AZ RAIL AIN7 ANALOG-SWITCH FINE TIMING BIAS SCLK SUCCESSIVE-APPROXIMATION REGISTER MULTIPLEXER OUTPUT DOUT OSCILLATOR ACCUMULATOR CS EOC DSPX CONTROL DSEL DSPR MEMORY INPUT REGISTER DIN AGND DGND Figure 4.
PAGE 14
MAX1167/MAX1168 Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters CS AIN0 AIN1 AIN2 AIN3 ANALOG INPUTS DIN CS SCLK DOUT EOC SCLK DOUT EOC CS AIN0 AIN1 AIN2 AIN3 ANALOG INPUTS AIN4 AIN5 AIN6 DIN CS SCLK DSPX SCLK DSPX DOUT DOUT EOC EOC AIN7 MAX1167 REF DIN 16 8 1μF AGND AGND DGND AVDD +5V 0.1μF DVDD +5V DIN MAX1168 DSEL DSPR REF 1μF AGND AGND DGND AVDD +5V REFCAP 0.1μF 0.1μF 0.1μF DVDD +5V REFCAP 0.1μF 0.1μF GND GND Figure 5.
PAGE 15
Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters BIT7 BIT6 BIT5 CH SEL2 CH SEL1 CH SEL0 CHANNEL AIN_ 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 1 1 1 1 Table 3. MAX1167 Scan Mode, Internal Clock Only BIT4 BIT3 SCAN1 SCAN0 Single channel, no scan 0 0 Sequentially scan channels 0 through N (N ≤ 3) 0 1 5 Sequentially scan channels 2 through N (2 ≤ N ≤ 3) 1 0 0 6 Scan channel N four times 1 1 1 7 ACTION Table 4.
PAGE 16
MAX1167/MAX1168 Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters tCSW CS tCSS tCP tCL tCSH tCH ••• SCLK tDS tDH DIN tDO tTR tDV DOUT Figure 8. Detailed SPI Interface Timing when in SPI/QSPI/MICROWIRE mode and on the falling edge of DSPR when in DSP mode. Allow 5ms for the internal reference to rise and settle when powering up from a complete shutdown (VREF = 0, CREF = 1µF). CS COMPLETE CONVERSION SEQUENCE DOUT CONVERSION 0 CONVERSION 1 POWERED UP POWERED DOWN POWERED UP Figure 9.
PAGE 17
Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168 CS 1 16 8 24 SCLK MSB LSB DIN 0 MSB LSB DOUT DSPR* DSEL* ADC STATE tACQ tCONV IDLE *MAX1168 ONLY Figure 10. SPI External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing SCLK rates less than 125kHz can reduce accuracy due to leakage of the sampling capacitor. DOUT changes from high-Z to logic low after CS is brought low. Input data latches on the rising edge of SCLK.
PAGE 18
MAX1167/MAX1168 Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters CS 1 16 8 24 32 SCLK MSB LSB 0 X DIN X X X X X X X MSB LSB DOUT DSPR DSEL ADC STATE tACQ , X = DON T CARE IDLE tCONV Figure 11. SPI External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only) CS 1 9 8 16 24 SCLK 2 INTERNAL CLK MSB DIN 6 25 LSB 1 LSB MSB DOUT X EOC ADC STATE , X = DON T CARE DSPR = DVDD, DSEL = GND (MAX1168 ONLY) tACQ tCONV IDLE POWER-DOWN Figure 12.
PAGE 19
Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168 CS 1 8 9 16 17 24 32 SCLK 2 13 32 INTERNAL CLK DIN DATA XXXXXXXX LSB MSB DOUT X EOC ADC STATE CONFIGURATION , X = DON T CARE DSPR = DSEL = DVDD tACQ tCONV POWER-DOWN Figure 13.
PAGE 20
MAX1167/MAX1168 Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters CS 1 8 9 48 17 16 SCLK 32 13 2 34 45 64 INTERNAL CLK DIN DATA XXXXXXXX LSB MSB DOUT X EOC ADC STATE tACQ , X = DON T CARE tACQ tCONV tCONV POWER-DOWN Figure 15. SPI Internal Clock Mode, 16-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing (MAX1168 Only) tCSW ... CS tDF tFSS ... DSPR tFSH tCSS tCL tCSH tCH ... SCLK tCP tDS tDH ... DIN tDO tDV DOUT tTR ... Figure 16.
PAGE 21
Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168 CS DSPR 16 1 8 MSB LSB 24 SCLK DIN 0 MSB LSB DOUT DSPX ADC STATE tACQ IDLE tCONV Figure 17. DSP External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only) CS DSPR 1 8 MSB LSB 0 X 16 24 32 SCLK DIN X X X X X X X LSB MSB DOUT DSPX ADC STATE , X = DON T CARE tACQ tCONV IDLE Figure 18.
PAGE 22
MAX1167/MAX1168 Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters OUTPUT CODE FULL-SCALE TRANSITION 1111...111 1111...110 1111...101 FS = VREF V 1 LSB = REF 65,536 0000...011 0000...010 0000...001 0000...000 0 1 2 3 INPUT VOLTAGE (LSB) FS FS - 3/2 LSB Figure 19. Unipolar Transfer Function, Full Scale (FS) = VREF, Zero Scale (ZS) = GND setting bits 4 and 3 in the command/configuration/control register (see Tables 3 and 4).
PAGE 23
Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters I/O CS SCLK SK SCLK MISO DOUT SI DOUT I/O VDD SPI MICROWIRE MAX1167 MAX1168 SS MAX1167 MAX1168 Figure 20a. SPI Connections Figure 20b. MICROWIRE Connections 1ST BYTE READ 1 SCLK MAX1167/MAX1168 CS SCK 2ND BYTE READ 4 6 12 8 16 CS DOUT* 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 MSB *WHEN CS IS HIGH, DOUT = HIGH-Z 3RD BYTE READ 20 24 HIGH-Z D7 D6 D5 D4 D3 D2 D1 D0 LSB Figure 20c.
PAGE 24
MAX1167/MAX1168 Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters Table 7. Detailed SSPCON Register Contents CONTROL BIT SETTINGS SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON) WCOL BIT7 X Write Collision Detection Bit SSPOV BIT6 X Receive Overflow Detection Bit 1 Synchronous Serial-Port Enable Bit: 0: Disables serial port and configures these pins as I/O port pins. 1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins. Clock Polarity Select Bit.
PAGE 25
Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters CONTROL BIT SETTINGS SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT) SMP BIT7 0 SPI Data-Input Sample Phase. Input data is sampled at the middle of the data output time. CKE BIT6 1 SPI Clock Edge-Select Bit. Data is transmitted on the rising edge of the serial clock.
PAGE 26
MAX1167/MAX1168 Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters 1ST BYTE READ 1 SCLK 2ND BYTE READ 4 6 8 12 16 CS DOUT* 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 MSB *WHEN CS IS HIGH, DOUT = HIGH-Z 3RD BYTE READ 24 20 HIGH-Z D7 D6 D5 D4 D3 D2 D1 D0 LSB Figure 22b.
PAGE 27
Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters AIN_ SCLK DOUT REF 12 EFFECTIVE BITS CS AIN_ 14 1μF AVDD +5V 10 0.1μF 8 MAX1167 MAX1168 10Ω 6 DVDD 4 0.1μF 2 CS SCLK DOUT AGND AGND DGND fSAMPLE = 200ksps 0 0.1 1 10 100 FREQUENCY (kHz) GND Figure 25. Powering AVDD and DVDD from a Single Supply Figure 24. Effective Bits vs. Frequency DSP Interface Aperture Definitions The DSP mode of the MAX1168 only operates in external clock mode.
PAGE 28
MAX1167/MAX1168 Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the ENOB as follows: ENOB = (SINAD - 1.76) / 6.02 Figure 24 shows the ENOB as a function of the MAX1167/MAX1168s’ input frequency.
PAGE 29
Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters TOP VIEW DOUT 1 16 DVDD DSPR 1 24 N.C.
PAGE 30
MAX1167/MAX1168 Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters Revision History REVISION NUMBER REVISION DATE 0 8/03 1 10/09 DESCRIPTION PAGES CHANGED Initial release. — Changed 2.9mA at 200ksps to 3.6mA at 200ksps, 1.45mA at 100ksps to 1.85mA at 100ksps, and 145μA at 10ksps to 185μA to 10ksps in the General Description and Features sections. 1 Removed the ±1.2 INL LSB and ±2 INL LSB packages from the Ordering Information table.