Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal SOIC 16 W

General Description

The MAX121 is a complete, BiCMOS, serial-output,

sampling 14-bit analog-to-digital converter (ADC) that

com bines an on-chip track/hold and a low-drift, low-

noise, buried-zener voltage reference with fast conversion

speed and low power consumption. The throughput rate

is as high as 308k samples per second (ksps). The full-

scale analog input range is ±5V.

The MAX121 utilizes the successive-approximation archi-

tecture with a high-speed DAC to achieve both fast

conversion speeds and low-power operation. Operating

with +5V and -12V or -15V power supplies, power con-

sumption is only 210mW.

The MAX121 can be directly interfaced to the serial port

of most popular digital-signal processors, and comes

in space-saving 16-pin DIP and SO and smaller 20-pin

SSOP packages. The MAX121 operates with TTL- and

CMOS-compatible clocks in the frequency range from

1.1MHz to 5.5MHz. All logic inputs and outputs are TTL -

and CMOS-compatible. This data sheet includes applica-

tion notes for easy interface to TMS320, µPD77230, and

ADSP2101 digital-signal processors, as well as µPs using

the Motorola SPI and QSPI interface standards.

Applications

● Digital Signal Processing

● Audio and Telecom Processing

● Speech Recognition and Synthesis

● DSP Servo Control

● Spectrum Analysis

Benets and Features

● 14-Bit Resolution

● 2.9µs Conversion Time/308ksps Throughput

● 400ns Acquisition Time

● Low Noise and Distortion

• 78d8 SINAD

• -85dB THD

● ±5V Bipolar Input Range, Overvoltage Tolerant to

±15V

● 210mW Power Dissipation

● Continuous-Conversion Mode Available

● 30ppm/°C, -5V Internal Reference

● Interfaces to DSP Processors

● 16-Pin DIP and SO Packages,

20-Pin SSOP Package

Ordering Information appears at end of data sheet.

For related parts and recommended products to use with this part, refer

to www.maximintegrated.com/MAX121.related.

DAC

SAR

AIN

3kΩ

TRACK/HOLD

CONTROL LOGIC

MAX121

BUFFER

7pF

REFERENCE

SAMPLING

COMPARATOR

-5V

AGND

DGND

SDATA

SCLK

FSTRT

SFRM

CONVST CS MODE INVCLK INVFRM

3kΩ

REF

CLIKIN

MAX121 308ksps ADC with DSP Interface and 78dB SINAD

19-0108; Rev 3; 1/12

Functional Diagram

EVALUATION KIT AVAILABLE

Summary of content (26 pages)

PAGE 1
EVALUATION KIT AVAILABLE MAX121 308ksps ADC with DSP Interface and 78dB SINAD General Description The MAX121 is a complete, BiCMOS, serial-output, sampling 14-bit analog-to-digital converter (ADC) that com bines an on-chip track/hold and a low-drift, lownoise, buried-zener voltage reference with fast conversion speed and low power consumption. The throughput rate is as high as 308k samples per second (ksps). The fullscale analog input range is ±5V.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD Absolute Maximum Ratings VDD to DGND ..........................................................-0.3V to +6V VSS to DGND.........................................................+0.3V to -17V AIN to AGND........................................................................±15V AGND to DGND..................................................................±0.3V Digital Inputs to DGNO.............................. -0.3V to (VDD + 0.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD Electrical Characteristics (continued) (VDD = 4.75V to 5.25V, VSS = -10.8V to -15.75V, fCLK = 5.5MHz, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE Output Voltage No external load, VAIN = 5V, TA = +25°C External Load Regulation 0mA < ISINK < 5mA, VAIN = 0V -5.02 Temperature Drift (Note 4) -4.98 V 5 mV ±30 ppm/°C 2.91 µs 5.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD Timing Characteristics (VDD = 5V, VSS = -12V or -15V, TA = TMIN to TMAX, unless otherwise noted.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD Pin Configurations TOP VIEW 1 + VSS 2 VDD 3 AIN MODE 16 CS 15 CLKIN 14 MAX121 CONVST 13 AGND SCLK 12 INVCLK SDATA 11 4 VREF 5 6 7 INVFRM 8 DGND FSTRT 10 SFRM 9 + 20 MODE VSS 1 VDD 2 AIN 3 VREF 4 17 CONVST N.C. 5 16 N.C. N.C. 6 15 N.C.
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MAX121 AGND 308ksps ADC with DSP Interface and 78dB SINAD 0.1µF 10µF -12V/-15V VSS MODE +5V VDD CS 0.1µF 10µF AGND DGND SAMPLING COMPARATOR AIN MAX121 ANALOG INPUT AIN 0.1µF 22µF VREF AGND CLKIN CONVST DGND SCLK AGND VDD CLOCK INPUT INVCLK SDATA INVFRM FSTRT TO SERIAL PORT CPACKAGE 10pF 3kΩ TRACK 3kΩ BUFFER CHOLD 7pF HOLD VREF VREF (-5V) CSWITCH 2pF DAC SAR DGND DGND Figure 1. MAX121 in the Simplest Operational Mode (Continuous-Conversion Mode) Figure 2.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD Proper bypassing minimizes reference noise and maintains a low impedance at high frequencies. The internal reference output buffer can sink up to 5mA from an external load. An external reference voltage can be used to overdrive the MAX121’s internal reference, if the external reference lies within the range from -5.05V to -5.10V. The external reference must be capable of sinking a minimum of 5mA. The external VREF bypass capacitors are still required.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD Operating Modes Timing and Control Mode 1: CONVST Controls Conversion Starts (MODE = VDD, CS = DGND) The MAX121 has three possible modes of operation, as outlined in the timing diagrams of Figures 7–9 and discussed in the Operating Modes section. Figure 7 shows the timing diagram for mode 1. In this mode, conversion start operations are controlled by the CONVST input. In Mode 1, the CONVST input is used to control the start of the conversion.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD Mode 2: CS Controls Conversion Starts (MODE = VDD, CONVST = DGND) Mode 3: Continuous-Conversion Mode (CONVST = CS = MODE = DGND) Figure 8 shows the timing diagram for mode 2. In mode 2, CS controls the conversion start and enables the serial output pins. Mode 2 is useful in applications where the MAX121 shares the output data bus with other devices.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD 15 16 1 13 14 15 16 1 CLKIN FSTRT 15 SCLK (INVCLK = VCD) SDATA T/H 16 LSB 1 13 MSB D2 14 D1 15 16 1 MSB LSB HOLD TRACK tAQ Figure 9.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD Maximum Clock Rate tor Serial Interface Motorola SPI Serial Interface (CPOL = 0, CPHA = 1) The maximum serial clock rate depends upon the minimum setup time required by the receiving processor’s serial data input and the ADC’s maximum clock-to-data delay. The MAX121 allows two fundamentally different methods of clocking data into the processor.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD Motorola QSPI Serial Interlace (CPOL = 0, CPHA = 1) time of 10ns (tSCS) and a minimum data-hold time of 10ns (tSCH). This interface permits operation of the MAX121 at its maximum clock rate of 5.5MHz. Figure 14 shows the connections required to implement a QSPI interface with the MAX121. The timing diagram for this interface is shown in Figure 15.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD +5V DMS OR PMS INVCLK CONVST SCLK SCLK MAX121 ADSP2101 RFS SFRM DR SDATA INVFRM CS CLKIN OSC 0.1MHz ≤ f ≤ 5.5MHz DGND Figure 16. ADSP2101 to MAX121 Interface CONVST CLKIN 1 2 14 15 16 17 SCLK (INVCLK = VCC) 1 2 14 15 16 17 SFRM (INVFRM = GND) tSCH tSCS MSB SDATA D12 LSB D1 Figure 17.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD NEC µPD77230 Serial Interface This section describes an interface that allows the maximum throughput to be obtained from the MAX121to-TMS320 system, by operating the MAX121 at its maximum clock. Figure 20 shows the interconnections required to implement this interface. Figure 21 is the timing diagram for this interface. Figure 18 shows the connections required to interface the MAX121 to NEC’s µPD77230 DSP without external glue logic.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD TMS320 Simple Serial Interface Figure 22 shows an application circuit using the simplest interface between the MAX121 and the TMS320. The timing diagram for this circuit is shown in Figure 23. In this circuit, the CLKR port of the TMS320 is configured as a clock output and drives the CLKIN of the MAX121. The MAX121 output changes state on the rising edge of the CLKIN while the data is latched into the DR port of the TMS320 on the falling edge.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD The board layout should ensure that digital and analog signal lines are kept separate, as much as possible. Take care not to run analog and digital (especially clock) lines parallel to one another. The high-speed comparator in the ADC is sensitive to high-frequency noise in the VDD and VSS power supplies. Bypass these supplies to the analog-ground plane with 0.1µF and 10µF bypass capacitors.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD CONVST CLKIN 1 2 14 15 FSTRT SDATA MSB D12 D1 LSB Figure 23. TMS320 Simple Serial-Interface Timing Diagram ;;#;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; ;; Project : Maxim 121 to TI TMS320C30 Application Note ;; ;; File: maximti.asm ;; Purpose: This file contains the code that is loaded onto the TMS320C30 Evaluation Module (EVM).
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Publics; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; .global maxim .global wait_sample .global wait_loop .global next_sample .global IOF_MASK_AMASK .global IOF_SET_XFI .global IOF_RESET_XFI .global CTRL .global SERGLOB1 .
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Functions; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; .
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD wait_sample ; ; wait for completion of conversion ; MAX121 SFRM Active signals TMS320 FSR1 that data transfer ; is ready to start.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD /*#********************************************************************************************************************* Project : Maxim 121 to TMS320C30 Application Note ** ** File: readdata.c ** Purpose: This file contains a PC based program used to read data from the TMS320C30 Evaluation Module (EVM) and display the ** data on the PC screen. ** This file may be compiled with either the Microsoft C Compiler of Borland C++ Compiler.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD while( !quit ) { if(kbhit( )) { switch ( gletch ( )) case ‘m’ : max = -32768 min = 32767; break; case ‘q’: case 0x1B: quit = 1; break; /* Clear Max/Min Storage Variables */ /* Quit Program */ } } for (x=o; x<30000; x++) { /* Gather samples as fast as possible and update Max/Min */ /* Only output every 30,000th sample. The 30,000 has no */ /* specific origin other than the display updated at a */ /* comfortable rate.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD DIGITAL SUPPLY -15V -15V AGND +5V 60 OPTIONAL 5Ω FILTER RESISTOR -15V AGND +5V DGND MAX121 WITH PI FILTER DGND VDD REJECTION (dB) ANALOG SUPPLY +5V DGND NO PI FILTER TA = +25°C 100k 10k Figure 28. VDD Power-Supply Rejection vs. Frequency fS = 300kHz IIN = 50kHz TA = +25°C SINAD = 78dB SIGNAL AMPLITUDE (dB) VSS REJECTION (dB) -20 50 40 -40 -60 -80 -100 -120 TA = +25°C 100k 1M FREQUENCY (Hz) Figure 27.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD 14 011...111 011...110 EFFECTIVE BITS 13 12 000...010 000...001 11 000...000 10 111...111 111...110 9 7 111...101 fS = 300kHz TA = +25°C 8 10k 100...001 100k 1M 10M INPUT FREQUENCY (Hz) 100...000 -5V 4.99939V 0V Figure 30. Effective Bits vs. Input Frequency Figure 31.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD Package Information Ordering Information PART TEMP RANGE PIN-PACKAGE MAX121CPE+ 0°C to +70°C 16 PDIP MAX121CWE+ 0°C to +70°C 16 Wide SO MAX121CAP+ 0°C to +70°C 20 SSOP* MAX121EPE+ -40°C to +85°C 16 PDIP MAX121EWE+ -40°C to +85°C 16 Wide SO MAX121EAP+ -40°C to +85°C 20 SSOP* MAX121EVKIT-DIP 0°C to +70°C Through-Hole +Denotes a lead(Pb)-free/RoHS-compliant package.
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MAX121 308ksps ADC with DSP Interface and 78dB SINAD Revision History REVISION NUMBER REVISION DATE 0 1/93 Initial release 3 1/12 Remove military grade and update Ordering Information DESCRIPTION PAGES CHANGED — 1–4, 24 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.