Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External SSOP 28

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General Description

The MAX1403 18-bit, low-power, multichannel, serial-

output analog-to-digital converter (ADC) features

matched 200µA current sources for sensor excitation.

This ADC uses a sigma-delta modulator with a digital

decimation filter to achieve 16-bit accuracy. The digital

filter’s user-selectable decimation factor allows the con-

version resolution to be reduced in exchange for a

higher output data rate. True 16-bit performance is

achieved at an output data rate of up to 480sps. In

addition, the modulator sampling frequency may be

optimized for either lowest power dissipation or highest

throughput rate. The MAX1403 operates from +3V.

This device offers three fully differential input channels

that may be independently programmed with a gain

between +1V/V and +128V/V. Furthermore, it can com-

pensate an input-referred DC offset up to 117% of the

selected full-scale range. These three differential chan-

nels may also be configured to operate as five pseudo-

differential input channels. Two additional, fully

differential system-calibration channels are provided for

gain and offset error correction.

The MAX1403 can be configured to sequentially scan all

signal inputs and provide the results via the serial inter-

face with minimum communications overhead. When

used with a 2.4576MHz or 1.024MHz master clock, the

digital decimation filter can be programmed to produce

zeros in its frequency response at the line frequency and

associated harmonics, ensuring excellent line rejection

without the need for further postfiltering.

The MAX1403 is available in a 28-pin SSOP package.

Applications

Portable Industrial Instruments

Portable Weigh Scales

Loop-Powered Systems

Pressure Transducers

Features

♦ 18-Bit Resolution, Sigma-Delta ADC

♦ 16-Bit Accuracy with No Missing Codes to 480sps

♦ Matched On-Board Current Sources (200µA) for

Sensor Excitation

♦ Low Quiescent Current

250µA (operating mode)

2µA (power-down mode)

♦ 3 Fully Differential or 5 Pseudo-Differential Signal

Input Channels

♦ 2 Additional, Fully Differential Calibration

Channels/Auxiliary Input Channels

♦ Programmable Gain and Offset

♦ Fully Differential Reference Inputs

♦ Converts Continuously or On Command

♦ Automatic Channel Scanning and Continuous

Data Output Mode

♦ Operates with Analog and Digital Supplies

from +2.7V to +3.6V

♦ SPI™/QSPI™-Compatible 3-Wire Serial Interface

♦ 28-Pin SSOP Package

MAX1403

+3V, 18-Bit, Low-Power, Multichannel,

Oversampling (Sigma-Delta) ADC

________________________________________________________________ Maxim Integrated Products 1

SCLK

DIN

DOUT

INT

DGND

AIN5

CALOFF+

CALOFF-

REFIN+

REFIN-

CALGAIN+

CALGAIN-

AIN6

AIN4

AIN3

AIN2

AIN1

V+

AGND

OUT1

OUT2

DS0

DS1

RESET

CLKOUT

CLKIN

SSOP

TOP VIEW

MAX1403

PART

MAX1403CAI

MAX1403EAI -40°C to +85°C

0°C to +70°C

TEMP RANGE PIN-PACKAGE

28 SSOP

Pin Configuration

Ordering Information

EVALUATION KIT

AVAILABLE

SPI and QSPI are trademarks of Motorola, Inc.

19-1481; Rev 1; 7/02

Summary of content (36 pages)

PAGE 1
9-1481; Rev 1; 7/02 KIT ATION EVALU E L B A AVAIL +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC This device offers three fully differential input channels that may be independently programmed with a gain between +1V/V and +128V/V. Furthermore, it can compensate an input-referred DC offset up to 117% of the selected full-scale range. These three differential channels may also be configured to operate as five pseudodifferential input channels.
PAGE 2
MAX1403 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC ABSOLUTE MAXIMUM RATINGS Maximum Current Input into Any Pin ..................................50mA Continuous Power Dissipation (TA = +70°C) 28-Pin SSOP (derate 9.52mW/°C above +70°C) ........524mW Operating Temperature Ranges MAX1403CAI .....................................................0°C to +70°C MAX1403EAI...................................................-40°C to +85°C Storage Temperature Range ............................
PAGE 3
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC (V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, VREFIN+ = +1.25V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS OFFSET DAC Offset DAC Range (Note 7) Offset DAC Resolution Offset DAC Full-Scale Error Unipolar mode -116.7 116.7 Bipolar mode -58.35 58.35 Unipolar mode 16.7 Bipolar mode 8.
PAGE 4
MAX1403 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC ELECTRICAL CHARACTERISTICS (continued) (V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, VREFIN+ = +1.25V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL AIN and REFIN Input Sampling Frequency fS REFIN+ - REFIN- Voltage (Note 14) CONDITIONS MIN TYP MAX (Table 15) ±5% for specified performance; functional with lower VREF UNITS Hz 1.
PAGE 5
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC (V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, VREFIN+ = +1.25V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG POWER-SUPPLY CURRENT (Measured with digital inputs at either DGND or VDD, external CLKIN, burn-out and transducer excitation currents disabled, X2CLK = 0, CLK = 0 for 1.024MHz, CLK = 1 for 2.4576MHz.
PAGE 6
MAX1403 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC ELECTRICAL CHARACTERISTICS (continued) (V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, VREFIN+ = +1.25V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER DISSIPATION (V+ = VDD = +3.3V, digital inputs = 0 or VDD, external CLKIN, burn-out and transducer excitation currents disabled, X2CLK = 0, CLK = 0 for 1.
PAGE 7
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC MAX1403 Note 16: The burn-out currents require a 500mV overhead between the analog input voltage and both V+ and AGND to operate correctly. Note 17: Measured at DC in the selected passband. PSR at 50Hz will exceed 120dB with filter notches of 25Hz or 50Hz and FAST bit = 0. PSR at 60Hz will exceed 120dB with filter notches of 20Hz or 60Hz and FAST bit = 0. Note 18: PSR depends on gain. For a gain of +1V/V, PSR is 70dB typical.
PAGE 8
MAX1403 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC TIMING CHARACTERISTICS (continued) (V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, AGND = DGND, fCLKIN = 2.4576MHz, input logic 0 = 0V, logic 1 = VDD, TA = TMIN to TMAX, unless otherwise noted.
PAGE 9
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC 100 V+ = +3.3V 0 0.5 1.0 1.5 2.0 2.5 3.0 INL (ppm) 0 0 -5 -5 -10 -10 -15 -1.0 3.5 -0.5 0 0.5 -1.0 1.0 -0.5 0 0.5 1.0 COMPLIANCE VOLTAGE (V) DIFFERENTIAL INPUT VOLTAGE (V) DIFFERENTIAL INPUT VOLTAGE (V) VDD SUPPLY CURRENT vs. TEMPERATURE (20sps OUTPUT DATA RATE UNBUFFERED) VDD SUPPLY CURRENT vs. TEMPERATURE (60sps OUTPUT DATA RATE UNBUFFERED) VDD SUPPLY CURRENT vs.
PAGE 10
Typical Operating Characteristics (continued) (V+ = +3V, VDD = +3V, VREFIN+ = +1.25V, REFIN- = AGND, fCLKIN = 2.4576MHz, transducer excitation currents disabled, TA = +25°C, unless otherwise noted.) VDD SUPPLY CURRENT vs. TEMPERATURE (240sps OUTPUT DATA RATE UNBUFFERED) 300 250 200 150 100 500 400 300 200 100 VDD = +3.6V (NOTE 30) 50 MAX1403 toc11 350 600 VDD = +3.6V (NOTE 30) 0 0 -50 -25 0 25 50 75 -50 100 -25 0 25 50 75 100 TEMPERATURE (°C) V+ SUPPLY CURRENT vs.
PAGE 11
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC PIN NAME FUNCTION 1 CLKIN Clock Input. A crystal can be connected across CLKIN and CLKOUT. Alternatively, drive CLKIN with a CMOS-compatible clock at a nominal frequency of 2.4576MHz or 1.024MHz, and leave CLKOUT unconnected. Frequencies of 4.9152MHz and 2.048MHz may be used if the X2CLK control bit is set to 1. 2 CLKOUT Clock Output. When deriving the master clock from a crystal, connect the crystal between CLKIN and CLKOUT.
PAGE 12
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC MAX1403 Pin Description (continued) PIN NAME FUNCTION 19 REFIN- Negative Differential Reference Input. Bias REFIN- between V+ and AGND, provided that REFIN+ is more positive than REFIN-. 20 REFIN+ Positive Differential Reference Input. Bias REFIN+ between V+ and AGND, provided that REFIN+ is more positive than REFIN-. CALOFF- Negative Offset Calibration Input. Used for system offset calibration.
PAGE 13
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Circuit Description The MAX1403 is a low-power, multichannel, serial-output, sigma-delta ADC designed for applications with a wide dynamic range, such as weigh scales and pressure transducers. The functional block diagram in Figure 2 contains a switching network, a modulator, a PGA, two buffers, an oscillator, an on-chip digital filter, two matched transducer excitation current sources, and a bidirectional serial communications port.
PAGE 14
MAX1403 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC The MAX1403 can be configured to sequentially scan all signal inputs and to transmit the results through the serial interface with minimum communications overhead. The output word contains a channel identification tag to indicate the source of each conversion result. Serial Digital Interface The serial digital interface provides access to eight onchip registers (Figure 3).
PAGE 15
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Data-Ready Signal (DRDY bit true or INT = low) The data-ready signal indicates that new data may be read from the 24-bit data register. After the end of a successful data register read, the data-ready signal becomes false. If a new measurement completes before the data is read, the data-ready signal becomes false. The data-ready signal becomes true again when new data is available in the data register.
PAGE 16
MAX1403 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC are held in reset, inhibiting normal self-timed operation. This bit may be used to convert on command to minimize the settling time to valid output data, or to synchronize operation of a number of MAX1403s. FSYNC does not reset the serial interface or the 0/DRDY flag. To clear the 0/DRDY flag while FSYNC is active, simply read the data register. Global Setup Register 1 A1, A0: (Default = 0, 0) Channel-Selection Control Bits.
PAGE 17
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC BOUT: (Default = 0) Burn-Out Current Bit. Setting BOUT = 1 connects 100nA current sources to the selected analog input channel. This mode is used to check that a transducer has not burned out or opened circuit. The burn-out current source must be turned off (BOUT = 0) before measurement to ensure best linearity. IOUT: (Default = 0) The IOUT bit controls the Transducer Excitation Currents.
PAGE 18
MAX1403 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Table 4.
PAGE 19
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC mapped to the correct output range. Note that U/B must be set before a conversion is performed; it will not affect any data already held in the output register. CALGAIN and CALOFF When not in scan mode (SCAN = 0), A1 and A0 select which transfer function applies to CALGAIN and CALOFF. In scan mode (SCAN = 1), CALGAIN and CALOFF are always mapped to transfer-function register 3.
PAGE 20
MAX1403 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Table 8.
PAGE 21
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC SCAN DIFF A1 A0 CHANNEL TRANSFERFUNCTION REGISTER 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 X X X X X X X X X X X X 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X 1 CALGAIN+–CALGAINCALGAIN+–CALGAINCALGAIN+–CALGAINCALGAIN+–CALGAINCALGAIN+–CALGAINCALGAIN+–CALGAINCALGAIN+–CALGAIN- 1 1 2 2 1 2 3 Do Not Use AIN1–AIN6 AIN2–AIN6 AIN3–AIN6 AIN4–AIN6 AIN5–AIN6 CALOFF+–CALOFFCALGAIN+–C
PAGE 22
MAX1403 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC channels. Table 12 shows the channel configurations available for both operating modes. Table 11. Channel ID Tag Codes CID2 0 CID1 0 CID0 0 CHANNEL AIN1–AIN6 0 0 1 AIN2–AIN6 0 1 0 AIN3–AIN6 0 1 1 AIN4–AIN6 1 0 0 AIN1–AIN2 1 0 1 AIN3–AIN4 1 1 0 AIN5–AIN6 1 1 1 Calibration DS1, DS0: The status of the auxiliary data input pins.
PAGE 23
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC REXT RMUX CEXT Dynamic Input Impedance at the Channel Selection Network When used in unbuffered mode (BUFF = 0), the analog inputs present a dynamic load to the driving circuitry. The size of the sampling capacitor and the input sampling frequency (Figure 5) determine the dynamic load seen by the driving circuitry. The MAX1403 samples at a constant rate for all gain settings.
PAGE 24
MAX1403 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Table 13c. REXT, CEXT Values for Less than 16-Bit Gain Error in Unbuffered (BUFF = 0) Mode—4x Modulator Sampling Frequency (MF1, MF0 = 10 ); X2CLK = 0; CLKIN = 2.4576MHz EXTERNAL RESISTANCE, REXT (kΩ) PGA GAIN CEXT = 0pF CEXT = 50pF CEXT = 100pF CEXT = 500pF CEXT = 1000pF CEXT = 5000pF 1 8.3 3.7 2.4 0.72 0.40 0.11 2 8.3 3.7 2.4 0.72 0.40 0.11 4 6.2 3.2 2.2 0.67 0.38 0.10 8, 16, 32, 64, 128 4.1 2.
PAGE 25
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC PGA GAIN EXTERNAL RESISTANCE, REXT (kΩ) CEXT = 0pF CEXT = 50pF CEXT = 100pF CEXT = 500pF CEXT = 1000pF CEXT = 5000pF 1 10 10 10 10 10 10 2 10 10 10 10 10 10 4 10 10 10 10 10 10 8 10 10 10 10 10 10 16 10 10 10 10 10 10 32 10 10 10 10 10 10 64 10 10 10 10 10 10 128 10 10 10 10 10 10 Reference Input The MAX1403 is optimized for ratiometric measurements and includes a fully differ
PAGE 26
MAX1403 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Table 15. Modulator Operating Frequency, Sampling Frequency, and 16-Bit Data Output Rates CLKIN FREQUENCY, fCLKIN (MHz) MODULATOR FREQUENCY, fM (kHz) AVAILABLE OUTPUT DATA RATES AT 16-BIT ACCURACY (sps) 20, 25 CLK MF1 MF0 AIN/REFIN SAMPLING FREQUENCY, fS (kHz) 2.048 0 0 0 16 8 2.048 0 0 1 32 16 40, 50 2.048 0 1 0 64 32 80, 100 160, 200 X2CLK = 0 DEFAULT X2CLK = 1 1.024 1.024 1.024 1.024 2.
PAGE 27
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC OUTPUT DATA RATE (sps) -3dB FREQ. (Hz) x1 x2 x4 x8 x16 x32 x64 x128 MF1:MF0 = 0 50 13.1 5.72 3.21 2.10 1.41 1.42 1.44 1.38 1.34 FS1:FS0 = 0 60 15.7 6.29 3.57 2.30 1.55 1.61 1.56 1.49 1.56 FS1:FS0 = 1 300 78.6 80.6 39.8 19.3 10.2 6.14 4.25 3.03 3.52 FS1:FS0 = 2 600 157.2 436 225 116 57.1 28.8 15.0 8.70 5.
PAGE 28
Clock Oscillator The clock oscillator may be used with an external crystal (or resonator) connected between CLKIN and CLKOUT, or may be driven directly by an external oscillator at CLKIN with CLKOUT left unconnected. In normal operating mode, the MAX1403 is specified for operation with CLKIN at either 1.024MHz (CLK = 0) or 2.4576MHz (CLK = 1, default).
PAGE 29
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC The SINC1 function results in a faster settling response while retaining the same frequency response notches as the default SINC3 filter. This allows the filter to settle faster at the expense of resolution and quantization noise. The SINC1 filter settles in one data word period. With 60Hz notches (60Hz data rate), the settling time would be 1 / 60Hz or 16.7ms, whereas the SINC3 filter would settle in 3 / 60Hz or 50ms.
PAGE 30
Analog Filtering Calibration Channels The digital filter does not provide any rejection close to the harmonics of the modulator sample frequency. However, due to the high oversampling ratio of the MAX1403, these bands occupy only a small fraction of the spectrum and most broadband noise is filtered. Therefore, the analog filtering requirements in front of the MAX1403 are considerably reduced compared to a conventional converter with no on-chip filtering.
PAGE 31
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC MAX1403 /* Assumptions: ** The MAX140X's CS pin is tied to ground ** The MAX140X's INT pin drives a falling-edge-triggered interrupt ** MAX140X's DIN is driven by MOSI, DOUT drives MISO, and SCLK drives SCLK */ /* Low-level function to write 8 bits using 68HC11 SPI */ void WriteByte (BYTE x) { /* System-dependent: write to SPI hardware and wait until it is finished */ HC11_SPDR = x; while (HC11_SPSR & HC11_SPSR_SPIF) { /* idle loop */ } }
PAGE 32
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC MAX1403 Bit-Banging Interface (80C51, PIC16C54) VDD RESET 8051 P3.0 DOUT DIN P3.1 SCLK CS MAX1403 Any microcontroller can use general-purpose I/O pins to interface to the MAX1403. If a bidirectional or opendrain I/O pin is available, reduce the interface pin count by connecting DIN to DOUT (Figure 13). Listing 2 shows how to emulate the SPI in software. Use the same initialization routine shown in Listing 1.
PAGE 33
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Temperature Measurement Figure 15 shows a connection from a thermocouple to the MAX1403. In this application, the MAX1403 is operated in its buffered mode to allow large decoupling capacitors on the front end. These decoupling capacitors eliminate any noise pickup from the thermocouple leads. When the MAX1403 is operated in buffered mode, it has a reduced common-mode range.
PAGE 34
Loop-Powered, 4–20mA Transmitters Low-power, single-supply operation, and easy interfacing with optocouplers make the MAX1403 ideal for loop-powered 4–20mA transmitters. Loop-powered transmitters draw their power from the 4–20mA loop, limiting the transmitter circuitry to a current budget of 4mA. Tolerances in the loop further limit this current budget to 3.5mA. Since the MAX1403 consumes only 250µA, a total of 3.25mA remains to power the remaining transmitter circuitry.
PAGE 35
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC MAX1403 +3V V+ VDD 200µA V+ REFIN- REFIN+ VDD 200µA OUT1 OUT2 MAX1403 12.5k REFIN+ MODULATOR AIN1 RL1 RTD AIN2 MODULATOR RREF PGA REFIN- GAIN = 1 TO 128 200µA OUT2 OUT1 RL2 200µA AGND MAX1403 RL3 AIN1 DGND RTD PGA Figure 17.
PAGE 36
Shield fast switching signals, such as clocks, with digital ground to avoid radiating noise to other sections of the board. Avoid running clock signals near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough on the board. A microstrip technique is best but is not always possible with double-sided boards.