Datasheet

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General Description

The MAX1415/MAX1416 low-power, 2-channel, serial-

output analog-to-digital converters (ADCs) use a sigma-

delta modulator with a digital filter to achieve 16-bit

resolution with no missing codes. These ADCs are pin-

compatible upgrades to the MX7705/AD7705. The

MAX1415/MAX1416 feature an internal oscillator (1MHz

or 2.4576MHz), an on-chip input buffer, and a program-

mable gain amplifier (PGA). The devices offer an SPI™-/

QSPI™-/MICROWIRE™-compatible serial interface.

The MAX1415 requires a single 2.7V to 3.6V supply, and

the MAX1416 requires a single 4.75V to 5.25V supply.

The operating supply current is 400µA (max) with a 3V

supply. Power-down mode reduces the supply current to

2µA (typ). When operating with a supply of 3V, the power

dissipation is less than 1.44mW, making the MAX1415

ideal for battery-powered applications.

Self-calibration and system calibration allow the

MAX1415/MAX1416 to correct for gain and offset errors.

Excellent DC performance (±0.0015% FSR INL) and low

noise (700nV in unbuffered mode) make the MAX1415/

MAX1416 ideal for measuring low-frequency signals with

a wide dynamic range. These devices accept fully differ-

ential bipolar/unipolar inputs. An internal input buffer

allows for input signals with high source impedances. An

on-chip digital filter, with a programmable cutoff and out-

put data rate, processes the output of the sigma-delta

modulator. The first notch frequency of the digital filter is

chosen to provide 150dB rejection of common-mode

50Hz or 60Hz noise and 98dB rejection of normal-mode

50Hz or 60Hz noise. A PGA and digital filtering allow sig-

nals to be directly acquired with little or no signal-condi-

tioning requirements.

The MAX1415/MAX1416 are available in 16-pin PDIP,

SO, and TSSOP packages.

Applications

Industrial Instruments

Weigh Scales

Strain-Gauge Measurements

Loop-Powered Systems

Flow and Gas Meters

Medical Instrumentation

Pressure Transducers

Thermocouple Measurements

RTD Measurements

Features

♦ 16-Bit Sigma-Delta ADCs

♦ Two Fully Differential Input Channels

♦ 0.0015% Integral Nonlinearity with No Missing

Codes

♦ Internal Analog Input Buffers

♦ Programmable Gain Amplifier (PGA) from 1 to 128

♦ Internal Oscillator (2.4576MHz or 1MHz)

♦ Single 2.7V to 3.6V (MAX1415) or 4.75V to 5.25V

(MAX1416) Supply

♦ Low Power

1mW max, 3V Supply

2µA (typ) Power-Down Current

♦ SPI™-/QSPI™-/MICROWIRE™-Compatible 3-Wire

Serial Interface

♦ Pin Compatible with MX7705/AD7705

♦ 16-Pin PDIP, SO, and TSSOP Packages

MAX1415/MAX1416

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADCs

________________________________________________________________ Maxim Integrated Products 1

SCLK

GND

DIN

DOUT

DRDY

AIN2-

REF-

REF+

TOP VIEW

MAX1415

MAX1416

PDIP/SO/TSSOP

CLKIN

CLKOUT

AIN2+

RESET

AIN1+

AIN1-

Pin Configuration

Ordering Information

19-3163; Rev 1; 12/05

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART

TEMP

RANGE

PIN-

PACKAGE

(

)

PKG

CODE

MAX1415ENE* -45°C to +85°C 16 PDIP 3 P16-1

MAX1415EWE* -45°C to +85°C 16 Wide SO 3 W16-1

MAX1415EUE -45°C to +85°C 16 TSSOP 3 U16-1

MAX1415AENE* -45°C to +85°C 16 PDIP 3 P16-1

MAX1415AEWE* -45°C to +85°C 16 Wide SO 3 W16-1

MAX1415AEUE* -45°C to +85°C 16 TSSOP 3 U16-1

MAX1415CNE* 0°C to +70°C 16 PDIP 3 P16-1

MAX1415CWE* 0°C to +70°C 16 Wide SO 3 W16-1

MAX1415CUE* 0°C to +70°C 16 TSSOP 3 U16-1

SPI/QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

*Future product—contact factory for availability.

Ordering Information continued at end of data sheet.

Summary of content (36 pages)

PAGE 1
9-3163; Rev 1; 12/05 KIT ATION EVALU E L B AVAILA 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs Features The MAX1415/MAX1416 low-power, 2-channel, serialoutput analog-to-digital converters (ADCs) use a sigmadelta modulator with a digital filter to achieve 16-bit resolution with no missing codes. These ADCs are pincompatible upgrades to the MX7705/AD7705. The MAX1415/MAX1416 feature an internal oscillator (1MHz or 2.4576MHz), an on-chip input buffer, and a programmable gain amplifier (PGA).
PAGE 2
MAX1415/MAX1416 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V All Other Pins to GND.................................-0.3V to (VDD + 0.3V) Maximum Current Input into Any Pin ..................................50mA Continuous Power Dissipation (TA = +70°C) 16-Pin PDIP (derate 10.5mW/°C above +70°C)...........842mW 16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW 16-Pin Wide SO (derate 9.
PAGE 3
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs (VDD = 3V, GND = 0, VREF+ = 1.225V, VREF- = GND, external fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1µF, CREF- to GND = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.
PAGE 4
MAX1415/MAX1416 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs ELECTRICAL CHARACTERISTICS—MAX1415 (continued) (VDD = 3V, GND = 0, VREF+ = 1.225V, VREF- = GND, external fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1µF, CREF- to GND = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Output-Voltage High Tri-State Leakage Current Tri-State Output Capacitance SYMBOL CONDITIONS MIN DOUT and DRDY, ISOURCE = 100µA VDD 0.6V CLKOUT, ISOURCE = 10µA VDD 0.
PAGE 5
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs (VDD = 3V, GND = 0, VREF+ = 1.225V, VREF- = GND, external fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1µF, CREF- to GND = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Typical Conversion-Time Variation SYMBOL ∆tCONV CONDITIONS MIN tCONV = 1/ODR TYP MAX ±0.
PAGE 6
MAX1415/MAX1416 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs ELECTRICAL CHARACTERISTICS—MAX1416 (continued) (VDD = 5V, GND = 0, VREF+ = 2.5V, VREF- = GND, fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1µF, CREF- to GND = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.
PAGE 7
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs (VDD = 5V, GND = 0, VREF+ = 2.5V, VREF- = GND, fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1µF, CREF- to GND = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EXTERNAL REFERENCE (REF+, REF-) REF Differential Input Range REF Absolute Input Voltage VREF REF Input Capacitance REF Input Sampling Rate (Note 9) 1 3.
PAGE 8
MAX1415/MAX1416 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs ELECTRICAL CHARACTERISTICS—MAX1416 (continued) (VDD = 5V, GND = 0, VREF+ = 2.5V, VREF- = GND, fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1µF, CREF- to GND = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Power-Supply Current (Note 12) SYMBOL IDD CONDITIONS MIN TYP 0.45 Buffered, fCLKIN = 1MHz, gain = 1 to 128 0.78 Unbuffered, fCLKIN = 2.4576MHz Gain = 1 to 4 0.6 Gain = 8 to 128 0.6 Buffered, fCLKIN = 2.
PAGE 9
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs (Note 16) (Figures 8, 9) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIN to SCLK Setup Time t9 30 ns DIN to SCLK Hold Time t10 20 ns Note 1: These errors are in the order of the conversion noise shown in Tables 1 and 3. This applies after calibration at the given temperature. Note 2: Recalibration at any temperature removes these drift errors.
PAGE 10
MAX1415/MAX1416 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs Table 1. MAX1415—Output RMS Noise vs. Gain and Output Data Rate (3V) FILTER FIRST NOTCH AND OUTPUT DATA RATE (Hz) TYPICAL OUTPUT RMS NOISE (µV) -3dB FREQUENCY (Hz) GAIN 1 2 4 8 16 32 64 128 2.85 1.63 2.16 0.70 0.67 0.63 0.64 0.62 0.70 BUFFERED (fCLKIN = 1MHz) 20 5.24 25 6.55 3.46 1.92 1.13 6.05 0.75 0.73 0.70 100 26.2 48.94 26.98 11.99 0.85 3.44 2.27 1.66 1.72 200 52.4 270.91 161.33 66.19 32.64 16.
PAGE 11
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs MAX1415/MAX1416 Table 2. MAX1415—Peak-to-Peak Resolution vs. Gain and Output Data Rate (3V) FILTER FIRST NOTCH AND OUTPUT DATA RATE (Hz) TYPICAL PEAK-TO-PEAK RESOLUTION (BITS) -3dB FREQUENCY (Hz) GAIN 1 2 4 8 16 32 64 128 BUFFERED (fCLKIN = 1MHz) 20 5.24 16 16 16 16 15 14 13 12 25 6.55 16 16 16 12 15 14 13 12 100 26.2 12 12 12 16 12 12 11 11 200 52.4 10 10 10 10 10 10 10 9 20 5.
PAGE 12
MAX1415/MAX1416 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs Table 3. MAX1416—Output RMS Noise vs. Gain and Output Data Rate (5V) FILTER FIRST NOTCH AND OUTPUT DATA RATE (Hz) TYPICAL OUTPUT RMS NOISE (µV) -3dB FREQUENCY (Hz) GAIN 1 2 4 8 16 32 64 128 3.51 1.87 1.11 0.75 0.70 0.71 0.67 0.65 0.74 BUFFERED (fCLKIN = 1MHz) 20 5.24 25 6.55 4.46 2.39 1.32 0.90 0.83 0.81 0.75 100 26.2 92.29 47.60 28.62 11.60 6.40 3.70 2.34 2.30 200 52.4 552.57 295.67 105.50 69.01 35.
PAGE 13
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs MAX1415/MAX1416 Table 4. MAX1416—Peak-to-Peak Resolution vs. Gain and Output Data Rate (5V) FILTER FIRST NOTCH AND OUTPUT DATA RATE (Hz) TYPICAL PEAK-TO-PEAK RESOLUTION (BITS) -3dB FREQUENCY (Hz) GAIN 1 2 4 8 16 32 64 128 BUFFERED (fCLKIN = 1MHz) 20 5.24 16 16 16 16 16 15 14 13 25 6.55 16 16 16 16 16 15 14 13 100 26.2 12 12 12 12 12 12 12 11 200 52.4 10 10 11 10 10 10 10 9 20 5.
PAGE 14
Typical Operating Characteristics (MAX1415: VDD = 5V, VREF+ = 2.5V, VREF- = GND, TA = +25°C, unless otherwise noted.) (MAX1416: VDD = 3V, VREF+ = 1.225V, VREF- = GND, TA = +25°C, unless otherwise noted.) TYPICAL OUTPUT NOISE (MAX1416, BUFFERED MODE) RMS NOISE = 1.3µV 300 OCCURRENCE CODE READ 32770 VDD = 5V, VREF = 2.5V GAIN = 128 ODR = 60Hz 32768 32766 32764 32762 200 0.0015 MAX1415/MAX1416 toc03 32772 400 OFFSET ERROR vs. SUPPLY VOLTAGE (MAX1415) 0.
PAGE 15
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX1415) 0.5 B 0.4 C D 0.3 0.65 MAX1415/MAX1416 toc10 SUPPLY CURRENT (mA) A SUPPLY CURRENT (mA) MAX1415/MAX1416 toc09 0.6 SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX1416) A B 0.55 0.45 C D 0.35 E E 0.2 0.25 2.70 2.85 3.00 3.15 3.30 3.45 3.60 4.75 4.85 4.95 5.05 5.15 5.25 SUPPLY VOLTAGE (V) A: BUFFERED MODE B: BUFFERED MODE C: BUFFERED MODE fCLKIN = 2.4576MHz, fCLKIN = 2.
PAGE 16
Typical Operating Characteristics (continued) (MAX1415: VDD = 5V, VREF+ = 2.5V, VREF- = GND, TA = +25°C, unless otherwise noted.) (MAX1416: VDD = 3V, VREF+ = 1.225V, VREF- = GND, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. fCLKIN (MAX1415) 0.4 C D 0.3 MAX1415/MAX1416 toc14 0.5 0.65 B SUPPLY CURRENT (mA) B A SUPPLY CURRENT vs. fCLKIN (MAX1416) MAX1415/MAX1416 toc13 A 0.55 0.45 C D 0.35 E E 0.2 0.25 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.
PAGE 17
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs 60 40 20 0 POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE 180 160 140 120 300 250 2.85 3.00 3.15 3.30 3.45 3.60 MAX1415 VDD = 5V 200 150 MAX1416 VDD = 3V 100 100 2.70 50 0 4.75 SUPPLY VOLTAGE (V) 4.85 4.95 5.05 5.15 5.
PAGE 18
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs MAX1415/MAX1416 Pin Description 18 PIN NAME FUNCTION 1 SCLK Serial Clock Input. Apply an external serial clock to transfer data to and from the device at data rates up to 5MHz. 2 CLKIN Clock Input. Connect a crystal/resonator between CLKIN and CLKOUT, or drive CLKIN externally with a CMOS-compatible clock source. Connect CLKIN to GND when using the internal oscillator. 3 CLKOUT Clock Output. Connect a crystal/resonator between CLKIN and CLKOUT.
PAGE 19
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs CLKIN CLOCK GENERATOR BUFFER CLKOUT MAX1415 MAX1416 AIN1+ AIN1AIN2+ MUX S1 S2 PGA 2nd-ORDER SIGMA-DELTA MODULATOR DIGITAL FILTER VDD GND AIN2BUFFER S1 AND S2 ARE OPEN IN BUFFERED MODE AND CLOSED IN UNBUFFERED MODE REF+ SERIAL INTERFACE, REGISTERS, AND CONTROL CS SCLK DIN DOUT DRDY RESET REF- Detailed Description The MAX1415/MAX1416 low-power, 2-channel serial output ADCs use a sigma-delta modulator with a digital filter to achieve 16-bit resol
PAGE 20
To minimize gain errors in unbuffered mode, select a source impedance less than the maximum values shown in Figures 2 and 3. These are the maximum external resistance/capacitance combinations allowed before gain errors greater than 1 LSB are introduced in unbuffered mode. Enable the internal input buffer for a high source impedance. This isolates the inputs from the sampling capacitor and reduces the sampling-related gain error.
PAGE 21
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs MAX1415/MAX1416 Table 5. Input Sampling Capacitor vs. Gain 2 7.5 4 15 8–128 30 Increasing the gain increases the resolution of the ADC (LSB size decreases), but reduces the differential input voltage range. Calculate 1 LSB in unipolar mode using the following equation: 1111 1111 1111 1101 1111 1111 1111 1100 1 LSB = 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 0 where: VREF = VREF+ - VREF-.
PAGE 22
Modulator The MAX1415/MAX1416 perform analog-to-digital conversions using a single-bit, 2nd-order, switched-capacitor, sigma-delta modulator. The sigma-delta modulator converts the input signal into a digital pulse train whose average duty cycle represents the digitized signal information. A single comparator within the modulator quantizes the input signal at a much higher sample rate than the bandwidth of the input.
PAGE 23
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs Internal-Clock Startup Time The internal clock requires time to stabilize during power-on reset. This startup time is dependent on the internal-clock frequency (see the Typical Operating Characteristics section). The typical startup time for the internal oscillator is less than 35µs, while the external oscillator startup time when using a crystal or resonator is in the order of milliseconds.
PAGE 24
MAX1415/MAX1416 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs DIN Communications Register The byte-wide communications register is bidirectional so it can be written and read. The byte written to the communications register indicates the next read or write operation on the selected register, the power-down mode, and the analog input channel (see Table 6). The DRDY bit indicates the conversion status.
PAGE 25
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs (MSB) FUNCTION (LSB) COMMUNICATION START/DATA READY Name REGISTER SELECT READ/WRITE SELECT POWER-DOWN MODE CHANNEL SELECT 0/DRDY RS2 RS1 RS0 R/W PD CH1 CH0 0 0 0 0 0 0 0 0 Defaults Table 7.
PAGE 26
MAX1415/MAX1416 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs Table 10. Operating-Mode Selection MD1 MD0 0 0 Normal Mode. Use this mode to perform normal conversions on the selected analog input channel. 1 Self-Calibration Mode. This mode performs self-calibration on the selected channel determined from CH0 and CH1 selection bits in the communications register (Table 6). Upon completion of self-calibration, the device returns to normal mode with MD1, MD0 returning to 0, 0.
PAGE 27
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs FS1, FS0: (Default = 0, 1) Filter-Selection Bits. These bits, in addition to the CLK bit, determine the output data rate and the digital filter cutoff frequency. See Table 13 for FS1 and FS0 settings. Recalibrate when the filter characteristics are changed. Offset and Gain-Calibration Registers The MAX1415/MAX1416 contain one offset register and one gain register for each input channel. Each register is 24 bits wide and can be written and read.
PAGE 28
MAX1415/MAX1416 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs Write to the calibration registers in normal mode only. After writing to the calibration registers, the devices implement the new offset and gain-register calibration coefficients at the beginning of a new acquisition. To ensure the results are valid, discard the first conversion result after writing to the calibration registers.
PAGE 29
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs MAX1415/MAX1416 POWER-ON RESET INITIALIZE µC/µP SERIAL PORT WRITE TO THE COMMUNICATIONS REGISTER. SELECT CHANNEL 1 AND SET NEXT OPERATION AS A WRITE TO THE CLOCK REGISTER (0x20) WRITE TO THE CLOCK REGISTER. ENABLE INTERNAL CLOCK. SET CLOCK FREQUENCY TO 2.4576MHz. SELECT OUTPUT UPDATE RATE OF 60Hz. (0xA5) WRITE TO THE COMMUNICATIONS REGISTER. SET NEXT OPERATION AS A WRITE TO THE SETUP REGISTER. (0x10) WRITE TO THE SETUP REGISTER.
PAGE 30
MAX1415/MAX1416 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs Using FSYNC When FSYNC = 1, the digital filter and analog modulator are in a reset state, inhibiting normal operation. Set FSYNC = 0 to begin calibration or conversion. When configured for normal operation (MD1 and MD0 set to 0), DRDY goes low 3 x 1/output data rate after FSYNC goes low to indicate that the new conversion result is ready to be read from the data register. DRDY returns high when a read operation on the data register is complete.
PAGE 31
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs The DRDY output goes high at the start of calibration and falls low when the calibration is complete and the next conversion result is valid in the data register. The total time for self-calibration and one conversion (time until DRDY goes low) is 9 x 1/output data rate.
PAGE 32
MAX1415/MAX1416 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs Applications Information VDD Applications Examples Strain-Gauge Measurement Connect the differential inputs of the MAX1415/ MAX1416 to the bridge network of the strain gauge. In Figure 12, the analog positive supply voltage powers the bridge network and the MAX1415/MAX1416 along with the reference voltage in a ratiometric configuration.
PAGE 33
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs ISO 3V/5V +VCC VDD 2kΩ VCC Bipolar Negative Full-Scale Error For the ideal transfer curve, the code edge transition that causes a negative full-scale transition to occur is 0.5 LSB above negative full scale. The negative full-scale error is the difference between the ideal value at this code transition and the actual measured value at this code transition.
PAGE 34
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) PDIPN.
PAGE 35
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs E DIM A A1 B C e E H L H MAX MIN 0.104 0.093 0.012 0.004 0.019 0.014 0.013 0.009 0.050 0.299 0.291 0.394 0.419 0.050 0.016 SOICW.EPS INCHES N MILLIMETERS MIN 2.35 0.10 0.35 0.23 MAX 2.65 0.30 0.49 0.32 1.27 7.40 7.60 10.00 10.65 0.40 1.27 VARIATIONS: 1 INCHES TOP VIEW DIM D D D D D D A B e FRONT VIEW MIN 0.398 0.447 0.496 0.598 0.697 MAX 0.413 0.463 0.512 0.614 0.713 MILLIMETERS MIN 10.10 11.35 12.60 15.20 17.70 MAX 10.50 11.75 13.00 15.
PAGE 36
Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) TSSOP4.40mm.EPS MAX1415/MAX1416 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs PACKAGE OUTLINE, TSSOP 4.40mm BODY 21-0066 G 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.