9-3005; Rev 3; 7/07 Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs The MAX5290–MAX5295 dual, 12-/10-/8-bit, voltageoutput digital-to-analog converters (DACs) offer buffered outputs and a 3µs maximum settling time at the 12-bit level. The DACs operate from a 2.7V to 5.25V analog supply and a separate 1.8V to 3.6V digital supply. The 20MHz 3-wire serial interface is compatible with SPI™, QSPI™, MICROWIRE™, and digital signal processor (DSP) protocol applications.
MAX5290–MAX5295 Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs ABSOLUTE MAXIMUM RATINGS AVDD to DVDD ........................................................................±6V AGND to DGND ..................................................................±0.3V AVDD to AGND, DGND.............................................-0.3V to +6V DVDD to AGND, DGND ............................................-0.3V to +6V FB_, OUT_, REF to AGND ........-0.3V to the lower of (AVDD + 0.
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs MAX5290–MAX5295 ELECTRICAL CHARACTERISTICS (continued) (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL Power-Supply Rejection Ratio PSRR CONDITIONS MIN Full-scale output, AVDD = 2.7V to 3.
MAX5290–MAX5295 Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs ELECTRICAL CHARACTERISTICS (continued) (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs (AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS Analog Supply Voltage Range AVDD 2.70 5.25 V Digital Supply Voltage Range DVDD 1.8 AVDD V 0.55 0.8 mA 0.9 1.2 mA Unity gain 0.85 2 Force sense 1.2 2 0.5 1.
MAX5290–MAX5295 Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V Logic) (Figure 1) (continued) (DVDD = 2.7V to 5.25V, DGND = 0, TA = TMIN to TMAX, unless otherwise noted.
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs (DVDD = 1.8V to 5.25V, DGND = 0, TA = TMIN to TMAX, unless otherwise noted.
MAX5290–MAX5295 Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V Logic) (Figure 2) (continued) (DVDD = 2.7V to 5.25V, DGND = 0, TA = TMIN to TMAX, unless otherwise noted.
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs (DVDD = 1.8V to 5.25V, DGND = 0, TA = TMIN to TMAX, unless otherwise noted.
Typical Operating Characteristics (AVDD = DVDD = 3V, VREF = 2.5V, RL = 10kΩ, CL = 100pF, speed mode = FAST, PU = floating, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (MAX5291A) 0.2 0.10 0.05 2 -0.4 -0.05 INL (LSB) INL (LSB) -0.10 -0.15 1 0 -1 -0.20 -2 -0.25 -0.8 0 1000 2000 3000 4000 -0.30 -3 -0.35 -4 4096 0 1000 INPUT CODE 3000 4000 4096 0 1024 INPUT CODE INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (10-BIT) UNITY GAIN 0.75 0.
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs UNITY GAIN B-GRADE 0.50 0.45 0.40 0.1 0 0.35 INL (LSB) DNL (LSB) INL (LSB) 2 UNITY GAIN MAX5290 toc12 0.2 MAX5290 toc10 4 INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE (MAX5290A) DIFFERENTIAL NONLINEARITY vs. TEMPERATURE (12-BIT) MAX5290 toc11 INTEGRAL NONLINEARITY vs. TEMPERATURE (12-BIT) 0 0.30 0.25 0.20 0.15 -2 -0.1 -4 -0.2 0.10 0.05 35 85 60 -15 35 OFFSET ERROR vs. TEMPERATURE (A-GRADE) OFFSET ERROR (mV) 0.
Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. DIGITAL INPUT CODE (UNITY GAIN) 0.5 0.4 SLOW MODE 12-BIT NO LOAD 0.1 0 MAX5290 toc20 0.4 0.3 1024 2048 3072 I = IAVDD + IDVDD AVDD = DVDD NO LOAD 0.2 0.1 95 90 85 UNITY GAIN 80 FORCE SENSE 75 70 65 AVDD = DVDD I = IAVDD + IDVDD NO LOAD 60 55 3.1 3.5 3.9 4.3 4.7 5.1 4.3 5.1 4 3 B-GRADE UNITY GAIN: 1 LSB = 1mV FORCE SENSE: 1 LSB = 0.5mV 2 UNITY GAIN 1 0 -1 FORCE SENSE -2 -3 -4 3.1 3.5 3.
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs REFERENCE INPUT BANDWIDTH SETTLING TIME NEGATIVE MAX5290 toc29 MAX5290 toc28 5 MAX5290 toc30 SETTLING TIME POSITIVE FULL-SCALE TRANSITION FULL-SCALE TRANSITION 0 OUT_ 2V/div -5 GAIN (dB) OUT_ 2V/div CS 2V/div CS 2V/div -10 -15 -20 VREF = 0.1VP-P AT 4.
MAX5290–MAX5295 Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs Pin Description PIN MAX5290 MAX5292 MAX5294 MAX5291 MAX5293 MAX5295 NAME FUNCTION THIN QFN TSSOP THIN QFN TSSOP 1 2 1 3 DSP Clock Enable. Connect DSP to DVDD at power-up to transfer data on the rising edge of SCLK. Connect DSP to DGND at power-up to transfer data on the falling edge of SCLK.
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs DVDD AVDD CS SCLK DIN DSP AGND DGND SERIAL INTERFACE CONTROL MAX5290 MAX5292 MAX5294 16-BIT SHIFT REGISTER MUX UPIO1 UPIO2 PU UPIO1 AND UPIO2 LOGIC DOUT REGISTER POWER-DOWN LOGIC AND REGISTER DECODE CONTROL OUTA INPUT REGISTER DAC REGISTER DAC A REF OUTB INPUT REGISTER DAC REGISTER DAC B ______________________________________________________________________________________ 15 MAX5290–MAX5295 Functional Diagrams
MAX5290–MAX5295 Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs Functional Diagrams (continued) DVDD AVDD CS SCLK DIN DSP AGND DGND SERIAL INTERFACE CONTROL MAX5291 MAX5293 MAX5295 16-BIT SHIFT REGISTER MUX UPIO1 UPIO2 PU UPIO1 AND UPIO2 LOGIC DOUT REGISTER POWER-DOWN LOGIC AND REGISTER FBA DECODE CONTROL OUTA INPUT REGISTER DAC REGISTER DAC A REF FBB OUTB INPUT REGISTER 16 DAC REGISTER DAC B ________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs The MAX5290–MAX5295 dual, 12-/10-/8-bit, voltageoutput digital-to-analog converters (DACs) offer buffered outputs and a 3µs maximum settling time at the 12-bit level. The DACs operate from a single 2.7V to 5.25V analog supply and a separate 1.8V to AVDD digital supply. The MAX5290–MAX5295 include an input register and DAC register for each channel and a 16-bit data-in/data-out shift register.
MAX5290–MAX5295 Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs Table 1. Serial Write Data Format MSB 16 BITS OF SERIAL DATA CONTROL BITS C3 C2 C1 LSB DATA BITS C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 tCH SCLK tCL tDS DIN C3 tCS0 C2 C1 D0 tCSH tDH tCSS CS tCSW tCS1 tDO1 DOUTDC1* DOUT VALID tDO2 DOUTDC0 OR DOUTRB* DOUT VALID *UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT).
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs Loading Input and DAC Registers The MAX5290–MAX5295 contain a 16-bit shift register that is followed by a 12-bit input register and a 12-bit DAC register for each channel (see the Functional Diagrams). Tables 3, 4, and 5 highlight a few of the commands for the loading of the input and DAC registers. See Table 2a for all DAC programming commands.
C2 C1 C0 CONTROL BITS C3 D1 D1 D9 D8 0 0 0 0 0 0 0 1 1 1 1 1 1 DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ______________________________________________________________________________________ 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X D11 D10 D11 D10 X X X X X X D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D11 D10 D9 D9 X X X X X X D9 D9 D9
C3 1 1 1 C1 1 1 X DIN DOUTRB X 1 1 X 0 0 0 1 1 X DIN DOUTRB X 1 1 X 0 0 1 1 X DIN DOUTRB X 1 1 X 0 0 X 1 1 X 1 1 X = Don’t care.
C2 C1 C0 D1 CONTROL BITS C3 D1 D9 X DOUTRB X 1 1 1 1 1 DIN DIN DIN DIN 1 1 1 1 1 1 1 1 1 1 X 1 1 1 1 1 1 X 1 1 1 1 1 1 X 0 1 1 1 0 0 X 0 1 1 0 1 0 X 1 C2 C1 C0 CONTROL BITS C3 D27 D26 D25 ______________________________________________________________________________________ X 1 X DOUTRB DIN DOUTRB X 1 X 1 X 1 X 1 X 1 X 1 X 0 X 0 X 1 X 1 X 1 X 0 X X X X D23 1 D23 1 D24 D23 D22 1 D22 1 D22 1 X X
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs DAC Programming Examples: To load input register A from the shift register, leaving DAC register A unchanged (DAC output unchanged), use the command in Table 3. The MAX5290–MAX5295 can load DAC register A from the shift register, leaving input register A unchanged, by using the command in Table 4. To load input register A and DAC register A simultaneously from the shift register, use the command in Table 5.
MAX5290–MAX5295 Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs Shutdown-Mode Bits (PDA0, PDA1, PDB0, PDB1) Use the shutdown-mode bits to shut down each DAC independently. Set PD_0 and PD_1 according to Table 8 to select the shutdown mode for DAC_, where “_” is replaced with A or B depending on the selected channel. The three possible states for unity-gain versions are 1) normal operation, 2) shutdown with 1kΩ output impedance, and 3) shutdown with 100kΩ output impedance.
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs Settling-Time-Mode Write Example: To configure DACA into FAST mode and DACB into SLOW mode, use the command in Table 13. To read back the settling-time-mode bits, use the command in Table 14. CPOL and CPHA Control Bits The CPOL and CPHA control bits of the MAX5290–MAX5295 are defined the same as the CPOL and CPHA bits in the SPI standard.
MAX5290–MAX5295 Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs and CPHA = 1 or set CPOL = 1 and CPHA = 0 for DSP and SPI applications requiring the clocking of data in on the falling edge of SCLK (refer to the Programmer’s Handbook and see Table 15 for details). At power-up, if DSP = DVDD, the default value of CPHA is zero and if DSP = DGND, the default value of CPHA is one. The default value of CPOL is zero at power-up. To write to the CPOL and CPHA bits, use the command in Table 16.
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs Table 22 lists the possible configurations for UPIO1 and UPIO2. UPIO1 and UPIO2 use the selected function when configured by the UP3–UP0 configuration bits. LDAC LDAC controls loading of the DAC registers. When LDAC is high, the DAC registers are latched, and any change in the input registers does not affect the contents of the DAC registers or the DAC outputs.
MAX5290–MAX5295 Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs SET, MID, CLR The SET, MID, and CLR signals force the DAC outputs to full scale, midscale, or zero scale (Figure 5). These signals cannot be active at the same time. The active-low SET input forces the DAC outputs to full scale when SET is low. When SET is high, the DAC outputs follow the data in the DAC registers. The active-low MID input forces the DAC outputs to midscale when MID is low.
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs 3) Detect whether or not a rising edge has occurred since the last read or reset (LR1 and LR2). RTP1, LF1, and LR1 represent the data read from UPIO1. RTP2, LF2, and LR2 represent the data read from UPIO2. To issue a read command for the UPIO configured as GPI, use the command in Table 23. Once the command is issued, RTP1 and RTP2 provide the real-time status (0 or 1) of the inputs at UPIO1 or UPIO2, respectively, at the time of the read.
MAX5290–MAX5295 Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs Applications Information Unipolar Output Figure 7 shows the unity gain of the MAX5290 in a unipolar output configuration. Table 24 lists the unipolar output codes. Bipolar Output The MAX5290 outputs can be configured for bipolar operation, as shown in Figure 8.
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs AVDD DVDD 0.1µF VREF AVDD niques, such as a multilayer board with a low-inductance ground plane. Wire-wrapped boards and sockets are not recommended. For optimum system performance, use printed circuit (PC) boards with separate analog and digital ground planes. Connect the two ground planes together at the low-impedance powersupply source. Using separate power supplies for AVDD and DVDD improves noise immunity.
Pin Configurations TOP VIEW 14 UPIO2 UPIO1 1 DSP 2 13 PU DIN 3 12 OUTA MAX5290 MAX5292 MAX5294 CS 4 SCLK 5 UPIO2 1 16 PU UPIO1 2 15 OUTA CS 5 10 OUTB DVDD 6 9 AVDD DGND 7 8 AGND MAX5291 MAX5293 MAX5295 DIN 4 13 REF 12 FBB SCLK 6 11 OUTB DVDD 7 10 AVDD DGND 8 9 AGND 16 TSSOP UPIO1 UPIO2 PU N.C. UPIO1 UPIO2 PU OUTA 14 TSSOP 16 15 14 13 16 15 14 13 DSP 1 12 OUTA DSP 1 12 FBA DIN 2 11 N.C.
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs TSSOP4.40mm.EPS PACKAGE OUTLINE, TSSOP 4.40mm BODY 21-0066 I 1 1 ______________________________________________________________________________________ 33 MAX5290–MAX5295 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.
Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS MAX5290–MAX5295 Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 F 2 2 Revision History Pages changed at Rev 3: 1, 6–9, 33, 34, 35 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
