Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - DA converter (DAC) TQFN 40 EP

General Description

The MAX5854 dual, 10-bit, 165Msps digital-to-analog

converter (DAC) provides superior dynamic performance

in wideband communication systems. The device inte-

grates two 10-bit DAC cores, and a 1.24V reference. The

MAX5854 supports single-ended and differential modes

of operation. The dynamic performance is maintained

over the entire 2.7V to 3.6V power-supply operating

range. The analog outputs support a -1.0V to +1.25V

compliance voltage.

The MAX5854 can operate in interleaved data mode to

reduce the I/O pin count. This allows the converter to

be updated on a single, 10-bit bus.

The MAX5854 features digital control of channel gain

matching to within ±0.4dB in sixteen 0.05dB steps.

Channel matching improves sideband suppression in

analog quadrature modulation applications. The on-

chip 1.24V bandgap reference includes a control

amplifier that allows external full-scale adjustments of

both channels through a single resistor. The internal ref-

erence can be disabled and an external reference may

be applied for high-accuracy applications.

The MAX5854 features full-scale current outputs of 2mA

to 20mA and operates from a 2.7V to 3.6V single sup-

ply. The DAC supports three modes of power-control

operation: normal, low-power standby, and complete

power-down. In power-down mode, the operating

current is reduced to 1µA.

The MAX5854 is packaged in a 40-pin thin QFN with

exposed paddle (EP) and is specified for the extended

(-40°C to +85°C) temperature range.

Pin-compatible, lower speed, and lower resolution ver-

sions are also available. Refer to the MAX5853 (10-bit,

80Msps), the MAX5852** (8-bit, 165Msps), and the

MAX5851** (8-bit, 80Msps) data sheets for more informa-

tion. See Table 4 at the end of the data sheet.

Applications

Communications

SatCom, LMDS, MMDS, HFC, DSL, WLAN,

Point-to-Point Microwave Links

Wireless Base Stations

Quadrature Modulation

Direct Digital Synthesis (DDS)

Instrumentation/ATE

Features

♦ 10-Bit, 165Msps Dual DAC

♦ Low Power

190mW with I

= 20mA at f

CLK

= 165MHz

♦ 2.7V to 3.6V Single Supply

♦ Full Output Swing and Dynamic Performance at

2.7V Supply

♦ Superior Dynamic Performance

73dBc SFDR at f

OUT

= 40MHz

UMTS ACLR = 65.5dB at f

OUT

= 30.7MHz

♦ Programmable Channel Gain Matching

♦ Integrated 1.24V Low-Noise Bandgap Reference

♦ Single-Resistor Gain Control

♦ Interleaved Data Mode

♦ Single-Ended and Differential Clock Input Modes

♦ Miniature 40-Pin Thin QFN Package, 6mm x 6mm

♦ EV Kit Available—MAX5854 EV Kit

MAX5854

Dual, 10-Bit, 165Msps, Current-Output DAC

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3197; Rev 0; 2/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE

MAX5854ETL -40°C to +85°C

40 Thin QFN-EP*

40 36373839

19 2016 17

3132

3435

DA0

DB8

AGND

MAX5854

THIN QFN

TOP VIEW

OUTPA

OUTNA

AGND

OUTPB

OUTNB

REFR

REFO

DB9

DB6

DB7

DB5

DB4

DGND

DB2

DB3

CGND

CLK

CLKXN

CLKXP

DCE

DB0

DB1

DA1

DA2/G0

DA3/G1

DA4/G2

DA5/G3

DA6/REN

DA7/IDE

DA8/DACEN

DA9/PD

Pin Configuration

*EP = Exposed paddle.

**Future product—contact factory for availability.

Summary of content (18 pages)

PAGE 1
9-3197; Rev 0; 2/04 KIT ATION EVALU LE B A IL A AV Dual, 10-Bit, 165Msps, Current-Output DAC ♦ 2.7V to 3.6V Single Supply ♦ Full Output Swing and Dynamic Performance at 2.7V Supply ♦ Superior Dynamic Performance 73dBc SFDR at fOUT = 40MHz UMTS ACLR = 65.5dB at fOUT = 30.7MHz ♦ Programmable Channel Gain Matching ♦ Integrated 1.
PAGE 2
MAX5854 Dual, 10-Bit, 165Msps, Current-Output DAC ABSOLUTE MAXIMUM RATINGS AVDD, DVDD, CVDD to AGND, DGND, CGND .........-0.3V to +4V DA9–DA0, DB9–DB0, CW, DCE to AGND, DGND, CGND .......................................................-0.3V to +4V CLKXN, CLKXP to CGND.........................................-0.3V to +4V OUTP_, OUTN_ to AGND.......................-1.25V to (AVDD + 0.3V) CLK to DGND ..........................................-0.3V to (DVDD + 0.3V) REFR, REFO to AGND ..........................
PAGE 3
Dual, 10-Bit, 165Msps, Current-Output DAC (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL ACLR fOUT = 30.72MHz, RBW = 30kHz, fCLK = 122.
PAGE 4
MAX5854 Dual, 10-Bit, 165Msps, Current-Output DAC ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 5
Dual, 10-Bit, 165Msps, Current-Output DAC (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 6
MAX5854 Dual, 10-Bit, 165Msps, Current-Output DAC ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 7
Dual, 10-Bit, 165Msps, Current-Output DAC SFDR (dBc) -12dBFS 85 80 10 20 30 40 50 60 70 80 0dBFS 75 70 65 -6dBFS 60 55 50 45 40 90 MAX5854 toc03 90 -12dBFS 35 30 70 65 -12dBFS 60 55 50 45 40 35 -6dBFS 30 0 5 10 15 20 1 25 30 35 40 45 50 3 5 7 9 13 11 fOUT (MHz) fOUT (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 200MHz) SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 165MHz) SPURIOUS-FREE DYNAMIC RANGE vs.
PAGE 8
Typical Operating Characteristics (continued) (AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, external reference, differential clock, IFS = 20mA, differential output, TA = +25°C, unless otherwise noted.) -20 fT2 fT7 fT1 -60 fT8 -40 -50 -60 -30 -40 -50 -60 -70 -80 -80 -80 -90 -90 -90 -70 -100 4.7 9.7 14.7 19.7 24.7 fOUT (MHz) 29.7 34.7 39.7 -100 3.0 3.5 4.0 4.5 5.0 5.5 fOUT (MHz) 6.0 7.0 6.
PAGE 9
Dual, 10-Bit, 165Msps, Current-Output DAC POWER DISSIPATION vs. CLOCK FREQUENCY (fOUT = 10MHz, AOUT = 0dBFS) 220 0.2 0.1 0 -0.1 -0.2 DIFFERENTIAL CLOCK DRIVE 210 200 190 180 SINGLE-ENDED CLOCK DRIVE 170 -0.3 160 -0.4 0 150 300 450 600 750 900 240 220 200 SINGLE-ENDED CLOCK DRIVE 180 160 20 1050 DIFFERENTIAL CLOCK DRIVE 260 160 150 -0.5 45 70 95 120 145 170 2.70 2.85 fCLK (MHz) DIGITAL INPUT CODE REFERENCE VOLTAGE vs.
PAGE 10
Dual, 10-Bit, 165Msps, Current-Output DAC MAX5854 Pin Description PIN NAME 1 DA9/PD 2 3 10 FUNCTION Channel A Input Data Bit 9 (MSB)/Power-Down DA8/DACEN Channel A Input Data Bit 8/DAC Enable Control DA7/IDE Channel A Input Data Bit 7/Interleaved Data Enable 4 DA6/REN Channel A Input Data Bit 6/Reference Enable. Setting REN = 0 enables the internal reference. Setting REN = 1 disables the internal reference.
PAGE 11
Dual, 10-Bit, 165Msps, Current-Output DAC PIN NAME FUNCTION 32 REFR Full-Scale Current Adjustment. To set the output full-scale current, connect an external resistor RSET between REFR and AGND. The output full-scale current is equal to 32 x VREFO/RSET. 33, 39 AVDD Analog Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details.
PAGE 12
MAX5854 Dual, 10-Bit, 165Msps, Current-Output DAC Table 1. Control Word Format and Function MSB LSB PD DACEN REN IDE G3 CONTROL WORD PD G1 G0 X X FUNCTION Power-Down. The part enters power-down mode if PD = 1. DACEN DAC Enable. When DACEN = 0 and PD = 0, the part enters standby mode. IDE Interleaved Data Mode. IDE = 1 enables the interleaved data mode. In this mode, digital data for both channels is applied through channel A in a multiplexed fashion.
PAGE 13
Dual, 10-Bit, 165Msps, Current-Output DAC MAX5854 AVDD OPTIONAL EXTERNAL BUFFER FOR HEAVIER LOADS 10µF MAX4040 1.24V BANDGAP REFERENCE AGND REN = 0 1.24V BANDGAP REFERENCE AVDD REFO CCOMP* REFR MAX6520 CURRENTSOURCE ARRAY IREF IFS EXTERNAL 1.2V REFERENCE IREF = REN = 1 REFO AGND REFR VREF 0.1µF CURRENTSOURCE ARRAY IREF RSET RSET IFS AGND RSET MAX5854 AGND MAX5854 *COMPENSATION CAPACITOR (CCOMP ≈ 100nF). Figure 3. Setting IFS with the Internal 1.
PAGE 14
MAX5854 Dual, 10-Bit, 165Msps, Current-Output DAC tCXH tCXL CLKXN CLKXP tCDL tCDH CLK OUTPUT tCWL CW tDCS DA0–DA9 DACA - 1 tCS tDCH DACA + 1 DACA tCW CONTROL WORD DACA + 2 DACA + 3 OUTNA DACA - 1 DACA DACA + 1 DACA + 2 XXXX (CONTROL WORD DATA) DACA + 3 OUTPA tDCS DB0–DB9 DACB - 1 tDCH DACB + 1 DACB DACB + 2 XXXX DACB + 3 OUTNB DACB - 1 DACB DACB + 1 DACB + 2 XXXX OUTPB Figure 5.
PAGE 15
Dual, 10-Bit, 165Msps, Current-Output DAC AVDD DVDD CVDD 50Ω OUTPA DA0–DA9 MAX5854 AVDD DVDD CVDD VOUTA, SINGLE ENDED 1/2 50Ω DA0–DA9 OUTPA 1/2 100Ω MAX5854 10 MAX5854 10 OUTNA OUTNA 50Ω 50Ω OUTPB DB0–DB9 50Ω 50Ω VOUTB, SINGLE ENDED DB0–DB9 1/2 OUTPB 1/2 100Ω 10 MAX5854 10 MAX5854 OUTNB OUTNB 50Ω 50Ω AGND DGND CGND Figure 7.
PAGE 16
MAX5854 Dual, 10-Bit, 165Msps, Current-Output DAC or spurious-free dynamic range. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX5854. Observe the grounding and power-supply decoupling guidelines for highspeed, high-frequency applications. Follow the power supply and filter configuration to realize optimum dynamic performance. Use of a multilayer printed circuit (PC) board with separate ground and power-supply planes is recommended.
PAGE 17
Dual, 10-Bit, 165Msps, Current-Output DAC Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in dBc of either output tone to the worst 3rd-order (or higher) IMD products. Static Performance Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a line drawn between the end points of the transfer function, once offset and gain errors have been nullified.
PAGE 18
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QFN THIN 6x6x0.8.EPS MAX5854 Dual, 10-Bit, 165Msps, Current-Output DAC D2 D CL D/2 b D2/2 k E/2 E2/2 E (NE-1) X e CL E2 k e L (ND-1) X e CL CL L L e A1 A2 e A PACKAGE OUTLINE 36,40L THIN QFN, 6x6x0.8 mm 21-0141 D 1 2 NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2.