Datasheet

ManualsBrandsMaxim ManualsEEPROM1-Wire 256 bit EEPROM TO-92

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FEATURES

 256-bit Electrically Erasable Programmable

Read Only Memory (EEPROM) plus 64-bit

one-time programmable application register

 Unique, factory-lasered and tested 64-bit

registration number (8-bit family code + 48-bit

serial number + 8-bit CRC tester) assures

absolute identity because no two parts are alike

 Built-in multidrop controller ensures

compatibility with other MicroLAN products

 EEPROM organized as one page of 32 bytes

for random access

 Reduces control, address, data, and power to a

single data pin

 Directly connects to a single port pin of a

microprocessor and communicates at up to

15.3kbits per second

 8-bit family code specifies DS2430A

communication requirements to reader

 Presence detector acknowledges when reader

first applies voltage

 Low cost TO-92 or 6-pin TSOC and UCSP

surface mount package

 Reads and writes over a wide voltage range of

2.8V to 5.25V from -40°C to +85°C

ORDERING INFORMATION

PART

TEMP RANGE

PIN-PACKAGE

DS2430A+

-40°C to +85°C

3 TO-92

DS2430A+T&R

-40°C to +85°C

3 TO-92 (2k pcs)

DS2430AP+

-40°C to +85°C

6 TSOC

DS2430AP+T&R

-40°C to +85°C

6 TSOC (4k pcs)

+Denotes a lead(Pb)-free/RoHS-compliant package.

T&R = Tape and reel.

PIN ASSIGNMENT

NOTE: The leads of TO-92 packages on tape and reel are formed

to approximately 100-mil (2.54mm) spacing. For details see the

Package Information.

PIN DESCRIPTION

TO-92 TSOC

Pin 1 Ground Ground

Pin 2 Data Data

Pin 3 NC NC

Pin 4 –––– NC

Pin 5 –––– NC

Pin 6 –––– NC

DS2430A

256-Bit 1-Wire EEPROM

SIDE VIEW

TOP VIEW

3.7mm x 4.0mm x 1.5mm

TSOC PACKAGE

BOTTOM VIEW

TO-92

DALLAS

DS2430A

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19-5236; Rev 2/12

NOT RECOMMENDED FOR NEW DESIGNS

Summary of content (19 pages)

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9-5236; Rev 2/12 FEATURES      TSOC PACKAGE M E W SIDE VIEW 1 2 3 BOTTOM VIEW NOTE: The leads of TO-92 packages on tape and reel are formed to approximately 100-mil (2.54mm) spacing. For details see the Package Information.
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DS2430A DESCRIPTION D E S IG N S The DS2430A 256-bit 1-Wire® EEPROM identifies and stores relevant information about the product to which it is associated. This lot or product specific information can be accessed with minimal interface, for example a single port pin of a microcontroller.
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DS2430A N O T R E C O M M E N D E D FO R N E W D E S IG N S DS2430A BLOCK DIAGRAM Figure 1 3 of 19
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M E N D E D FO R N E W D E S IG N S HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 DS2430A O M 64-BIT LASERED ROM Figure 3 8-Bit CRC Code LSB MSB 8-Bit Family Code (14H) LSB MSB LSB E C MSB 48-Bit Serial Number Polynomial = X8 + X5 + X4 + 1 N O T R 1-WIRE CRC GENERATOR Figure 4 4 of 19
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DS2430A MEMORY E S IG N S The memory of the DS2430A consists of three separate sections, called data memory, application register, and status register (Figure 5). The data memory and the application register each have its own intermediate storage area called scratchpad that acts as a buffer when writing to the device. The data memory can be read and written as often as desired. The application register, however, is one-time programmable only.
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DS2430A N D E D FO R N E W D E S IG N S MEMORY FUNCTION FLOW CHART Figure 6 COPY SCRATCHPAD [55h] O M M E After the data stored in the scratchpad has been verified the master may send the Copy Scratchpad command followed by a validation key of A5h to transfer data from the scratchpad to the EEPROM memory. This command always copies the data of the entire scratchpad.
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DS2430A FO R N E W D E S IG N S MEMORY FUNCTION FLOW CHART Figure 6 (continued) WRITE APPLICATION REGISTER [99h] M E N D E D This command is essentially the same as the Write Scratchpad command, but it addresses the 64-bit register scratchpad. After issuing the command code, the master must provide a 1-byte address, followed by the data to be written. The DS2430A automatically increments the address after every byte it receives.
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DS2430A N D E D FO R N E W D E S IG N S MEMORY FUNCTION FLOW CHART Figure 6 (continued) READ APPLICATION REGISTER [C3h] R E C O M M E This command is used to read the application register or the register scratchpad. As long as the application register is not yet locked, the DS2430A transmits data from the register scratchpad. After the application register is locked the DS2430A transmits data from the application register, making the register scratchpad inaccessible for reading.
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DS2430A 1-WIRE BUS SYSTEM E S IG N S The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances, the DS2430A is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal type and timing).
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DS2430A N O T R E C O M M E N D E D FO R N E W D E S IG N S ROM FUNCTIONS FLOW CHART Figure 8 10 of 19
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DS2430A Transaction Sequence Initialization  ROM Function Command  Memory Function Command  Transaction/Data E S IG N  S The sequence for accessing the DS2430A via the 1-Wire port is as follows: INITIALIZATION D All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a Reset Pulse transmitted by the bus master followed by a Presence Pulse(s) transmitted by the slave(s).
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DS2430A After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Application Note 187 for a comprehensive discussion of a search ROM, including an actual example. 1-Wire Signaling E S IG N S The DS2430A requires strict protocols to insure data integrity.
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DS2430A Master-to-Slave E S IG N S For a Write-1 time slot, the voltage on the data line must have crossed the VTH threshold before the Write-1 low time tW1LMAX is expired. For a Write-0 time slot, the voltage on the data line must stay below the VTH threshold until the Write-0 low time tW0LMIN is expired. For the most reliable communication, the voltage on the data line should not exceed VILMAX during the entire tW0L or tW1L window.
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DS2430A Slave-to-Master E S IG N S A Read-data time slot begins like a Write-1 time slot. The voltage on the data line must remain below VTL until the read low time tRL is expired. During the tRL window, when responding with a 0, the DS2430A starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again.
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DS2430A MEMORY FUNCTION EXAMPLE FO R N E W D E S IG N COMMENTS Reset pulse (480µs to 960µs) Presence pulse Issue “Skip ROM” command Issue “Write Scratchpad” command Start address = 06h Write 2 bytes of data to scratchpad Reset pulse Presence pulse Issue “Skip ROM” command Issue “Read Scratchpad” command Start address = 06h Read scratchpad data and verify Reset pulse Presence pulse Issue “Skip ROM” command Issue “Copy Scratchpad” command Validation key Data line must be above VPUPmin for tPROG.
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ABSOLUTE MAXIMUM RATINGS -0.5V to +6.0V 20mA -40°C to +85°C +150°C -55°C to +125°C +300°C E S IG N Voltage Range on DATA to Ground DATA Sink Current Operating Temperature Range Junction Temperature Storage Temperature Range Lead Temperature (soldering, 10s) Soldering Temperature (reflow) TSOC TO-92 S DS2430A +260°C +250°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
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DS2430A ELECTRICAL CHARACTERISTICS (continued) (TA = -40°C to +85°C, unless otherwise noted.) (Note 1) E S IG N Note 2: Note 3: Note 4: E W D Note 5: Note 6: Note 7: Note 8: FO R N Note 9: Note 10: Note 11: Note 12: Note 13: D Note 14: Note 15: N D E Note 16: Note 17: M M E Note 18: R E C O Note 19: Note 20: Note 21: Note 22: Note 23: Limits are 100% production tested at TA = +25°C and/or TA = +85°C.
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DS2430A PACKAGE INFORMATION For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 21-0248 21-0250 21-0382 LAND PATTERN NO. — — S OUTLINE NO.
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DS2430A REVISION DATE 4/3/95 Initial release Changed “C-lead” package to “TSOC” package. Deleted VIHmax specification value. Note “Under certain low voltage conditions VILMAX may have to be reduced to as much as 0.5V to always guarantee a presence pulse.” added to VIL specification, changed VCC to VPUP in Note 6. Changed “Touch Memory” to “iButton”.