Datasheet

 2009-2012 Microchip Technology Inc. Preliminary DS41393B-page 17
AR1000 SERIES RESISTIVE TOUCH SCREEN CONTROLLER
4.0 I
2
C
TM
COMMUNICATIONS
The AR1021 is an I
2
C slave device with a 7-bit address
of 0x4D, supporting up to 400 kHz bit rate.
A master (host) device interfaces with the AR1021.
4.1 I
2
C Hardware Interface
A summary of the hardware interface pins is shown
below in Table 4- 1 .
M1 Pin
• The M1 pin must be connected to V
SS to config-
ure the AR1021 for I
2
C communications.
SCL Pin
• The SCL (Serial Clock) pin is electrically
open-drain and requires a pull-up resistor, typi-
cally 2.2 K to 10 K, from SCL to V
DD.
• SCL Idle state is high.
SDA Pin
• The SDA (Serial Data) pin is electrically
open-drain and requires a pull-up resistor, typi-
cally 2.2K to 10K, from SDA to V
DD.
• SDA Idle state is high.
• Master write data is latched in on SCL rising
edges.
• Master read data is latched out on SCL falling
edges to ensure it is valid during the subsequent
SCL high time.
SDO Pin
• The SDO pin is a driven output interrupt to the
master.
• SDO Idle state is low.
• SDO will be asserted high when the AR1021 has
data ready (touch report or command response)
for the master to read.
TABLE 4-1: I
2
C HARDWARE INTERFACE
AR1021 Pin Description
M1 Connect to V
SS to select I
2
C™ communications
SCL Serial Clock to master I
2
C
SDA Serial Data to master I
2
C
SDO Data ready interrupt output to master