Datasheet

AR1000 SERIES RESISTIVE TOUCH SCREEN CONTROLLER
DS41393B-page 18 Preliminary  2009-2012 Microchip Technology Inc.
4.2 I
2
C Pin Voltage Level
Characteristics
4.3 Addressing
The AR1021’s device ID 7-bit address is: 0x4D
(0b1001101)
4.4 Master Read Bit Timing
Master read is to receive touch reports and command
responses from the AR1021.
• Address bits are latched into the AR1021 on the
rising edges of SCL.
• Data bits are latched out of the AR1021 on the
rising edges of SCL.
• ACK is presented (by AR1021 for address, by
master for data) on the ninth clock.
• The master must monitor the SCL pin prior to
asserting another clock pulse, as the AR1021
may be holding off the master by stretching the
clock.
FIGURE 4-1: I
2
C MASTER READ BIT TIMING DIAGRAM
Steps
1. SCL and SDA lines are Idle high.
2. Master presents “Start” bit to the AR1021 by
taking SDA high-to-low, followed by taking SCL
high-to-low.
3. Master presents 7-bit Address, followed by a
R/W = 1 (Read mode) bit to the AR1021 on
SDA, at the rising edge of eight master clock
(SCL) cycles.
4. AR1021 compares the received address to its
device ID. If they match, the AR1021
acknowledges (ACK) the master sent address
by presenting a low on SDA, followed by a
low-high-low on SCL.
5. Master monitors SCL, as the AR1021 may be
“clock stretching”, holding SCL low to indicate
that the master should wait.
TABLE 4-2: I
2
C PIN VOLTAGE LEVEL CHARACTERISTICS
Function Pin Input Output
SCL/SCK SCL/SCK/TX V
SS ≤ VIL≤ 0.2*VDD
0.8*VDD ≤ VIH ≤ VDD
—
SDO SDO — V
SS ≤ VOL
(1)
≤ (1.2V – 0.15*VDD)
(2)
(1.25*VDD – 2.25V)
(3)
≤ VOH
(1)
≤ VDD
SDA SDI/SDA/RX VSS ≤ VIL ≤ 0.2*VDD
0.8*VDD ≤ VIH ≤ VDD
Open-drain
Note 1: These parameters are characterized but not tested.
2: At 10 mA.
3: At –4 mA.
TABLE 4-3: I
2
C DEVICE ID ADDRESS
Device ID Address, 7-bit
A7 A6 A5 A4 A3 A2 A1
1001101
TABLE 4-4: I
2
C DEVICE WRITE ID
ADDRESS
A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 1 1010 0x9A
TABLE 4-5: I
2
C DEVICE READ ID
ADDRESS
A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 1 1011 0x9B