PIC18F2331/2431/4331/4431 Data Sheet 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC18F2331/2431/4331/4431 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D 14-Bit Power Control PWM Module: Power-Managed Modes: • • • • • • • • • • • • • • Up to 4 Channels with Complementary Outputs Edge or Center-Aligned Operation Flexible Dead-Band Generator Hardware Fault Protection Inputs Simultaneous Update of Duty Cycle and Period: - Flexible Special Event Trigger output Motion Feedback Module: • Three Independent Input Capture Channels: - Flex
PIC18F2331/2431/4331/4431 Pin Diagrams 28-Pin SPDIP, SOIC 1 28 RB7/KBI3/PGD RA0/AN0 2 27 RB6/KBI2/PGC RA1/AN1 3 26 RB5/KBI1/PWM4/PGM RA2/AN2/VREF-/CAP1/INDX 25 24 RB4/KBI0/PWM5 RA3/AN3/VREF+/CAP2/QEA 4 5 RA4/AN4/CAP3/QEB 6 23 RB2/PWM2 AVDD 7 8 22 21 RB1/PWM1 AVSS PIC18F2331/2431 MCLR/VPP RB3/PWM3 RB0/PWM0 VDD 20 19 VSS OSC2/CLKO/RA6 9 10 RC0/T1OSO/T1CKI 11 18 RC7/RX/DT/SDO RC1/T1OSI/CCP2/FLTA 12 13 14 17 16 15 RC6/TX/CK/SS OSC1/CLKI/RA7 RC2/CCP1 RC3/T0CKI/T5CKI/INT
PIC18F2331/2431/4331/4431 Pin Diagrams (Continued) MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RA4/AN4/CAP3/QEB RA5/AN5/LVDIN RE0/AN6 RE1/AN7 RE2/AN8 AVDD AVSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2/FLTA RC2/CCP1/FLTB RC3/T0CKI(1)/T5CKI(1)/INT0 RD0/T0CKI/T5CKI RD1/SDO Note 1: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIC18F4331/4431 40-Pin PDIP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PW
PIC18F2331/2431/4331/4431 Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 RC6/TX/CK/SS RC5/INT2/SCK(1)/SCL(1) RC4/INT1/SDI(1)/SDA(1) RD3/SCK/SCL RD2/SDI/SDA RD1/SDO RD0/T0CKI/T5CKI RC3/T0CKI(1)/T5CKI(1)/INT0 RC2/CCP1/FLTB RC1/T1OSI/CCP2/FLTA NC 44-Pin TQFP PIC18F4331 PIC18F4431 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 NC RC0/T1OSO/T1CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 AVSS AVDD RE2/AN8 RE1/AN7 RE0/AN6 RA5/AN5/LVDIN RA4/AN4/CAP3/QEB NC NC RB4/KB
PIC18F2331/2431/4331/4431 Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 RC6/TX/CK/SS RC5/INT2/SCK(1)/SCL(1) RC4/INT1/SDI(1)/SDA(1) RD3/SCK/SCL RD2/SDI/SDA RD1/SDO RD0/T0CKI/T5CKI RC3/T0CKI(1)/T5CKI(1)/INT0 RC2/CCP1/FLTB RC1/T1OSI/CCP2/FLTA RC0/T1OSO/T1CKI 44-Pin QFN(2) PIC18F4331 PIC18F4431 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS AVSS AVDD VDD RE2/AN8 RE1/AN7 RE0/AN6 RA5/AN5/LVDIN RA4/AN4/CAP3/QEB RB3/PWM3
PIC18F2331/2431/4331/4431 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with PIC18F Microcontrollers ..................................................................................................... 25 3.0 Oscillator Configurations .............................................................................
PIC18F2331/2431/4331/4431 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 10 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • • • • PIC18F2331 PIC18F2431 PIC18F4331 PIC18F4431 • • • • PIC18LF2331 PIC18LF2431 PIC18LF4331 PIC18LF4431 This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price, with the addition of high-endurance enhanced Flash program memory and a high-speed 10-bit A/D Converter.
PIC18F2331/2431/4331/4431 1.2 Other Special Features • Memory Endurance: The enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 100 years. • Self-Programmability: These devices can write to their own program memory spaces under internal software control.
PIC18F2331/2431/4331/4431 1.3 All other features for devices in this family are identical. These are summarized in Table 1-1. Details on Individual Family Members Devices in the PIC18F2331/2431/4331/4431 family are available in 28-pin (PIC18F2331/2431) and 40/44-pin (PIC18F4331/4431) packages. The block diagram for the two groups is shown in Figure 1-1. The devices are differentiated from each other in three ways: 1. 2. 3.
PIC18F2331/2431/4331/4431 FIGURE 1-1: PIC18F2331/2431 (28-PIN) BLOCK DIAGRAM Data Bus<8> PORTA 21 Table Pointer<21> 8 8 21 Data RAM (768 bytes) inc/dec logic 21 Address Latch RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RA4/AN4/CAP3/QEB OSC2/CLKO/RA6 OSC1/CLKI/RA7 Data Latch Address Latch 20 Program Memory PCLATU PCLATH 12 Address<12> PCU PCH PCL Program Counter Data Latch 4 12 BSR 31 Level Stack 16 Decode Table Latch PORTB 4 FSR0 FSR1 FSR2 Bank 0, F 12 inc/dec l
PIC18F2331/2431/4331/4431 FIGURE 1-2: PIC18F4331/4431 (40/44-PIN) BLOCK DIAGRAM Data Bus<8> PORTA 21 Table Pointer<21> 8 8 21 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RA4/AN4/CAP3/QEB RA5/AN5/LVDIN OSC2/CLKO/RA6 OSC1/CLKI/RA7 Data Latch Data RAM (768 bytes) inc/dec logic 21 Address Latch Address Latch 20 Program Memory PCLATU PCLATH 12 Address<12> PCU PCH PCL Program Counter Data Latch 4 12 BSR 31 Level Stack 16 Decode Table Latch PORTB 4 FSR0 FSR1 FSR2 Bank 0
PIC18F2331/2431/4331/4431 TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS Pin Number Pin Name MCLR/VPP MCLR Pin Buffer SPDIP, Type Type QFN SOIC 1 26 I VPP OSC1/CLKI/RA7 OSC1 P 9 6 I CLKI I RA7 OSC2/CLKO/RA6 OSC2 ST I/O 10 Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. High-voltage ICSP™ programming enable pin. Oscillator crystal or external clock input.
PIC18F2331/2431/4331/4431 TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer SPDIP, Type Type QFN SOIC Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F2331/2431/4331/4431 TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer SPDIP, Type Type QFN SOIC Description PORTC is a bidirectional I/O port.
PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS Pin Name MCLR/VPP/RE3 MCLR Pin Number Pin Buffer Type Type PDIP TQFP QFN 1 18 18 VPP RE3 OSC1/CLKI/RA7 OSC1 13 30 I ST P I ST 32 I CLKI I RA7 I/O OSC2/CLKO/RA6 OSC2 14 31 Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Available only when MCLR is disabled.
PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer Type Type PDIP TQFP QFN Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 2 RA1/AN1 RA1 AN1 3 RA2/AN2/VREF-/CAP1/ INDX RA2 AN2 VREFCAP1 INDX 4 RA3/AN3/VREF+/ CAP2/QEA RA3 AN3 VREF+ CAP2 QEA 5 RA4/AN4/CAP3/QEB RA4 AN4 CAP3 QEB 6 RA5/AN5/LVDIN RA5 AN5 LVDIN 7 19 20 21 22 23 24 19 I/O I TTL Analog Digital I/O. Analog Input 0.
PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer Type Type PDIP TQFP QFN Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer Type Type PDIP TQFP QFN Description PORTC is a bidirectional I/O port.
PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer Type Type PDIP TQFP QFN Description PORTD is a bidirectional I/O port. RD0/T0CKI/T5CKI RD0 T0CKI T5CKI 19 RD1/SDO RD1 SDO(1) 20 RD2/SDI/SDA RD2 SDI(1) SDA(1) 21 RD3/SCK/SCL RD3 SCK(1) SCL(1) 22 RD4/FLTA RD4 FLTA(2) 27 RD5/PWM4 RD5 PWM4(3) 28 RD6/PWM6 RD6 PWM6 29 RD7/PWM7 RD7 PWM7 30 38 39 40 41 2 3 4 5 38 I/O I I ST ST ST Digital I/O.
PIC18F2331/2431/4331/4431 TABLE 1-3: Pin Name PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Type Type PDIP TQFP QFN Description PORTE is a bidirectional I/O port. RE0/AN6 RE0 AN6 8 RE1/AN7 RE1 AN7 9 RE2/AN8 RE2 AN8 10 VSS 12, 31 VDD NC 25 25 I/O I ST Analog Digital I/O. Analog Input 6. I/O I ST Analog Digital I/O. Analog Input 7. I/O I ST Analog Digital I/O. Analog Input 8. 6, 29 6, 30, 31 P — Ground reference for logic and I/O pins.
PIC18F2331/2431/4331/4431 2.
PIC18F2331/2431/4331/4431 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC18F2331/2431/4331/4431 2.3 Master Clear (MCLR) Pin The MCLR pin provides two specific device functions: Device Reset, and Device Programming and Debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1.
PIC18F2331/2431/4331/4431 2.5 External Oscillator Pins FIGURE 2-3: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 3.0 “Oscillator Configurations” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
PIC18F2331/2431/4331/4431 3.0 OSCILLATOR CONFIGURATIONS 3.1 Oscillator Types FIGURE 3-1: C1(1) The PIC18F2331/2431/4331/4431 devices can be operated in 10 different oscillator modes. The user can program the Configuration bits, FOSC<3:0>, in Configuration Register 1H to select one of these 10 modes: 1. 2. 3. 4. LP XT HS HSPLL 5. RC 6. RCIO 7. INTIO1 8. INTIO2 9. EC 10. ECIO 3.
PIC18F2331/2431/4331/4431 TABLE 3-2: Osc Type LP XT HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq Typical Capacitor Values Tested: C1 C2 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF 1 MHz 33 pF 33 pF 4 MHz 27 pF 27 pF 4 MHz 27 pF 27 pF 8 MHz 22 pF 22 pF 20 MHz 15 pF 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized.
PIC18F2331/2431/4331/4431 3.4 External Clock Input The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 3-4 shows the pin connections for the EC Oscillator mode.
PIC18F2331/2431/4331/4431 3.6 Internal Oscillator Block The PIC18F2331/2431/4331/4431 devices include an internal oscillator block, which generates two different clock signals; either can be used as the system’s clock source. This can eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the system clock.
PIC18F2331/2431/4331/4431 REGISTER 3-1: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits 011111 = Maximum frequency • • • • 000001 000000 = Center frequency.
PIC18F2331/2431/4331/4431 3.7 Clock Sources and Oscillator Switching Like previous PIC18 devices, the PIC18F2331/2431/ 4331/4431 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F2331/ 2431/4331/4431 devices offer two alternate clock sources. When enabled, these give additional options for switching to the various power-managed operating modes.
PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 CLOCK DIAGRAM CONFIG1H <3:0> Primary Oscillator OSC2 LP, XT, HS, RC, EC OSC1 Secondary Oscillator T1OSC T1OSO T1OSI OSCCON<1:0> HSPLL 4 x PLL Sleep Clock Control Clock Source Option for other Modules T1OSCEN Enable Oscillator OSCCON<6:4> 8 MHz OSCCON<6:4> MUX FIGURE 3-8: Peripherals Internal Oscillator CPU 111 4 MHz 8 MHz (INTOSC) Postscaler INTRC Source 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 31 kHz 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Idle mode enabled; CPU core is not clocked in power-managed modes 0 = Run mode enabled; CPU core is clocked in power-manag
PIC18F2331/2431/4331/4431 3.7.2 OSCILLATOR TRANSITIONS The PIC18F2331/2431/4331/4431 devices contain circuitry to prevent clocking “glitches” when switching between clock sources. A short pause in the system clock occurs during the clock switch. The length of this pause is between 8 and 9 clock periods of the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources.
PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 38 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 4.0 4.1.1 POWER-MANAGED MODES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: PIC18F2331/2431/4331/4431 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices).
PIC18F2331/2431/4331/4431 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • OSTS (OSCCON<3>) • IOFS (OSCCON<2>) • T1RUN (T1CON<6>) In general, only one of these bits will be set while in a given power-managed mode.
PIC18F2331/2431/4331/4431 FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 T1OSI 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition(1) OSC1 CPU Clock Peripheral Clock Program Counter Note 1: PC PC + 2 PC + 4 Clock transition typically occurs within 2-4 TOSC.
PIC18F2331/2431/4331/4431 If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks. On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-4).
PIC18F2331/2431/4331/4431 4.3 Sleep Mode 4.4 The power-managed Sleep mode in the PIC18F2331/ 2431/4331/4431 devices is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-5). All clock source status bits are cleared. Entering the Sleep mode from any other mode does not require a clock switch.
PIC18F2331/2431/4331/4431 4.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm-up” or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction.
PIC18F2331/2431/4331/4431 4.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP.
PIC18F2331/2431/4331/4431 4.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode, where the primary clock source is not stopped; and • the primary clock source is not any of the LP, XT, HS or HSPLL modes.
PIC18F2331/2431/4331/4431 5.0 RESET The PIC18F2331/2431/4331/4431 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset FIGURE 5-1: This section discusses Resets generated by MCLR, POR and BOR, and the operation of the various startup timers.
PIC18F2331/2431/4331/4431 5.1 RCON Register Device Reset events are tracked through the RCON register (Register 5-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be cleared by the event and must be set by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 5.6 “Reset State of Registers”.
PIC18F2331/2431/4331/4431 5.2 Master Clear (MCLR) FIGURE 5-2: The MCLR pin can trigger an external Reset of the device by holding the pin low. These devices have a noise filter in the MCLR Reset path that detects and ignores small pulses. In PIC18F2331/2431/4331/4431 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. For more information, see Section 11.5 “PORTE, TRISE and LATE Registers”. 5.
PIC18F2331/2431/4331/4431 5.5 5.5.3 Device Reset Timers PIC18F2331/2431/4331/4431 devices incorporate three separate on-chip timers that help regulate the Power-on Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: • Power-up Timer (PWRT) • Oscillator Start-up Timer (OST) • PLL Lock Time-out 5.5.
PIC18F2331/2431/4331/4431 5.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation.
PIC18F2331/2431/4331/4431 FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39616D-page 52 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 FIGURE 5-7: TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST TPLL OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer.
PIC18F2331/2431/4331/4431 TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets TOSU 2331 2431 4331 4431 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu(3) TOSL 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 2331 2431 4331 4431 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU 2331 2431 4331 4431 ---0 0000 ---0 0000 ---u uuuu PCLATH
PIC18F2331/2431/4331/4431 TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt FSR1H 2331 2431 4331 4431 ---- 0000 ---- uuuu ---- uuuu FSR1L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu BSR 2331 2431 4331 4431 ---- 0000 ---- 0000 ---- uuuu INDF2 2331 2431 4331 4431 N/A N/A N/A Register POSTINC2 2331 2431 4331 4431 N/A N/A N/A P
PIC18F2331/2431/4331/4431 TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt ADRESH 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu ADCON1 2331 2431 4331 4431 00-0 0000 00-0 0000 uu-u uuuu ADCON2 2331 2431 4331 4431 0000
PIC18F2331/2431/4331/4431 TABLE 5-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt IPR2 2331 2431 4331 4431 1--1 -1-1 1--1 -1-1 u--u -u-u PIR2 2331 2431 4331 4431 0--0 -0-0 0--0 -0-0 u--u -u-u PIE2 2331 2431 4331 4431 0--0 -0-0 0--0 -0-0 u--u -u-u IPR1 2331 2431 4331 4431 -111 1111 -111 1111 -uuu uuuu PIR1 2331 2431 4331 4431 -000
PIC18F2331/2431/4331/4431 TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt PTCON0 2331 2431 4331 4431 0000 0000 uuuu uuuu uuuu uuuu PTCON1 2331 2431 4331 4431 00-- ---- 00-- ---- uu-- ---- PTMRL 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu PTMRH 2331 2431 4331 4431 ---- 0000 ---- 0000 ---- uuuu PTPERL 2331 2431 4331 4431 1111 1
PIC18F2331/2431/4331/4431 TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Register Applicable Devices Power-on Reset, Brown-out Reset CAP3BUFL/ MAXCNTL 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CAP1CON 2331 2431 4331 4431 -0-- 0000 -0-- 0000 -u-- uuuu CAP2CON 2331 2431 4331 4431 -0-- 0000 -0-- 0000 -u-- uuuu CAP3CON 2331 2431 4331 4431 -0-- 0000 -0-- 0000 -u-- uuuu DFLTCON
PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 60 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 6.0 MEMORY ORGANIZATION There are three memory types in enhanced MCU devices. These memory types are: • Program Memory • Data RAM • Data EEPROM As Harvard architecture devices, the data and program memories use separate buses, enabling concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers.
PIC18F2331/2431/4331/4431 6.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and contained in three 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte (PCH register) contains the PC<15:8> bits and is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is the PCU register and contains the bits, PC<20:16>.
PIC18F2331/2431/4331/4431 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and set the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or a POR occurs. FIGURE 6-3: Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken.
PIC18F2331/2431/4331/4431 6.1.2.3 PUSH and POP Instructions Since the Top-of-Stack (TOS) is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable option. To push the current PC value onto the stack, a PUSH instruction can be executed. This will increment the Stack Pointer and load the current PC value onto the stack. TOSU, TOSH and TOSL can then be modified to place data or a return address on the stack.
PIC18F2331/2431/4331/4431 6.1.4.2 Table Reads and Table Writes 6.2 A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored, two bytes per program word, by using table reads and writes. The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4.
PIC18F2331/2431/4331/4431 6.4 Instructions in Program Memory The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). Figure 6-5 shows an example of how instruction words are stored in the program memory. To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read ‘0’.
PIC18F2331/2431/4331/4431 6.5 The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this subsection. Data Memory Organization The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4,096 bytes of data memory.
PIC18F2331/2431/4331/4431 6.5.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes.
PIC18F2331/2431/4331/4431 6.5.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 6-1 and Table 6-2. The SFRs can be classified into two sets: those associated with the “core” function and those related to the peripheral functions.
PIC18F2331/2431/4331/4431 TABLE 6-2: File Name REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) Bit 7 Bit 6 Bit 5 — — — TOSU TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKFUL STKUNF — PCLATU — — bit 21(3) Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — — Bit 3 Bit 2 Bit 1 Bit 0 Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR ---0 0000 0000 0000 0000 0000 STKPTR PCLATH Bit 4 SP4 SP3 SP2 SP1 SP0 Holding Register f
PIC18F2331/2431/4331/4431 TABLE 6-2: File Name REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED) Bit 6 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0000 q000 LVDCON — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 WDTCON WDTW — — — — — — SWDTEN 0--- ---0 IPEN — — RI TO PD POR BOR 0--1 11q0 RCON Bit 5 TMR1H Timer1 Register High Byte TMR1L Timer1 Register Low Byte T1CON RD16 T1RUN TMR2 Timer2 Register PR2 Timer2 Period Register T2CON —
PIC18F2331/2431/4331/4431 TABLE 6-2: File Name REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR EEADR EEPROM Address Register 0000 0000 EEDATA EEPROM Data Register 0000 0000 EECON2 EEPROM Control Register 2 (not a physical register) EECON1 0000 0000 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 IPR3 — — — PTIP IC3DRIP IC2QEIP IC1IP TMR5IP ---1 1111 PIR3 — — — PTIF IC3DRIF IC2QEIF IC1IF
PIC18F2331/2431/4331/4431 TABLE 6-2: File Name PDC0L REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWM Duty Cycle #0L Register (lower 8 bits) PDC0H PDC1L 0000 0000 PWM Duty Cycle #0H Register (upper 6 bits) UNUSED --00 0000 PWM Duty Cycle #1L Register (lower 8 bits) PDC1H PDC2L 0000 0000 PWM Duty Cycle #1H Register (upper 6 bits) UNUSED --00 0000 PWM Duty Cycle #2L Register (lower 8 bits) PDC2H PDC3L(4) 0000 0000 PWM Dut
PIC18F2331/2431/4331/4431 6.6 STATUS Register The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic.
PIC18F2331/2431/4331/4431 6.7 Data Addressing Modes The data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. The addressing modes are: • • • • Inherent Literal Direct Indirect 6.7.1 The destination of the operation’s results is determined by the destination bit, ‘d’.
PIC18F2331/2431/4331/4431 6.7.3.1 FSR Registers and the INDF Operand 6.7.3.2 At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations.
PIC18F2331/2431/4331/4431 The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 6.7.3.
PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 78 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 7.0 DATA EEPROM MEMORY 7.2 EECON1 and EECON2 Registers The data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). Access to the data EEPROM is controlled by two registers: EECON1 and EECON2.
PIC18F2331/2431/4331/4431 REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit (cannot be cleared in software) R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEP
PIC18F2331/2431/4331/4431 7.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation).
PIC18F2331/2431/4331/4431 7.7 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if either of these mechanisms are enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 23.0 “Special Features of the CPU” for additional information. 7.
PIC18F2331/2431/4331/4431 TABLE 7-1: Name INTCON REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 EEADR EEPROM Address Register 56 EEDATA EEPROM Data Register 56 EECON2 EEPROM Control Register 2 (not a physical register) 56 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 56 IPR2 OSCFIP — — EEIP — LVDIP — CCP2IP 57 PIR2 OSCFIF — — EEIF —
PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 84 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 8.0 FLASH PROGRAM MEMORY The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A bulk erase operation may not be issued from user code. While writing or erasing program memory, instruction fetches cease until the operation is complete.
PIC18F2331/2431/4331/4431 FIGURE 8-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: 8.2 The Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section 8.5 “Writing to Flash Program Memory”.
PIC18F2331/2431/4331/4431 REGISTER 8-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit (cannot be cleared in software) R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access dat
PIC18F2331/2431/4331/4431 8.2.2 TABLAT – TABLE LATCH REGISTER 8.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch is used to hold 8-bit data during data transfers between program memory and data RAM. 8.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the Table Pointer determine which byte is read from program or configuration memory into TABLAT.
PIC18F2331/2431/4331/4431 8.3 Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and place it into data RAM. Table reads from program memory are performed one byte at a time. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 8-4 shows the interface between the internal program memory and the TABLAT.
PIC18F2331/2431/4331/4431 8.4 8.4.1 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Larger blocks of program memory can be bulk erased only through the use of an external programmer or ICSP control. Word erase in the Flash array is not supported. The sequence of events for erasing a block of internal program memory location is: 1. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased.
PIC18F2331/2431/4331/4431 The programming block size is 4 words or 8 bytes. Word or byte programming is not supported. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 8 holding registers used by the table writes for programming.
PIC18F2331/2431/4331/4431 8.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE 7. The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. Read 64 bytes into RAM. Update data values in RAM as necessary. Load Table Pointer with address being erased. Do the row erase procedure (see Section 8.4.1 “Flash Program Memory Erase Sequence”). Load Table Pointer with the address of the first byte being written.
PIC18F2331/2431/4331/4431 EXAMPLE 8-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64' COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT,W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; number of bytes in erase block ;
PIC18F2331/2431/4331/4431 EXAMPLE 8-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BCF MOVLW MOVWF MOVLW MOVWF BSF NOP BSF DECFSZ GOTO BCF 8.5.2 INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR ; disable interrupts ; required sequence ; write 55h INTCON, GIE COUNTER_HI PROGRAM_LOOP EECON1, WREN ; re-enable interrupts ; loop until done ; write 0AAh ; start program (CPU stall) ; disable write to memory WRITE VERIFY reprogrammed if needed.
PIC18F2331/2431/4331/4431 9.0 8 x 8 HARDWARE MULTIPLIER 9.1 Introduction 9.2 Example 9-1 shows the sequence to do an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL.
PIC18F2331/2431/4331/4431 Example 9-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES<3:0>.
PIC18F2331/2431/4331/4431 10.0 INTERRUPTS The PIC18F2331/2431/4331/4431 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high-priority level or a low-priority level. The highpriority interrupt vector is at 000008h and the low-priority interrupt vector is at 000018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress.
PIC18F2331/2431/4331/4431 FIGURE 10-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Wake-up if in Power-Managed Mode Interrupt to CPU Vector to Location 0008h INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP TXIF TXIE TXIP GIE/GIEH ADIF ADIE ADIP IPEN IPEN PEIE/GIEL RCIF RCIE RCIP IPEN Additional Peripheral Interrupts High-Priority Interrupt Generation Low-Priority Interrupt Generation TXIF TXIE TXIP ADIF ADIE ADIP RCIF RCIE RCIP TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP Interrupt to
PIC18F2331/2431/4331/4431 10.1 INTCON Registers Note: The INTCON registers are readable and writable registers which contain various enable, priority and flag bits. REGISTER 10-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18F2331/2431/4331/4431 REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt
PIC18F2331/2431/4331/4431 REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priori
PIC18F2331/2431/4331/4431 10.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) Registers (PIR1, PIR2 and PIR3). Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>).
PIC18F2331/2431/4331/4431 REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 U-0 R/W-0 OSCFIF — — EEIF — LVDIF — CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device
PIC18F2331/2431/4331/4431 REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PTIF IC3DRIF IC2QEIF IC1IF TMR5IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 PTIF: PWM Time Base Interrupt bit 1 = PWM time base matched the value in the PTPER registers.
PIC18F2331/2431/4331/4431 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable Registers (PIE1, PIE2 and PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18F2331/2431/4331/4431 REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 U-0 R/W-0 OSCFIE — — EEIE — LVDIE — CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6-5 Unimplemented: Read as ‘0’ bit 4 EEIE: Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3
PIC18F2331/2431/4331/4431 REGISTER 10-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PTIE IC3DRIE IC2QEIE IC1IE TMR5IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 PTIE: PWM Time Base Interrupt Enable bit 1 = PTIF enabled 0 = PTIF disabled bit 3 IC3DRIE: IC3 Interrupt Enable/Direction Chang
PIC18F2331/2431/4331/4431 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three peripheral interrupt priority registers (IPR1, IPR2 and IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
PIC18F2331/2431/4331/4431 REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 U-0 U-0 R/W-1 U-0 R/W-1 U-0 R/W-1 OSCFIP — — EEIP — LVDIP — CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6-5 Unimplemented: Read as ‘0’ bit 4 EEIP: Interrupt Priority bit 1 = High priority
PIC18F2331/2431/4331/4431 REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — PTIP IC3DRIP IC2QEIP IC1IP TMR5IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 PTIP: PWM Time Base Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 IC3DRIP: IC3 Interrupt Priority/Direction
PIC18F2331/2431/4331/4431 10.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from a powermanaged mode. RCON also contains the bit that enables interrupt priorities (IPEN).
PIC18F2331/2431/4331/4431 10.6 INTx Pin Interrupts 10.7 External interrupts on the INT0, INT1 and INT2 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge. If the bit is clear, the trigger is on the falling edge. When a valid edge appears on the INTx pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE.
PIC18F2331/2431/4331/4431 11.0 I/O PORTS 11.1 Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation.
PIC18F2331/2431/4331/4431 TABLE 11-1: PORTA I/O SUMMARY Pin RA0/AN0 RA1/AN1 RA2/AN2/VREF-/ CAP1/INDX RA3/AN3/VREF+/ CAP2/QEA RA4/AN4/CAP3/ QEB RA5/AN5/LVDIN OSC2/CLKO/RA6 OSC1/CLKI/RA7 Legend: Function TRIS Setting I/O I/O Type RA0 0 O DIG 1 I TTL PORTA<0> data input; disabled when analog input is enabled. AN0 1 I ANA A/D Input Channel 0. Default input configuration on POR; does not affect digital output. RA1 0 O DIG LATA<1> data output; not affected by analog input.
PIC18F2331/2431/4331/4431 TABLE 11-2: Name PORTA SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 57 (1) (1) LATA LATA7 LATA6 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Register LATA Data Output Register 57 57 ADCON1 VCFG1 VCFG0 — FIFOEN BFEMT BFOVFL ADPNT1 ADPNT0 56 ANSEL0 ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0 56 ANSEL1 — — — — — — — A
PIC18F2331/2431/4331/4431 11.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped.
PIC18F2331/2431/4331/4431 TABLE 11-3: Pin RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3 RB4/KBI0/PWM5 PORTB I/O SUMMARY Function TRIS Setting I/O I/O Type RB0 0 O DIG LATB<0> data output; not affected by analog input. 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input is enabled. PWM0 0 O DIG PWM Output 0. RB1 0 O DIG LATB<1> data output; not affected by analog input. 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.
PIC18F2331/2431/4331/4431 TABLE 11-4: Name PORTB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 57 LATB LATB Data Output Register 57 TRISB PORTB Data Direction Register 57 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE INTCON2 RBPU INTEDG0 INTEDG1 INTCON3 INT2IP INT1IP — Legend: RBIE TMR0IF INT0IF RBIF 54 INTEDG2 — TMR0IP — RBIP 54 INT2IE INT1IE — INT2IF INT1IF 54
PIC18F2331/2431/4331/4431 11.3 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped.
PIC18F2331/2431/4331/4431 TABLE 11-5: Pin PORTC I/O SUMMARY Function TRIS Setting I/O I/O Type RC0 0 O DIG 1 I ST x O ANA RC0/T1OSO/ T1CKI T1OSO RC1/T1OSI/ CCP2/FLTA RC2/CCP1/FLTB RC3/T0CKI/ T5CKI/INT0 RC4/INT1/SDI/ SDA 1 I ST Timer1/Timer3 counter input. 0 O DIG LATC<1> data output. 1 I ST T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator is enabled. Disables digital I/O. CCP2 0 O DIG CCP2 compare and PWM output; takes priority over port data.
PIC18F2331/2431/4331/4431 TABLE 11-5: PORTC I/O SUMMARY (CONTINUED) Pin Function TRIS Setting I/O I/O Type RC7/RX/DT/SDO RC7 0 O DIG 1 I ST PORTC<7> data input. RX 1 I ST Asynchronous serial receive data input (EUSART module). DT 0 O DIG Synchronous serial data output (EUSART module); takes priority over port data. 1 I ST Synchronous serial data input (EUSART module). User must configure as an input. 0 O DIG SPI data out; takes priority over port data.
PIC18F2331/2431/4331/4431 11.4 Note: PORTD, TRISD and LATD Registers PORTD is only available on PIC18F4331/ 4431 devices. PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin).
PIC18F2331/2431/4331/4431 TABLE 11-7: Pin PORTD I/O SUMMARY Function TRIS Setting I/O I/O Type RD0 0 O DIG LATD<0> data output. 1 I ST PORTD<0> data input. T0CKI(1) 1 I ST Timer0 alternate clock input. T5CKI(1) 1 I ST Timer5 alternate clock input. RD1 0 O DIG LATD<1> data output. 1 I ST PORTD<1> data input. SDO(1) 0 O DIG SPI data out; takes priority over port data. RD2 0 O DIG LATD<2> data output.
PIC18F2331/2431/4331/4431 11.5 PORTE, TRISE and LATE Registers Note: PORTE is only available on PIC18F4331/ 4431 devices. PORTE is a 4-bit wide, bidirectional port. Three pins (RE0/AN6, RE1/AN7 and RE2/AN8) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as ‘0’s. The corresponding Data Direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e.
PIC18F2331/2431/4331/4431 TABLE 11-9: PORTE I/O SUMMARY Pin Function TRIS Setting I/O I/O Type RE0 0 O DIG 1 I ST AN6 1 I ANA A/D Input Channel 6. Default input configuration on POR. RE1 0 O DIG LATE<1> data output; not affected by analog input. 1 I ST AN7 1 I ANA A/D Input Channel 7. Default input configuration on POR. RE2 0 O DIG LATE<2> data output; not affected by analog input. 1 I ST PORTE<2> data input; disabled when analog input is enabled.
PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 126 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 12.
PIC18F2331/2431/4331/4431 FIGURE 12-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 1 Programmable Prescaler T0CKI pin T0SE T0CS 0 Sync with Internal Clocks (2 TCY Delay) 8 3 T0PS<2:0> 8 PSA Note: Set TMR0IF on Overflow TMR0L Internal Data Bus Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
PIC18F2331/2431/4331/4431 12.1 12.2.1 Timer0 Operation Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting the T0CS bit.
PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 130 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 13.0 TIMER1 MODULE The Timer1 timer/counter module has the following features: • 16-bit timer/counter (two 8-bit registers; TMR1H and TMR1L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • Reset from CCP module Special Event Trigger • Status of system clock operation Figure 13-1 is a simplified block diagram of the Timer1 module.
PIC18F2331/2431/4331/4431 13.1 When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator, if enabled. Timer1 Operation Timer1 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2/FLTA and RC0/T1OSO/ T1CKI pins become inputs.
PIC18F2331/2431/4331/4431 13.2 Timer1 Oscillator 13.3 A crystal oscillator circuit is built in-between pins, T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated for 32 kHz crystals. It will continue to run during all power-managed modes. The circuit for a typical LP oscillator is shown in Figure 13-3. Table 13-1 shows the capacitor selection for the Timer1 oscillator.
PIC18F2331/2431/4331/4431 13.4 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow, which is latched in Timer1 Interrupt Flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>). 13.
PIC18F2331/2431/4331/4431 EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 0x80 TMR1H TMR1L b'00001111' T1CON secs mins .12 hours PIE1, TMR1IE BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN MOVLW MOVWF RETURN TMR1H, 7 PIR1, TMR1IF secs, F .
PIC18F2331/2431/4331/4431 14.0 TIMER2 MODULE 14.1 The Timer2 module has the following features: • • • • • • • 8-bit Timer register (TMR2) 8-bit Period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match with PR2 SSP module optional use of TMR2 output to generate clock shift Timer2 has a control register, shown in Register 14-1.
PIC18F2331/2431/4331/4431 14.2 Timer2 Interrupt 14.3 Output of TMR2 Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The unscaled output of TMR2 is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode.
PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 138 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 15.
PIC18F2331/2431/4331/4431 FIGURE 15-1: TIMER5 BLOCK DIAGRAM (16-BIT READ/WRITE MODE SHOWN) 1 Noise Filter T5CKI Internal Data Bus 1 FOSC/4 Internal Clock Synchronize Detect Prescaler 1, 2, 4, 8 0 0 2 Sleep Input Timer5 On/Off TMR5CS T5PS<1:0> T5SYNC TMR5ON 8 8 TMR5H 8 Write TMR5L Read TMR5L Special Event Trigger Input from IC1 Timer5 Reset (external) 8 TMR5 1 TMR5L Timer5 Reset 16 0 Reset Logic Comparator 16 PR5 8 PR5L Set TMR5IF Special Event Trigger Output 15.
PIC18F2331/2431/4331/4431 In Synchronous Counter mode configuration, the timer is clocked by the external clock (T5CKI) with the optional prescaler. The external T5CKI is selected by setting the TMR5CS bit (TMR5CS = 1); the internal clock is selected by clearing TMR5CS. The external clock is synchronized to the internal clock by clearing the T5SYNC bit. The input on T5CKI is sampled on every Q2 and Q4 of the internal clock.
PIC18F2331/2431/4331/4431 15.4 Noise Filter The Timer5 module includes an optional input noise filter, designed to reduce spurious signals in noisy operating environments. The filter ensures that the input is not permitted to change until a stable value has been registered for three consecutive sampling clock cycles. The noise filter is part of the input filter network associated with the Motion Feedback Module (see Section 17.0 “Motion Feedback Module”).
PIC18F2331/2431/4331/4431 TABLE 15-1: Name INTCON REGISTERS ASSOCIATED WITH TIMER5 Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 54 IPR3 — — — PTIP IC3DRIP IC2QEIP IC1IP TMR5IP 56 PIE3 — — — PTIE IC3DRIE IC2QEIE IC1IE TMR5IE 56 — — — PTIF IC3DRIF IC2QEIF IC1IF TMR5IF 56 PIR3 TMR5H Timer5 Register High Byte 57 TMR5L TImer5 Register Low Byte 57 PR5H Timer5 Period Register High Byt
PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 144 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 16.0 CAPTURE/COMPARE/PWM (CCP) MODULES TABLE 16-1: The CCP (Capture/Compare/PWM) module contains a 16-bit register that can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. Table 16-1 shows the timer resources required for each of the CCP module modes. The operation of CCP1 is identical to that of CCP2, with the exception of the Special Event Trigger.
PIC18F2331/2431/4331/4431 16.3 16.3.3 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following: • • • • every falling edge every rising edge every 4th rising edge every 16th rising edge CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: 16.3.
PIC18F2331/2431/4331/4431 16.4 16.4.2 Compare Mode TIMER1 MODE SELECTION In Compare mode, the 16-bit CCPR1 (CCPR2) register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/ CCP1 (RC1/CCP2) pin: Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. • • • • 16.4.
PIC18F2331/2431/4331/4431 TABLE 16-2: Name INTCON REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1 Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 54 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 57 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 57 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 57 IPR1 TRISC PORTC Data Direction Register 57 TMR1L Timer1 Register Low Byte 5
PIC18F2331/2431/4331/4431 16.5 16.5.1 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. Note: Figure 16-3 shows a simplified block diagram of the CCP1 module in PWM mode.
PIC18F2331/2431/4331/4431 The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the following equation: 16.5.3 EQUATION 16-3: 4.
PIC18F2331/2431/4331/4431 17.0 MOTION FEEDBACK MODULE The Motion Feedback Module (MFM) is a special purpose peripheral designed for motion feedback applications. Together with the Power Control PWM (PCPWM) module (see Section 18.0 “Power Control PWM Module”), it provides a variety of control solutions for a wide range of electric motors.
PIC18F2331/2431/4331/4431 FIGURE 17-1: MOTION FEEDBACK MODULE BLOCK DIAGRAM Special Event Trigger Reset TMR5IF TMR5 Reset Control Timer Reset Special Event Trigger Output Timer5 TMR5<15:0> 8 Filter Data Bus<7:0> TCY T5CKI 3x Input Capture Logic Filter Prescaler IC3 Filter CAP2/QEA Prescaler IC2 Filter CAP1/INDX Prescaler TMR5<15:0> CAP3/QEB TCY IC3IF 8 IC2IF IC1 Clock Divider 8 IC1IF Special Event Trigger Reset 8 8 Postscaler QEB Velocity Event Timer Reset QEA 8 Direction
PIC18F2331/2431/4331/4431 17.
PIC18F2331/2431/4331/4431 FIGURE 17-3: INPUT CAPTURE BLOCK DIAGRAM FOR IC2 AND IC3 CAPxBUF(1,2,3) CAP2/3 Pin Noise Filter Prescaler 1, 4, 16 and Mode Select Capture Clock TMR5 Enable 3 FLTCK<2:0> 4 CAP1M<3:0>(1) Q Clocks TMR5 ICxIF(1) Capture Clock/ Reset/ Interrupt Decode Logic Q Clocks CAPxBUF_clk(1) Reset Timer Reset Control TMR5 Reset CAPxM<3:0>(1) CAPxREN(2) Note 1: IC2 and IC3 are denoted as x = 2 and 3. 2: CAP2BUF is enabled as POSCNT when QEI mode is active.
PIC18F2331/2431/4331/4431 The three input capture channels are controlled through the Input Capture Control registers, CAP1CON, CAP2CON and CAP3CON. Each channel is configured independently with its dedicated register. The implementation of the registers is identical except for the Special Event Trigger (see Section 17.1.8 “Special Event Trigger (CAP1 Only)”). The typical Capture Control register is shown in Register 17-1.
PIC18F2331/2431/4331/4431 When in Counter mode, the counter must be configured as the synchronous counter only (T5SYNC = 0). When configured in Asynchronous mode, the IC module will not work properly. Note 1: Input capture prescalers are reset (cleared) when the input capture module is disabled (CAPxM = 0000). 2: When the Input Capture mode is changed, without first disabling the module and entering the new Input Capture mode, a false interrupt (or Special Event Trigger on IC1) may be generated.
PIC18F2331/2431/4331/4431 17.1.2 PERIOD MEASUREMENT MODE The Period Measurement mode is selected by setting CAPxM<3:0> = 0101. In this mode, the value of Timer5 is latched into the CAPxBUF register on the rising edge of the input capture trigger and Timer5 is subsequently reset to 0000h (optional by setting CAPxREN = 1) on the next TCY (see capture and Reset relationship in Figure 17-4). 17.1.3 Timer5 is always reset on the edge when the measurement is first initiated.
PIC18F2331/2431/4331/4431 17.1.3.1 Pulse-Width Measurement Timing 17.1.4 Pulse-width measurement accuracy can only be ensured when the pulse-width high and low present on the CAPx input exceeds one TCY clock cycle. The limitations depend on the mode selected: INPUT CAPTURE ON STATE CHANGE When CAPxM<3:0> = 1000, the value is captured on every signal change on the CAPx input.
PIC18F2331/2431/4331/4431 17.1.5 ENTERING INPUT CAPTURE MODE AND CAPTURE TIMING 17.1.6 Every input capture trigger can optionally reset (TMR5). The Capture Reset Enable bit, CAPxREN, gates the automatic Reset of the time base of the capture event with this enable Reset signal. All capture events reset the selected timer when CAPxREN is set. Resets are disabled when CAPxREN is cleared (see Figure 17-4, Figure 17-5 and Figure 17-6).
PIC18F2331/2431/4331/4431 17.1.8 SPECIAL EVENT TRIGGER (CAP1 ONLY) 17.1.9 The Special Event Trigger mode of IC1 (CAP1M<3:0> = 1110 or 1111) enables the Special Event Trigger signal. The trigger signal can be used as the Special Event Trigger Reset input to TMR5, resetting the timer when the specific event happens on IC1. The events are summarized in Table 17-2. TABLE 17-2: SPECIAL EVENT TRIGGER CAP1M<3:0> Description 1110 The trigger occurs on every falling edge on the CAP1 input.
PIC18F2331/2431/4331/4431 Quadrature Encoder Interface The Quadrature Encoder Interface (QEI) decodes speed and motion sensor information. It can be used in any application that uses a quadrature encoder for feedback.
PIC18F2331/2431/4331/4431 17.2.1 QEI CONFIGURATION The operation of the QEI is controlled by the QEICON Configuration register (see Register 17-2). The QEI module shares its input pins with the Input Capture (IC) module. The inputs are mutually exclusive; only the IC module or the QEI module (but not both) can be enabled at one time. Also, because the IC and QEI are multiplexed to the same input pins, the programmable noise filters can be dedicated to one module only.
PIC18F2331/2431/4331/4431 17.2.2 QEI MODES 17.2.3 Position measurement resolution depends on how often the Position Counter register, POSCNT, is incremented. There are two QEI Update modes to measure the rotor’s position: QEI x2 and QEI x4. TABLE 17-4: QEI MODES QEIM<2:0> Mode/ Reset 000 — 001 010 Description QEI disabled.(1) x2 update/ Two clocks per QEA index pulse pulse. INDX resets POSCNT. x2 update/ Two clocks per QEA pulse. period POSCNT is reset by the match period match (MAXCNT).
PIC18F2331/2431/4331/4431 17.2.3.3 Reset and Update Events The position counter will continue to increment or decrement until one of the following events takes place. The type of event and the direction of rotation when it happens determines if a register Reset or update occurs. 1. An index pulse is detected on the INDX input (QEIM<2:0> = 001). If the encoder is traveling in the forward direction, POSCNT is reset (00h) on the next clock edge after the index marker, INDX, has been detected.
PIC18F2331/2431/4331/4431 FIGURE 17-9: QEI INPUTS WHEN SAMPLED BY THE FILTER (DIVIDE RATIO = 1:1) TCY QEA Pin TQEI = 16 TCY(1) QEB Pin QEA Input TGD = 3 TCY QEB Input Note 1: The module design allows a quadrature frequency of up to FQEI = FCY/16.
PIC18F2331/2431/4331/4431 FIGURE 17-11: QEI MODULE RESET TIMING WITH THE INDEX INPUT Forward Reverse Note 2 Note 2 QEA QEB Count (+/-) -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 MAXCNT 1515 1514 1517 1516 1519 1518 1520 1522 1521 1525 1524 1523 1527 1526 0001 0000 0002 0003 0004 0003 0000 0001 0002 1526 1527 1524 1525 1521 1522 1523 1520 POSCNT(1) MAXCNT = 1527 INDX Note 6 IC2QEIF UP/DOWN Q4(3) Position Counter Load
PIC18F2331/2431/4331/4431 17.2.6 17.2.6.1 VELOCITY MEASUREMENT The velocity pulse generator, in conjunction with the IC1 and the synchronous TMR5 (in synchronous operation), provides a method for high accuracy speed measurements at both low and high mechanical motor speeds. The Velocity mode is enabled when the VELM bit is cleared (= 0) and QEI is set to one of its operating modes (see Table 17-6). The event pulses are reduced by a fixed ratio by the velocity pulse divider.
PIC18F2331/2431/4331/4431 FIGURE 17-13: VELOCITY MEASUREMENT TIMING(1) Forward Reverse QEA QEB vel_out velcap VELR(2) Old Value 1529 0003 0004 0001 0002 0008 0009 0000 0006 0007 0005 0003 0004 0001 0002 0000 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1525 1526 1523 1524 1522 1520 1521 TMR5(2) 1537 cnt_reset(3) Q1 Q1 Q1 IC1IF(4) CAP1REN Instr.
PIC18F2331/2431/4331/4431 17.3 Noise Filters The Motion Feedback Module includes three noise rejection filters on RA2/AN2/VREF-/CAP1/INDX, RA3/AN3/VREF+/CAP2/QEA and RA4/AN4/CAP3/QEB. The filter block also includes a fourth filter for the T5CKI pin. They are intended to help reduce spurious noise spikes which may cause the input signals to become corrupted at the inputs.
PIC18F2331/2431/4331/4431 FIGURE 17-14: NOISE FILTER TIMING DIAGRAM (CLOCK DIVIDER = 1:1) TQEI = 16 TCY TCY Noise Glitch(3) Noise Glitch(3) Pin(1) CAP1/INDX (input to filter) CAP1/INDX Input(2) (output from filter) TGD = 3 TCY Note 1: 17.4 Only the CAP1/INDX pin input is shown for simplicity. Similar event timing occurs on the CAP2/QEA and CAP3/QEB pins. 2: Noise filtering occurs in the shaded portions of the CAP1 input. 3: Filter’s group delay: TGD = 3 TCY.
PIC18F2331/2431/4331/4431 TABLE 17-8: Name INTCON REGISTERS ASSOCIATED WITH THE MOTION FEEDBACK MODULE Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 Bit 6 GIE/GIEH PEIE/GIEL IPR3 — — — PTIP IC3DRIP IC2QEIP IC1IP TMR5IP 56 PIE3 — — — PTIE IC3DRIE IC2QEIE IC1IE TMR5IE 56 — — — PTIF IC3DRIF IC2QEIF IC1IF TMR5IF 56 PIR3 TMR5H Timer5 Register High Byte 57 TMR5L Timer5 Register Low Byte 57 PR5H Timer5 Per
PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 172 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 18.0 POWER CONTROL PWM MODULE The Power Control PWM module simplifies the task of generating multiple, synchronized Pulse-Width Modulated (PWM) outputs for use in the control of motor controllers and power conversion applications.
PIC18F2331/2431/4331/4431 FIGURE 18-1: POWER CONTROL PWM MODULE BLOCK DIAGRAM Internal Data Bus 8 PWMCON0 PWM Enable and Mode 8 PWMCON1 8 DTCON Dead-Time Control 8 FLTCONFIG Fault Pin Control 8 OVDCON PWM Manual Control PWM Generator #3(1) 8 PDC3 Buffer PDC3 Comparator 8 PWM Generator 2 PTMR Channel 3 Dead-Time Generator and Override Logic(2) PWM7(2) Channel 2 Dead-Time Generator and Override Logic PWM5 Comparator PWM Generator 1 PTPER PWM Generator 0 8 PTPER Buffer Channel 1
PIC18F2331/2431/4331/4431 FIGURE 18-2: PWM MODULE BLOCK DIAGRAM, ONE OUTPUT PAIR, COMPLEMENTARY MODE VDD Dead-Band Generator PWM1 Duty Cycle Comparator HPOL PWM Duty Cycle Register PWM0 LPOL Fault Override Values Channel Override Values Fault A Pin Fault Pin Assignment Logic Fault B Pin Note: In Complementary mode, the even channel cannot be forced active by a Fault or override event when the odd channel is active.
PIC18F2331/2431/4331/4431 18.1 Control Registers The operation of the PWM module is controlled by a total of 22 registers.
PIC18F2331/2431/4331/4431 FIGURE 18-4: PWM TIME BASE BLOCK DIAGRAM PTMR Register PTMR Clock Timer Reset Up/Down Comparator Zero Match Period Match Comparator PTMOD1 Timer Direction Control PTDIR Duty Cycle Load PTPER Period Load PTPER Buffer Update Disable (UDIS) FOSC/4 Prescaler 1:1, 1:4, 1:16, 1:64 Zero Match Zero Match Period Match PTMOD1 PTMOD0 Clock Control PTMR Clock PTEN Postscaler 1:1-1:16 Interrupt Control PTIF Period Match PTMOD1 PTMOD0 The PWM time base can be configured for
PIC18F2331/2431/4331/4431 REGISTER 18-1: PTCON0: PWM TIMER CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 PTOPS<3:0>: PWM Time Base Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale . . .
PIC18F2331/2431/4331/4431 REGISTER 18-3: U-0 — PWMCON0: PWM CONTROL REGISTER 0 R/W-1(1) R/W-1(1) PWMEN2 PWMEN1 R/W-1(1) PWMEN0 R/W-0 (3) PMOD3 R/W-0 R/W-0 R/W-0 PMOD2 PMOD1 PMOD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 PWMEN<2:0>: PWM Module Enable bits(1) 111 = All odd PWM I/O pins are enabled for PWM output(2) 110 =
PIC18F2331/2431/4331/4431 REGISTER 18-4: PWMCON1: PWM CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR — UDIS OSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale . . .
PIC18F2331/2431/4331/4431 18.3.5 Table 18-1 shows the minimum PWM frequencies that can be generated with the PWM time base and the prescaler. An operating frequency of 40 MHz (FCYC = 10 MHz) and PTPER = 0xFFF is assumed in the table. The PWM module must be capable of generating PWM signals at the line frequency (50 Hz or 60 Hz) for certain power control applications.
PIC18F2331/2431/4331/4431 18.4.2 INTERRUPTS IN SINGLE-SHOT MODE 18.4.3 When the PWM time base is in the Single-Shot mode (PTMOD<1:0> = 01), an interrupt event is generated when a match with the PTPER register occurs. The PWM Time Base register (PTMR) is reset to zero on the following input clock edge and the PTEN bit is cleared. The postscaler selection bits have no effect in this Timer mode.
PIC18F2331/2431/4331/4431 FIGURE 18-7: PWM TIME BASE INTERRUPT, CONTINUOUS UP/DOWN COUNT MODE A: PRESCALER = 1:1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FOSC/4 PTMR 002h 001h 000h 001h 002h PTDIR bit PTMR_INT_REQ 1 1 1 1 PTIF bit B: PRESCALER = 1:4 Qc Qc Q4 Qc Qc Qc 002h PTMR Qc Qc Qc Qc 001h Q4 Qc Qc Qc Qc Qc Qc 001h 000h Qc Qc Qc Qc Qc 002h PTDIR bit 1 1 PTMR_INT_REQ 1 1 PTIF bit Note 1: Interrupt flag bit, PTIF, is sam
PIC18F2331/2431/4331/4431 18.4.4 INTERRUPTS IN DOUBLE UPDATE MODE Note: This mode is available in Continuous Up/Down Count mode. In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero and each time the PTMR matches with PTPER register. Figure 18-8 shows the interrupts in Continuous Up/Down Count mode with double updates. Do not change the PTMOD bits while PTEN is active; it will yield unexpected results.
PIC18F2331/2431/4331/4431 18.5 PWM Period The PWM period is defined by the PTPER register pair (PTPERL and PTPERH). The PWM period has 12-bit resolution by combining 4 LSBs of PTPERH and 8 bits of PTPERL. PTPER is a double-buffered register used to set the counting period for the PWM time base.
PIC18F2331/2431/4331/4431 FIGURE 18-9: PWM PERIOD BUFFER UPDATES IN FREE-RUNNING MODE Period Value Loaded from PTPER Register 7 New PTPER Value = 007 6 5 4 Old PTPER Value = 004 4 3 4 3 3 2 2 2 1 1 1 0 0 0 New Value Written to PTPER Register FIGURE 18-10: PWM PERIOD BUFFER UPDATES IN CONTINUOUS UP/DOWN COUNT MODE Period Value Loaded from PTPER Register 7 New PTPER Value = 007 6 5 4 Old PTPER Value = 004 3 2 1 0 4 3 3 2 2 1 1 0 6 5 4 3 2 1 0 New Value Written to PTPER Register
PIC18F2331/2431/4331/4431 18.6 PWM Duty Cycle PWM duty cycle is defined by the PDCx (PDCxL and PDCxH) registers. There are a total of four PWM Duty Cycle registers for four pairs of PWM channels. The Duty Cycle registers have 14-bit resolution by combining six LSbs of PDCxH with the 8 bits of PDCxL. PDCx is a double-buffered register used to set the counting period for the PWM time base. 18.6.
PIC18F2331/2431/4331/4431 18.6.2 DUTY CYCLE REGISTER BUFFERS The four PWM Duty Cycle registers are double-buffered to allow glitchless updates of the PWM outputs. For each duty cycle block, there is a Duty Cycle Buffer register that is accessible by the user and a second Duty Cycle register that holds the actual compare value used in the present PWM period.
PIC18F2331/2431/4331/4431 FIGURE 18-14: DUTY CYCLE UPDATE TIMES IN CONTINUOUS UP/DOWN COUNT MODE WITH DOUBLE UPDATES Duty Cycle Value Loaded from Buffer Register PWM Output PTMR Value New Values Written to Duty Cycle Buffer 18.6.4 CENTER-ALIGNED PWM Center-aligned PWM signals are produced by the module when the PWM time base is configured in a Continuous Up/Down Count mode (see Figure 18-15).
PIC18F2331/2431/4331/4431 PWM5 3-Phase Load PWM4 PWM3 Each upper/lower power switch pair is fed by a complementary PWM signal. Dead time may be optionally inserted during device switching, where both outputs are inactive for a short period (see Section 18.7 “Dead-Time Generators”). TYPICAL LOAD FOR COMPLEMENTARY PWM OUTPUTS +V PWM2 The Complementary mode of PWM operation is useful to drive one or more power switches in half-bridge configuration as shown in Figure 18-16.
PIC18F2331/2431/4331/4431 18.7 18.7.1 Dead-Time Generators In power inverter applications, where the PWMs are used in Complementary mode to control the upper and lower switches of a half-bridge, a dead-time insertion is highly recommended. The dead-time insertion keeps both outputs in inactive state for a brief time. This avoids any overlap in the switching during the state change of the power devices due to TON and TOFF characteristics.
PIC18F2331/2431/4331/4431 REGISTER 18-5: DTCON: DEAD-TIME CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTPS1 DTPS0 DT5 DT4 DT3 DT2 DT1 DT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 DTPS<1:0>: Dead-Time Unit A Prescale Select bits 11 = Clock source for dead-time unit is FOSC/16 10 = Clock source for dead-time unit is FOSC/8 01 = Clock source for dead-ti
PIC18F2331/2431/4331/4431 The actual dead time is calculated from the DTCON register as follows: Dead Time = Dead-Time Value/(FOSC/Prescaler) Table 18-3 shows example dead-time ranges as a function of the input clock prescaler selected and the device operating frequency. TABLE 18-3: EXAMPLE DEAD-TIME RANGES Prescaler Dead-Time Dead-Time FOSC MIPS (MHz) Selection Min Max 40 10 FOSC/2 50 ns 3.2 s 40 10 FOSC/4 100 ns 6.4 s 40 10 FOSC/8 200 ns 12.8 s 40 10 FOSC/16 400 ns 25.
PIC18F2331/2431/4331/4431 18.8.2 PWM CHANNEL OVERRIDE PWM output may be manually overridden for each PWM channel by using the appropriate bits in the OVDCOND and OVDCONS registers. The user may select the following signal output options for each PWM output pin operating in the Independent PWM mode: • I/O pin outputs PWM signal • I/O pin inactive • I/O pin active Refer to Section 18.10 “PWM Output Override” for details for all the override functions.
PIC18F2331/2431/4331/4431 FIGURE 18-20: PWM OVERRIDE BITS IN COMPLEMENTARY MODE 1 POUT0 POUT1 4 5 3 6 PWM1 2 PWM0 7 Assume: POVD0 = 0; POVD1 = 0; PMOD0 = 0 1. 2. 3. 4. 5. 6. 7. Even override bits have no effect in Complementary mode. Odd override bit is activated, which causes the even PWM to deactivate. Dead-time insertion. Odd PWM activated after the dead time. Odd override bit is deactivated, which causes the odd PWM to deactivate. Dead-time insertion. Even PWM is activated after the dead time.
PIC18F2331/2431/4331/4431 18.10.3 OUTPUT OVERRIDE EXAMPLES Figure 18-21 shows an example of a waveform that might be generated using the PWM output override feature. The figure shows a six-step commutation sequence for a BLDC motor. The motor is driven through a 3-phase inverter as shown in Figure 18-16. When the appropriate rotor position is detected, the PWM outputs are switched to the next commutation state in the sequence. In this example, the PWM outputs are driven to specific logic states.
PIC18F2331/2431/4331/4431 FIGURE 18-21: 1 PWM OUTPUT OVERRIDE EXAMPLE #1 2 3 4 5 FIGURE 18-22: 6 PWM OUTPUT OVERRIDE EXAMPLE #2 1 2 3 4 PWM5 PWM4 PWM7 PWM3 PWM2 PWM6 PWM1 PWM0 PWM5 PWM4 TABLE 18-4: State PWM OUTPUT OVERRIDE EXAMPLE #1 PWM3 OVDCOND (POVD) OVDCONS (POUT) 1 00000000b 00100100b 2 00000000b 00100001b 3 00000000b 00001001b 4 00000000b 00011000b 5 00000000b 00010010b 6 00000000b 00000110b TABLE 18-5: PWM2 PWM1 PWM0 PWM OUTPUT OVERRIDE EXAMPLE #2 State O
PIC18F2331/2431/4331/4431 18.11 PWM Output and Polarity Control 18.11.2 There are three device Configuration bits associated with the PWM module that provide PWM output pin control defined in the CONFIG3L Configuration register. They are: The polarity of the PWM I/O pins is set during device programming via the HPOL and LPOL Configuration bits in the CONFIG3L Configuration register. The HPOL Configuration bit sets the output polarity for the high side PWM outputs: PWM1, PWM3, PWM5 and PWM7.
PIC18F2331/2431/4331/4431 18.11.3 PWM OUTPUT PIN RESET STATES The PWMPIN Configuration bit determines the PWM output pins to be PWM output pins or digital I/O pins, after the device comes out of Reset. If the PWMPIN Configuration bit is unprogrammed (default), the PWMEN<2:0> control bits will be cleared on a device Reset. Consequently, all PWM outputs will be tri-stated and controlled by the corresponding PORT and TRIS registers.
PIC18F2331/2431/4331/4431 18.12.3 PWM OUTPUTS WHILE IN FAULT CONDITION While in the Fault state (i.e., one or both FLTA and FLTB inputs are active), the PWM output signals are driven into their inactive states. The selection of which PWM outputs are deactivated (while in the Fault state) is determined by the FLTCON bit in the FLTCONFIG register as follows: • FLTCON = 1: When FLTA or FLTB is asserted, the PWM outputs (i.e., PWM<7:0>) are driven into their inactive state.
PIC18F2331/2431/4331/4431 REGISTER 18-8: R/W-0 BRFEN FLTCONFIG: FAULT CONFIGURATION REGISTER R/W-0 (1) FLTBS R/W-0 R/W-0 (1) FLTBMOD (1) FLTBEN R/W-0 (2) FLTCON R/W-0 R/W-0 R/W-0 FLTAS FLTAMOD FLTAEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 BRFEN: Breakpoint Fault Enable bit 1 = Enable Fault condition on a breakpoint (i.e.
PIC18F2331/2431/4331/4431 18.13 PWM Update Lockout For a complex PWM application, the user may need to write up to four Duty Cycle registers and the PWM Time Base Period register, PTPER, at a given time. In some applications, it is important that all buffer registers be written before the new duty cycle and period values are loaded for use by the module. A PWM update lockout feature may optionally be enabled so the user may specify when new duty cycle buffer values are valid.
PIC18F2331/2431/4331/4431 TABLE 18-6: Name INTCON REGISTERS ASSOCIATED WITH THE POWER CONTROL PWM MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 IPR3 — — — PTIP IC3DRIP IC2QEIP IC1IP TMR5IP 56 PIE3 — — — PTIE IC3DRIE IC2QEIE IC1IE TMR5IE 56 IC3DRIF IC2QEIF IC1IF TMR5IF 56 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 58 — — — PTIF PTCON0 PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCON1 PTEN P
PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 204 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 19.0 19.1 SYNCHRONOUS SERIAL PORT (SSP) MODULE SSP Module Overview The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D Converters, etc.
PIC18F2331/2431/4331/4431 REGISTER 19-1: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must b
PIC18F2331/2431/4331/4431 REGISTER 19-2: R/W-0 WCOL bit 7 Legend: R = Readable bit -n = Value at POR bit 7 SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER R/W-0 SSPOV(1) R/W-0 SSPEN(2) W = Writable bit ‘1’ = Bit is set R/W-0 CKP R/W-0 SSPM3(3) R/W-0 SSPM2(3) R/W-0 SSPM1(3) R/W-0 SSPM0(3) bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cle
PIC18F2331/2431/4331/4431 REGISTER 19-2: SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (CONTINUED) SSPM<3:0>: Synchronous Serial Port Mode Select bits(3) 0000 = SPI Master mode, Clock = FOSC/4 0001 = SPI Master mode, Clock = FOSC/16 0010 = SPI Master mode, Clock = FOSC/64 0011 = SPI Master mode, Clock = TMR2 output/2 0100 = SPI Slave mode, Clock = SCK pin, SS pin control enabled 0101 = SPI Slave mode, Clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0110 = I2C Slave mode, 7-bit addre
PIC18F2331/2431/4331/4431 FIGURE 19-1: SSP BLOCK DIAGRAM (SPI MODE) Internal Data Bus Read Write SSPBUF Reg • Serial Data Out (SDO) – RC7/RX/DT/SDO or RD1/SDO • SDI must have TRISC<4> or TRISD<2> set • SDO must have TRISC<7> or TRISD<1> cleared • SCK (Master mode) must have TRISC<5> or TRISD<3> cleared • SCK (Slave mode) must have TRISC<5> or TRISD<3> set • SS must have TRISA<6> set SSPSR Reg SDI SDO Shift Clock bit 0 Peripheral OE SS Control Enable SS Note 1: When the SPI is in Slave mode, with th
PIC18F2331/2431/4331/4431 FIGURE 19-2: SPI MODE TIMING, MASTER MODE SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 SDI (SMP = 1) bit 0 bit 7 SSPIF FIGURE 19-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) SS (optional) SCK (CKP = 0) SCK (CKP = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 SSPIF DS39616D-page 210 2010 Micr
PIC18F2331/2431/4331/4431 FIGURE 19-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) SS SCK (CKP = 0) SCK (CKP = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 SSPIF TABLE 19-1: Name INTCON PIR1 PIE1 REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 GIE/GIEH PEIE/GIEL TMR0IE — ADIF RCIF — ADIE RCIE TRISC PORTC Data Direction Register SSPBUF SSP Receive Buffer/Transmit Register SSPCON TRISA SSPSTAT WCOL (1) TRISA7 SMP SSPOV TRISA
PIC18F2331/2431/4331/4431 19.3 SSP I2 C Operation The SSP module, in I2C mode, fully implements all slave functions except general call support and provides interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the SCK/ SCL pin, which is the clock (SCL), and the SDI/SDA pin, which is the data (SDA).
PIC18F2331/2431/4331/4431 19.3.1.1 Addressing Once the SSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse.
PIC18F2331/2431/4331/4431 19.3.1.2 Reception When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON<6>) is set. This is an error condition due to the user’s firmware. When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register.
PIC18F2331/2431/4331/4431 19.3.1.3 Transmission An SSP interrupt is generated for each data transfer byte. Flag bit, SSPIF, must be cleared in software and the SSPSTAT register is used to determine the status of the byte. Flag bit, SSPIF, is set on the falling edge of the ninth clock pulse. When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register.
PIC18F2331/2431/4331/4431 19.3.2 MASTER MODE 19.3.3 Master mode of operation is supported in firmware using interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle and both the S and P bits are clear.
PIC18F2331/2431/4331/4431 20.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The operation of the Enhanced USART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • Baud Rate Control (BAUDCON) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of the two serial I/O modules available in the PIC18F2331/ 2431/4331/4431 family of microcontrollers.
PIC18F2331/2431/4331/4431 REGISTER 20-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
PIC18F2331/2431/4331/4431 REGISTER 20-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled 0 = Serial port disabled bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 =
PIC18F2331/2431/4331/4431 REGISTER 20-3: BAUDCON: BAUD RATE CONTROL REGISTER U-0 R-1 U-0 R/W-1 R/W-0 U-0 R/W-0 R/W-0 — RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receiver is Idle 0 = Receive in progress bit 5 Unimplemented: Read as ‘0’ bit 4
PIC18F2331/2431/4331/4431 20.2 20.2.1 EUSART Baud Rate Generator (BRG) The BRG is a dedicated 8-bit or 16-bit generator, that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit (BAUDCON<3>) selects 16-bit mode. The SPBRGH:SPBRG register pair controls the period of a free-running timer. In Asynchronous mode, bits BRGH (TXSTA<2>) and BRG16 also control the baud rate. In Synchronous mode, bit BRGH is ignored.
PIC18F2331/2431/4331/4431 EXAMPLE 20-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1)) Solving for SPBRGH:SPBRG: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.
PIC18F2331/2431/4331/4431 TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) FOSC = 10.000 MHz Actual Rate (K) % Error SPBRG value (decimal) FOSC = 8.000 MHz Actual Rate (K) % Error SPBRG value (decimal) 2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.
PIC18F2331/2431/4331/4431 TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error 0.00 33332 0.300 0.00 8332 1.200 2.400 0.02 4165 9.6 9.606 0.06 19.2 19.193 57.6 57.803 115.2 114.943 FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error 0.00 16665 0.300 0.02 4165 1.200 2.400 0.02 2082 1040 9.596 -0.03 -0.03 520 19.231 0.
PIC18F2331/2431/4331/4431 20.2.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 20-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. This allows the user to verify that no carry occurred for 8bit modes by checking for 00h in the SPBRGH register.
PIC18F2331/2431/4331/4431 20.3 EUSART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTA<4>). In this mode, the EUSART uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The EUSART transmits and receives the LSb first.
PIC18F2331/2431/4331/4431 FIGURE 20-2: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXIE 8 MSb LSb (8) Pin Buffer and Control 0 TSR Register RC6/TX/CK/SS Pin Interrupt TXEN Baud Rate CLK TRMT BRG16 SPBRGH SPEN SPBRG TX9 Baud Rate Generator TX9D FIGURE 20-3: Write to TXREG BRG Output (Shift Clock) ASYNCHRONOUS TRANSMISSION Word 1 RC6/TX/CK/SS (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Interrupt Reg. Flag) TRMT bit (Transmit Shift Reg.
PIC18F2331/2431/4331/4431 TABLE 20-5: Name INTCON REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 57 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 57 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 57 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 56 IPR1 RCSTA TXREG TXSTA EUSART
PIC18F2331/2431/4331/4431 20.3.2 EUSART ASYNCHRONOUS RECEIVER 20.3.3 The receiver block diagram is shown in Figure 20-5. The data is received on the RC7/RX/DT/SDO pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
PIC18F2331/2431/4331/4431 To set up an Asynchronous Transmission: 1. 2. 3. 4. 5. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit, BRGH (see Section 20.2 “EUSART Baud Rate Generator (BRG)”). Enable the asynchronous serial port by clearing bit, SYNC, and setting bit, SPEN. If interrupts are desired, set enable bit, TXIE. If 9-bit transmission is desired, set transmit bit, TX9. Can be used as address/data bit. FIGURE 20-6: 6. 7.
PIC18F2331/2431/4331/4431 20.3.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RX/DT line, while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCON<1>).
PIC18F2331/2431/4331/4431 20.3.5 BREAK CHARACTER SEQUENCE The Enhanced USART module has the capability of sending the special Break character sequences that are required by the LIN/J2602 bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set while the Transmit Shift register is loaded with data.
PIC18F2331/2431/4331/4431 20.4 Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG is empty and interrupt bit, TXIF (PIR1<4>), is set. The interrupt can be enabled/disabled by setting/clearing enable bit, TXIE (PIE1<4>). Flag bit, TXIF, will be set, regardless of the state of enable bit, TXIE, and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register.
PIC18F2331/2431/4331/4431 FIGURE 20-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT/SDO Pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX/CK/SS Pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit TABLE 20-7: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 57 PIE1 — ADIE RC
PIC18F2331/2431/4331/4431 20.4.2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTA<5>), or the Continuous Receive Enable bit, CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT/SDO pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence.
PIC18F2331/2431/4331/4431 TABLE 20-8: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 57 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 57 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 57 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 56 IPR1 RCSTA RCREG TXSTA BAUDC
PIC18F2331/2431/4331/4431 20.5 To set up a Synchronous Slave Transmission: EUSART Synchronous Slave Mode 1. Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the RC6/TX/CK/SS pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 20.5.1 2. 3. 4. 5. 6. EUSART SYNCHRONOUS SLAVE TRANSMIT 7.
PIC18F2331/2431/4331/4431 20.5.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit SREN, which is a “don’t care” in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this Low-Power mode.
PIC18F2331/2431/4331/4431 21.0 10-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The high-speed Analog-to-Digital (A/D) Converter module allows conversion of an analog signal to a corresponding 10-bit digital number. The A/D module supports up to 5 input channels on PIC18F2331/2431 devices, and up to 9 channels on the PIC18F4331/4431 devices.
PIC18F2331/2431/4331/4431 REGISTER 21-1: ADCON0: A/D CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ACONV ACSCH ACMOD1 ACMOD0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 ACONV: Auto-Conversion Continuous Loop or Single-Shot Mode Select bit 1 = Continuous Loop mode enabled 0 = Single-Shot
PIC18F2331/2431/4331/4431 REGISTER 21-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0 R/W-0 U-0 R/W-0 R-0 R-0 R-0 R-0 VCFG1 VCFG0 — FIFOEN BFEMT BFOVL ADPNT1 ADPNT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 VCFG<1:0>: A/D VREF+ and A/D VREF- Source Selection bits 00 = VREF+ = AVDD, VREF- = AVSS (AN2 and AN3 are analog inputs or digital I/O) 01 = VREF+ = Extern
PIC18F2331/2431/4331/4431 REGISTER 21-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM ACQT3 ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6-3 ACQT<3:0>: A/D Acquisition Time Select bits 0000 = No delay (co
PIC18F2331/2431/4331/4431 REGISTER 21-4: R/W-0 ADCON3: A/D CONTROL REGISTER 3 R/W-0 ADRS1 U-0 — ADRS0 R/W-0 SSRC4 (1) R/W-0 SSRC3 (1) R/W-0 SSRC2 (1) R/W-0 SSRC1 (1) R/W-0 SSRC0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 ADRS<1:0>: A/D Result Buffer Depth Interrupt Select Control for Continuous Loop Mode bits The ADRS bits are ignored in Single-Shot mod
PIC18F2331/2431/4331/4431 REGISTER 21-5: ADCHS: A/D CHANNEL SELECT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GDSEL1 GDSEL0 GBSEL1 GBSEL0 GCSEL1 GCSEL0 GASEL1 GASEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 GDSEL<1:0>: Group D Select bits S/H-2 positive input. 00 = AN3 01 = AN7(1) 1x = Reserved bit 5-4 GBSEL<1:0>: Group B Select bits S/H-2 positive input.
PIC18F2331/2431/4331/4431 REGISTER 21-6: R/W-1 ANS7 ANSEL0: ANALOG SELECT REGISTER 0(1) R/W-1 (2) R/W-1 (2) ANS6 ANS5 (2) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANS4 ANS3 ANS2 ANS1 ANS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ANS<7:0>: Analog Input Function Select bits Correspond to pins, AN<7:0>.
PIC18F2331/2431/4331/4431 The A/D channels are grouped into four sets of 2 or 3 channels. For the PIC18F2331/2431 devices, AN0 and AN4 are in Group A, AN1 is in Group B, AN2 is in Group C and AN3 is in Group D. For the PIC18F4331/ 4431 devices, AN0, AN4 and AN8 are in Group A, AN1 and AN5 are in Group B, AN2 and AN6 are in Group C and AN3 and AN7 are in Group D. The selected channel in each group is selected by configuring the A/D Channel Select Register, ADCHS.
PIC18F2331/2431/4331/4431 21.1 Continuous Loop mode allows the defined sequence to be executed in a continuous loop when ACONV = 1. In this mode, either the user can trigger the start of conversion by setting the GO/DONE bit, or one of the A/D triggers can start the conversion. The interrupt flag, ADIF, is set based on the configuration of the bits, ADRS<1:0> (ADCON3<7:6>). In Simultaneous modes, STNM1 and STNM2 acquisition time must be configured to ensure proper conversion of the analog input signals.
PIC18F2331/2431/4331/4431 21.1.3 CONVERSION SEQUENCING The ACMOD<1:0> bits control the sequencing of the A/D conversions. When ACSCH = 0, the A/D is configured to sample and convert a single channel. The ACMOD bits select which group to perform the conversions and the GxSEL<1:0> bits select which channel in the group is to be converted. If Single-Shot mode is enabled, the A/D interrupt flag will be set after the channel is converted.
PIC18F2331/2431/4331/4431 21.2 A/D Result Buffer The A/D module has a 4-level result buffer with an address range of 0 to 3, enabled by setting the FIFOEN bit in the ADCON1 register. This buffer is implemented in a circular fashion, where the A/D result is stored in one location and the address is incremented. If the address is greater than 3, the pointer is wrapped back around to 0. The result buffer has a Buffer Empty Flag, BFEMT, indicating when any data is in the buffer.
PIC18F2331/2431/4331/4431 EXAMPLE 21-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = Negligible TCOFF = (Temp – 25°C)(0.005 s/°C) (50°C – 25°C)(0.005 s/°C) = .13 s Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 s. TC = -(CHOLD) (RIC + RSS + RS) ln(1/2047) s -(9 pF) (1 k + 6 k + 100) ln(0.0004883) s = .49 s TACQ = 0 + .49 s + .13 s = .
PIC18F2331/2431/4331/4431 21.4 A/D Voltage References If external voltage references are used instead of the internal AVDD and AVSS sources, the source impedance of the VREF+ and VREF- voltage sources must be considered. During acquisition, currents supplied by these sources are insignificant. However, during conversion, the A/D module sinks and sources current through the reference sources.
PIC18F2331/2431/4331/4431 21.7 Operation in Power-Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT<3:0> and ADCS<2:0> bits in ADCON2 should be updated in accordance with the power-managed mode clock that will be used.
PIC18F2331/2431/4331/4431 21.9 A/D Conversions Figure 21-3 shows the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. The internal A/D RC oscillator must be selected to perform a conversion in Sleep.
PIC18F2331/2431/4331/4431 21.9.1 A/D RESULT REGISTER The ADRESH:ADRESL register pair is the location where the 10-bit A/D result is loaded at the completion of the A/D conversion. This register pair is 16 bits wide. The A/D module gives the flexibility to left or right justify the 10-bit result in the 16-bit result register. The A/D FIGURE 21-5: Format Select bit (ADFM) controls this justification. Figure 21-5 shows the operation of the A/D result justification. The extra bits are loaded with ‘0’s.
PIC18F2331/2431/4331/4431 TABLE 21-3: Name INTCON SUMMARY OF A/D REGISTERS Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 54 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 57 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 57 IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 57 PIR2 OSCFIF — — EEIF — LVDIF — CCP2IF 57 PIE2 OSCFIE — — EEIE — LVDIE — CCP2IE 57 IP
PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 256 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 22.0 LOW-VOLTAGE DETECT (LVD) PIC18F2331/2431/4331/4431 devices have a LowVoltage Detect module (LVD), a programmable circuit that enables the user to specify a device voltage trip point. If the device experiences an excursion below the trip point, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. The block diagram for the LVD module is shown in Figure 22-1.
PIC18F2331/2431/4331/4431 FIGURE 22-1: VDD LVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) Externally Generated Trip Point VDD LVDCON Register LVDEN LVDIN 16-to-1 MUX LVDIN LVDL<3:0> VDIRMAG Set LVDIF LVDEN BOREN DS39616D-page 258 Internal Voltage Reference 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 22.1 Operation When the LVD module is enabled, a comparator uses an internally generated reference voltage as the set point. The set point is compared with the trip point, where each node in the resistor divider represents a trip point voltage. The “trip point” voltage is the voltage level at which the device detects a low-voltage event, depending on the configuration of the module.
PIC18F2331/2431/4331/4431 22.4 start-up time, TIRVST, is an interval that is independent of device clock speed. It is specified in electrical specification Parameter 36. LVD Start-up Time The internal reference voltage of the LVD module, specified in electrical specification Parameter D420, may be used by other internal circuitry, such as the Programmable Brown-out Reset.
PIC18F2331/2431/4331/4431 22.5 Operation During Sleep 22.7 When enabled, the LVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the LVDIF bit will be set and the device will wakeup from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. 22.6 Effects of a Reset A device Reset forces all registers to their Reset state. This forces the LVD module to be turned off.
PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 262 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 23.0 SPECIAL FEATURES OF THE CPU PIC18F2331/2431/4331/4431 devices include several features intended to maximize system reliability and minimize cost through elimination of external components.
PIC18F2331/2431/4331/4431 TABLE 23-1: CONFIGURATION BITS AND DEVICE IDs File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value 300000h CONFIG1L — — — — — — — — ---- ---- 300001h CONFIG1H IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 11-- 1111 BORV0 BOREN PWRTEN ---- 1111 WDTEN --11 1111 300002h CONFIG2L — — — — BORV1 300003h CONFIG2H — — WINEN WDTPS3 WDTPS2 300004h CONFIG3L — HPOL LPOL — T1OSCMX 300005h CONFIG3H MCLRE(1) — —
PIC18F2331/2431/4331/4431 REGISTER 23-2: U-0 CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 — U-0 — — U-0 — R/P-1 BORV1 R/P-1 BORV0 R/P-1 R/P-1 (1) BOREN bit 7 PWRTEN(1) bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 BORV<1:0>: Brown-out Reset Voltage bits 11 = Reserved 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.
PIC18F2331/2431/4331/4431 REGISTER 23-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — WINEN WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ U = Unchanged from programmed state bit 7-6 Unimplemented: Read as ‘0’ bit 5 WINEN: Watchdog Timer Window Enable bit 1 = WDT window is disabled 0 = WDT window is
PIC18F2331/2431/4331/4431 REGISTER 23-4: U-0 CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h) U — R/P-1 — T1OSCMX R/P-1 HPOL (1) R/P-1 LPOL (1) R/P-1 (3) PWMPIN U U — — bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ U = Unchanged from programmed state bit 7-6 Unimplemented: Read as ‘0’ bit 5 T1OSCMX: Timer1 Oscillator Mode bit 1 = Low-power Timer1 operation when microcontroller is in Sl
PIC18F2331/2431/4331/4431 REGISTER 23-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U U MCLRE(1) — — R/P-1 R/P-1 EXCLKMX(1) PWM4MX(1) R/P-1 U R/P-1 SSPMX(1) — FLTAMX(1) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ U = Unchanged from programmed state bit 7 MCLRE: MCLR Pin Enable bit(1) 1 = MCLR pin is enabled; RE3 input pin is disabled 0 = RE3 input pin is enabled; MCLR is
PIC18F2331/2431/4331/4431 REGISTER 23-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 U-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 DEBUG — — — — LVP — STVREN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ U = Unchanged from programmed state bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled; RB6 and RB7 are configured as general purpose I/O pins 0 = Background
PIC18F2331/2431/4331/4431 REGISTER 23-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — CP3(1,2) CP2(1,2) CP1(2) CP0(2) bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit(1,2) 1 = Block 3 is not code-protected 0 = Block 3 is code-protected bit 2 CP2: Code Protection bit(1,2) 1
PIC18F2331/2431/4331/4431 REGISTER 23-9: U-0 CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 — U-0 — — U-0 R/P-1 — WRT3 (1,2) R/P-1 WRT2 (1,2) R/P-1 R/P-1 (2) WRT1 WRT0(2) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit(1,2) 1 = Block 3 is not write-protected 0 = Block 3 is write-protected bit 2 WRT2: Write Protection bit(1,2) 1 = Block 2 is not wr
PIC18F2331/2431/4331/4431 REGISTER 23-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 — — U-0 — U-0 — R/P-1 EBTR3 (1,2,3) R/P-1 R/P-1 (1,2,3) EBTR2 EBTR1 (2,3) R/P-1 EBTR0(2,3) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ U = Unchanged from programmed state bit 7-4 Unimplemented: Read as ‘0’ bit 3 EBTR3: Table Read Protection bit(1,2,3) 1 = Block 3 is not protected from ta
PIC18F2331/2431/4331/4431 REGISTER 23-13: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2331/2431/4331/4431 DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ U = Unchanged from programmed state bit 7-5 DEV<2:0>: Device ID bits These bits are used with the DEV<10:3> bits in the Device ID Register 2 to identify the part number.
PIC18F2331/2431/4331/4431 23.2 Watchdog Timer (WDT) For PIC18F2331/2431/4331/4431 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H (see Register 23-3). Available periods range from 4 ms to 131.
PIC18F2331/2431/4331/4431 REGISTER 23-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER R-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 WDTW — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WDTW: Watchdog Timer Window bit 1 = WDT count is in fourth quadrant 0 = WDT count is not in fourth quadrant bit 6-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Enable/Disable for Watc
PIC18F2331/2431/4331/4431 23.3 In all other power-managed modes, Two-Speed Startup is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO Configuration bit is ignored.
PIC18F2331/2431/4331/4431 23.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation, in the event of an external oscillator failure, by automatically switching the system clock to the internal oscillator block. The FSCM function is enabled by setting the Fail-Safe Clock Monitor Enable bit, FCMEN (CONFIG1H<6>).
PIC18F2331/2431/4331/4431 FIGURE 23-4: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: 23.4.3 CM Test CM Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. FSCM INTERRUPTS IN POWER-MANAGED MODES As previously mentioned, entering a power-managed mode clears the fail-safe condition.
PIC18F2331/2431/4331/4431 23.5 Each of the five blocks has three code protection bits associated with them. They are: Program Verification and Code Protection The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PIC® devices. • Code-Protect bit (CPn) • Write-Protect bit (WRTn) • External Block Table Read bit (EBTRn) The user program memory is divided into five blocks. One of these is a Boot Block of 512 bytes.
PIC18F2331/2431/4331/4431 23.5.1 PROGRAM MEMORY CODE PROTECTION Note: The program memory may be read to, or written from, any location using the table read and table write instructions. The Device ID may be read with table reads. The Configuration registers may be read and written with the table read and table write instructions. In normal execution mode, the CPn bits have no direct effect. CPn bits inhibit external reads and writes.
PIC18F2331/2431/4331/4431 FIGURE 23-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Configuration Bit Settings Program Memory 000000h 0001FFh 000200h TBLPTR = 0002FFh PC = 000FFEh WRTB, EBTRB = 11 WRT0, EBTR0 = 10 0007FFh 000800h TBLRD * 000FFFh 001000h WRT1, EBTR1 = 11 WRT2, EBTR2 = 11 0017FFh 001800h WRT3, EBTR3 = 11 001FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. The TABLAT register returns a value of ‘0’.
PIC18F2331/2431/4331/4431 23.5.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits external writes to data EEPROM. The CPU can continue to read and write data EEPROM regardless of the protection bit settings. 23.5.3 CONFIGURATION REGISTER PROTECTION The Configuration registers can be write-protected. The WRTC bit controls protection of the Configuration registers.
PIC18F2331/2431/4331/4431 24.0 INSTRUCTION SET SUMMARY The PIC18 instruction set adds many enhancements to the previous PIC® instruction sets, while maintaining an easy migration from these PIC instruction sets. Most instructions are a single program memory word (16 bits), but there are three instructions that require two program memory locations.
PIC18F2331/2431/4331/4431 TABLE 24-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank.
PIC18F2331/2431/4331/4431 FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 OPCODE Example Instruction 8 7 d 0 a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE 15 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destinatio
PIC18F2331/2431/4331/4431 TABLE 24-2: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f s, f d MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f
PIC18F2331/2431/4331/4431 TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL n n n n n n n n n n, s CLRWDT DAW GOTO — — n NOP NOP POP PUSH RCALL RESET RETFIE — — — — n RETLW RETURN SLEEP Note 1: 2: 3: 4: 5: 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 1 (2) 1 (2) 2 s Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Bran
PIC18F2331/2431/4331/4431 TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Load Literal (12-bit) 2nd word to FSRx 1st word Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Subtrac
PIC18F2331/2431/4331/4431 24.2 Instruction Set ADDLW ADD Literal to W ADDWF ADD W to f Syntax: [ label ] ADDLW Syntax: [ label ] ADDWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 k 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18F2331/2431/4331/4431 ADDWFC ADD W and Carry bit to f ANDLW Syntax: [ label ] ADDWFC Syntax: [ label ] ANDLW Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 k 255 Operation: (W) .AND. k W Status Affected: N, Z f [,d [,a]] Operation: (W) + (f) + (C) dest Status Affected: N, OV, C, DC, Z Encoding: 0010 Description: 00da Encoding: ffff ffff Add W, the Carry flag and data memory location, ‘f’. If ‘d’ is ‘0’, the result is placed in W.
PIC18F2331/2431/4331/4431 ANDWF AND W with f Syntax: [ label ] ANDWF Operands: 0 f 255 d [0,1] a [0,1] f [,d [,a]] Operation: (W) .AND. (f) dest Status Affected: N, Z Encoding: 0001 01da ffff ffff The contents of W are ANDed with register, ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register, ‘f’. If ‘a’ is ‘0’, the Access Bank will be selected. If ‘a’ is ‘1’, the BSR will not be overridden.
PIC18F2331/2431/4331/4431 BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 f 255 0b7 a [0,1] Operation: 0 f Status Affected: None Encoding: 1001 f,b[,a] bbba ffff ffff Bit ‘b’ in register, ‘f’, is cleared. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value.
PIC18F2331/2431/4331/4431 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: [ label ] BNC Syntax: [ label ] BNN Operands: -128 n 127 Operands: -128 n 127 Operation: if Carry bit is ‘0’, (PC) + 2 + 2n PC Operation: if Negative bit is ‘0’, (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: n 0011 nnnn nnnn Encoding: 1110 If the Carry bit is ‘0’, then the program will branch.
PIC18F2331/2431/4331/4431 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: [ label ] BNOV Syntax: [ label ] BNZ Operands: -128 n 127 Operands: -128 n 127 Operation: if Overflow bit is ‘0’, (PC) + 2 + 2n PC Operation: if Zero bit is ‘0’, (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: n 0101 nnnn nnnn Encoding: 1110 If the Overflow bit is ‘0’, then the program will branch.
PIC18F2331/2431/4331/4431 BRA Unconditional Branch BSF Syntax: [ label ] BRA Syntax: [ label ] BSF Operands: -1024 n 1023 Operands: 0 f 255 0b7 a [0,1] n Operation: (PC) + 2 + 2n PC Status Affected: None Encoding: 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number, ‘2n’, to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction.
PIC18F2331/2431/4331/4431 BTFSC Bit Test File, Skip if Clear BTFSS Syntax: [ label ] BTFSC f,b[,a] Syntax: [ label ] BTFSS f,b[,a] Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Bit Test File, Skip if Set Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register, ‘f’, is ‘0’, then the next instruction is skip
PIC18F2331/2431/4331/4431 BTG Bit Toggle f BOV Branch if Overflow Syntax: [ label ] BTG f,b[,a] Syntax: [ label ] BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if Overflow bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None Operation: (f) f Status Affected: None Encoding: Encoding: 0111 bbba ffff ffff Description: Bit ‘b’ in data memory location, ‘f’, is inverted. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value.
PIC18F2331/2431/4331/4431 BZ Branch if Zero CALL Syntax: [ label ] BZ Syntax: [ label ] CALL k [,s] Operands: -128 n 127 Operands: Operation: if Zero bit is ‘1’, (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: (PC) + 4 TOS, k PC<20:1>; if s = 1: (W) WS, (STATUS) STATUSS, (BSR) BSRS Status Affected: None Status Affected: n Subroutine Call None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
PIC18F2331/2431/4331/4431 CLRF Clear f Syntax: [ label ] CLRF Operands: 0 f 255 a [0,1] Operation: 000h f, 1Z Status Affected: Z Encoding: 0110 f [,a] 101a ffff ffff CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 000h WDT, 000h WDT postscaler, 1 TO, 1 PD Status Affected: TO, PD Clears the contents of the specified register. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value.
PIC18F2331/2431/4331/4431 COMF Complement f Syntax: [ label ] COMF Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest Status Affected: N, Z Encoding: 0001 Description: CPFSEQ f [,d [,a]] 11da ffff ffff The contents of register, ‘f’, are complemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register, ‘f’. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value.
PIC18F2331/2431/4331/4431 CPFSGT Compare f with W, Skip if f > W CPFSLT Syntax: [ label ] CPFSGT Syntax: [ label ] CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) W), skip if (f) > (W) (unsigned comparison) Operation: (f) –W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a f [,a] ffff ffff Description: Compares the contents of data memory location, ‘f’, to the contents of the W by pe
PIC18F2331/2431/4331/4431 DAW Decimal Adjust W Register DECF Syntax: [ label ] DAW Syntax: [ label ] DECF f [,d [,a]] Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1] then, (W<3:0>) + 6 W<3:0>; else, (W<3:0>) W<3:0>; 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> 9] or [C = 1] then, (W<7:4>) + 6 W<7:4>; else, (W<7:4>) W<7:4> Status Affected: Decrement f 0000 0000 Description: 0000 0000 Words: 1
PIC18F2331/2431/4331/4431 DECFSZ Decrement f, Skip if 0 DCFSNZ Syntax: [ label ] DECFSZ f [,d [,a]] Syntax: [ label ] DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest, skip if result = 0 Operation: (f) – 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff Decrement f, Skip if Not 0 Encoding: 0100 The contents of register, ‘f’, are decremented.
PIC18F2331/2431/4331/4431 GOTO Unconditional Branch INCF Syntax: [ label ] Syntax: [ label ] Operands: 0 k 1048575 Operands: Operation: k PC<20:1> Status Affected: None 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 GOTO k 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range.
PIC18F2331/2431/4331/4431 INCFSZ Increment f, Skip if 0 INFSNZ Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 Description: INCFSZ f [,d [,a]] 11da ffff ffff Increment f, Skip if Not 0 Encoding: 0100 The contents of register, ‘f’, are incremented.
PIC18F2331/2431/4331/4431 IORLW Inclusive OR Literal with W IORWF Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: Operation: (W) .OR. k W Status Affected: N, Z 0 f 255 d [0,1] a [0,1] Operation: (W) .OR. (f) dest Status Affected: N, Z Encoding: 0000 Description: IORLW k 1001 kkkk kkkk The contents of W are ORed with the 8-bit literal, ‘k’. The result is placed in W.
PIC18F2331/2431/4331/4431 LFSR Load FSR MOVF Syntax: [ label ] Syntax: [ label ] Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N, Z Encoding: LFSR f,k 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’.
PIC18F2331/2431/4331/4431 MOVFF Move f to f MOVLB Syntax: [ label ] Operands: 0 fs 4095 0 fd 4095 Operation: (fs) fd Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) MOVFF fs,fd 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register, ‘fs’, are moved to destination register, ‘fd’.
PIC18F2331/2431/4331/4431 MOVLW Move Literal to W MOVWF Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Operation: (W) f Status Affected: None Encoding: 0000 MOVLW k 1110 kkkk kkkk Description: The 8-bit literal, ‘k’, is loaded into W.
PIC18F2331/2431/4331/4431 MULLW Multiply Literal with W Syntax: [ label ] Operands: 0 k 255 Operation: (W) x k PRODH:PRODL Status Affected: None Encoding: 0000 Description: MULLW MULWF k 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal, ‘k’. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the Status flags are affected.
PIC18F2331/2431/4331/4431 NEGF Negate f Syntax: [ label ] Operands: 0 f 255 a [0,1] Operation: (f)+1f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: NEGF f [,a] 1 Cycles: 1 No Operation Syntax: [ label ] Operands: None ffff NOP Operation: No operation Status Affected: None Encoding: 110a 0000 1111 ffff Location, ‘f’, is negated using two’s complement. The result is placed in the data memory location, ‘f’.
PIC18F2331/2431/4331/4431 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC + 2) TOS Status Affected: None Status Affected: None Encoding: 0000 POP 0000 0000 0110 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18F2331/2431/4331/4431 RCALL Relative Call Syntax: [ label ] RCALL Operands: -1024 n 1023 Operation: (PC) + 2 TOS, (PC) + 2 + 2n PC Status Affected: None Encoding: 1101 Description: n 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n.
PIC18F2331/2431/4331/4431 RETFIE Return from Interrupt RETLW Syntax: [ label ] Syntax: [ label ] Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL; if s = 1: (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged Operation: k W, (TOS) PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: RETFIE [s] Encoding: 0000 0000 Description: 0000 0001 Words: 1 Cycles: 2 Q Cycle Activity: 1100 kkkk kkkk W i
PIC18F2331/2431/4331/4431 RETURN Return from Subroutine RLCF Syntax: [ label ] Syntax: [ label ] Operands: s [0,1] Operands: Operation: (TOS) PC; if s = 1: (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) C, (C) dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Description: RETURN [s] Rotate Left f through Carry Encoding: 0000 0001 001s 0011 Description: f
PIC18F2331/2431/4331/4431 RLNCF Rotate Left f (No Carry) RRCF Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) dest<0> Operation: Status Affected: N, Z (f) dest, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: RLNCF 01da f [,d [,a]] ffff ffff The contents of register, ‘f’, are rotated one bit to the left.
PIC18F2331/2431/4331/4431 RRNCF Rotate Right f (No Carry) SETF Syntax: [ label ] Syntax: [ label ] SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: FFh f Operation: (f) dest, (f<0>) dest<7> Status Affected: None Status Affected: RRNCF f [,d [,a]] Encoding: N, Z Encoding: 0100 Description: 00da ffff ffff The contents of register, ‘f’, are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18F2331/2431/4331/4431 SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) – (f) – (C) dest Status Affected: N, OV, C, DC, Z SLEEP Operands: None Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set.
PIC18F2331/2431/4331/4431 SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) dest Status Affected: N, OV, C, DC, Z SUBLW k Operands: 0 k 255 Operation: k – (W) W Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the 8-bit literal, ‘k’. The result is placed in W.
PIC18F2331/2431/4331/4431 SUBWFB Subtract W from f with Borrow SWAPF Syntax: [ label ] Syntax: [ label ] 0 f 255 d [0,1] a [0,1] SUBWFB f [,d [,a]] Swap f SWAPF f [,d [,a]] Operands: 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) – (W) – (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: 0101 10da ffff ffff Description: Subtract W and the Carry flag (borrow) from register, ‘f’ (2’s co
PIC18F2331/2431/4331/4431 TBLRD Table Read TBLRD Table Read (cont’d) Syntax: [ label ] Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) TABLAT, TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT, (TBLPTR) + 1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT, (TBLPTR) – 1 TBLPTR; if TBLRD +*, (TBLPTR) + 1 TBLPTR, (Prog Mem (TBLPTR)) TABLAT TBLRD ( *; *+; *-; +*) Encoding: 0000 0000 0000 = = = 0x55 0x00A356 0x34 After Instruction TABLAT TBLPTR
PIC18F2331/2431/4331/4431 TBLWT Table Write TBLWT Table Write (Continued) Syntax: [ label ] Words: Operands: None Cycles: 2 Operation: if TBLWT*, (TABLAT) Holding Register, TBLPTR – No Change; if TBLWT*+, (TABLAT) Holding Register, (TBLPTR) + 1 TBLPTR; if TBLWT*-, (TABLAT) Holding Register, (TBLPTR) – 1 TBLPTR; if TBLWT+*, (TBLPTR) + 1 TBLPTR, (TABLAT) Holding Register Q Cycle Activity: Status Affected: Encoding: Description: TBLWT ( *; *+; *-; +*) Example 1: None 0000 0000 0
PIC18F2331/2431/4331/4431 TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 a [0,1] TSTFSZ f [,a] Operation: skip if f = 0 Status Affected: None Encoding: Description: Operands: 0 k 255 Operation: (W) .XOR.
PIC18F2331/2431/4331/4431 XORWF Exclusive OR W with f Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 XORWF 10da f [,d [,a]] ffff ffff Description: Exclusive OR the contents of W with register, ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register, ‘f’. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value.
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PIC18F2331/2431/4331/4431 25.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
PIC18F2331/2431/4331/4431 25.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC18F2331/2431/4331/4431 25.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 25.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC18F2331/2431/4331/4431 26.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) .......................................
PIC18F2331/2431/4331/4431 FIGURE 26-1: PIC18F2331/2431/4331/4431 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18F2X31/4X31 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz Frequency FIGURE 26-2: PIC18LF2331/2431/4331/4431 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18LF2X31/4X31 Voltage 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz 4 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.
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PIC18F2331/2431/4331/4431 26.
PIC18F2331/2431/4331/4431 26.
PIC18F2331/2431/4331/4431 26.
PIC18F2331/2431/4331/4431 26.
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PIC18F2331/2431/4331/4431 26.3 DC Characteristics: PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions VSS 0.15 VDD V VDD < 4.5V — 0.8 V 4.5V VDD 5.5V VSS VSS 0.2 VDD 0.
PIC18F2331/2431/4331/4431 26.3 DC Characteristics: PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param Symbol No. VOL Characteristic Min Max Units Conditions Output Low Voltage D080 I/O Ports — 0.6 V IOL = 8.5 mA, VDD = 4.
PIC18F2331/2431/4331/4431 TABLE 26-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param No. Sym Characteristic Min Typ† Max Units V Conditions Internal Program Memory Programming Specifications(1) D110 VPP Voltage on MCLR/VPP pin 9.00 — 13.
PIC18F2331/2431/4331/4431 FIGURE 26-3: LOW-VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be cleared in software) VLVD (LVDIF set by hardware) LVDIF TABLE 26-2: LOW-VOLTAGE DETECT CHARACTERISTICS PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for indust
PIC18F2331/2431/4331/4431 TABLE 26-2: LOW-VOLTAGE DETECT CHARACTERISTICS (CONTINUED) PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F2331/2431/4331/4431 26.4 26.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC18F2331/2431/4331/4431 26.4.2 TIMING CONDITIONS Note: The temperature and voltages specified in Table 26-3 apply to all timing specifications unless otherwise noted. Figure 26-4 specifies the load conditions for the timing specifications.
PIC18F2331/2431/4331/4431 26.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 26-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 26-4: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic Min Max Units External CLKI Frequency(1) DC 40 MHz EC, ECIO DC 4 MHz RC osc 0.
PIC18F2331/2431/4331/4431 TABLE 26-5: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Sym Characteristic Min Typ† Max 4 16 — — 10 40 Units F10 F11 FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency F12 TPLL PLL Start-up Time (Lock Time) — — 2 ms CLK CLKO Stability (Jitter) -2 — +2 % F13 Conditions MHz HS mode only MHz HS mode only † Data in “Typ” column is at 5V, 25C unless otherwise stated.
PIC18F2331/2431/4331/4431 FIGURE 26-6: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O Pin (Input) 15 17 I/O Pin (Output) New Value Old Value 20, 21 TABLE 26-7: Param No.
PIC18F2331/2431/4331/4431 FIGURE 26-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins FIGURE 26-8: BROWN-OUT RESET TIMING VDD BVDD 35 VIRVST VBGAP = 1.2V (nominal) Enable Internal Reference Voltage Internal Reference Voltage Stable 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 TABLE 26-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No.
PIC18F2331/2431/4331/4431 FIGURE 26-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 TABLE 26-9: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol No.
PIC18F2331/2431/4331/4431 FIGURE 26-10: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 TABLE 26-10: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param Symbol No. 50 51 TccL TccH Characteristic Min Max Units CCPx Input Low No prescaler Time With PIC18FXX31 prescaler PIC18LFXX31 0.5 TCY + 20 — ns 10 — ns 20 — ns CCPx Input High No prescaler Time With PIC18FXX31 prescaler PIC18LFXX31 0.
PIC18F2331/2431/4331/4431 FIGURE 26-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SCK (CKP = 0) 78 79 79 78 SCK (CKP = 1) 80 bit 6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 TABLE 26-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No.
PIC18F2331/2431/4331/4431 FIGURE 26-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) 81 SCK (CKP = 0) 79 73 SCK (CKP = 1) 80 78 MSb SDO bit 6 - - - - - -1 LSb bit 6 - - - -1 LSb In 75, 76 SDI MSb In 74 TABLE 26-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No.
PIC18F2331/2431/4331/4431 FIGURE 26-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 77 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 TABLE 26-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE, CKE = 0) Param No. Symbol Characteristic 70 TssL2scH, SS to SCK or SCK Input TssL2scL 71 TscH SCK Input High Time 71A 72 TscL SCK Input Low Time 72A 73 Min TCY Max Units Conditions — ns Continuous 1.
PIC18F2331/2431/4331/4431 FIGURE 26-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 75, 76 SDI 77 bit 6 - - - -1 MSb In LSb In 74 TABLE 26-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No.
PIC18F2331/2431/4331/4431 FIGURE 26-15: I2C™ BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Stop Condition Start Condition TABLE 26-15: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
PIC18F2331/2431/4331/4431 TABLE 26-16: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH Characteristic Clock High Time Min Max Units Conditions 100 kHz mode 4.0 — s PIC18FXX31 must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s PIC18FXX31 must operate at a minimum of 10 MHz 1.5 TCY — 100 kHz mode 4.7 — s PIC18FXX31 must operate at a minimum of 1.5 MHz 400 kHz mode 1.
PIC18F2331/2431/4331/4431 TABLE 26-17: SSP I2C™ BUS DATA REQUIREMENTS Param. No. Symbol Characteristic Min Max Units 2(TOSC)(BRG + 1) — ms 100 THIGH Clock High Time 100 kHz mode 400 kHz mode 2(TOSC)(BRG + 1) — ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 102 TR SDA and SCL Rise Time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns 103 TF SDA and SCL Fall Time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.
PIC18F2331/2431/4331/4431 FIGURE 26-17: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK/SS Pin 121 121 RC7/RX/DT/SDO Pin 120 122 TABLE 26-18: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Symbol No.
PIC18F2331/2431/4331/4431 TABLE 26-20: A/D CONVERTER CHARACTERISTICS PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param Symbol No. Characteristic Min Typ Max Units — VDD + 0.
PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 362 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 27.0 PACKAGING INFORMATION 27.1 Package Marking Information 28-Lead SPDIP (Skinny PDIP) Example PIC18F2331-I/SP e3 1010017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead QFN Example XXXXXXXX XXXXXXXX YYWWNNN 18F2431 -I/ML e3 1010017 Legend: XX...
PIC18F2331/2431/4331/4431 27.1 Package Marking Information (Continued) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS39616D-page 364 PIC18F4331-I/P e3 1010017 Example PIC18F4431 -I/PT e3 1010017 Example PIC18F4431 -I/ML e3 1010017 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 27.2 Package Details The following sections give the technical details of the packages. ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6 &! ' ! 9 ' &! 7"') % ! 7,8.
PIC18F2331/2431/4331/4431 # # $ % &'( # ) ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 NOTE 1 1 2 3 e b h α A2 A h c φ L A1 β L1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7: 7 ; < & : 8 & = = = = = - # # 4 4 !! & # %% + 1 , : > #& .
PIC18F2331/2431/4331/4431 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 * + % ! , - ./. *+! 0 1 '(( ) , 1 ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D D2 EXPOSED PAD e E b E2 2 2 1 1 N K N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 6 &! ' ! 9 ' &! 7"') % ! 99 . .
PIC18F2331/2431/4331/4431 * + % ! , - ./. *+! 0 1 '(( ) , 1 ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 2 . ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6 &! ' ! 9 ' &! 7"') % ! 7,8. 7 7 & ; & & 7: 1 , = = = 1 ! & & = = .
PIC18F2331/2431/4331/4431 22 31 ! " * + 4 3 5 /5 /5 % ' 3*+ 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A φ c β A2 A1 L L1 6 &! ' ! 9 ' &! 7"') % 9 #! 99 . .
PIC18F2331/2431/4331/4431 22 31 ! " * + 4 3 5 /5 /5 % ' 3*+ 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 DS39616D-page 372 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 22 * + % ! , - / *+! ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 7: ; & : 8 & < & # %% , & & 4 !! - : > #& .
PIC18F2331/2431/4331/4431 22 * + % ! , - / *+! ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 DS39616D-page 374 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 APPENDIX A: REVISION HISTORY Revision A (June 2003) Original data sheet for PIC18F2331/2431/4331/4431 devices. Revision B (December 2003) The Electrical Specifications in Section 26.0 “Electrical Characteristics” have been updated and there have been minor corrections to the data sheet text. Revision D (September 2010) Section 2.0 “Guidelines for Getting Started with PIC18F Microcontrollers” has been updated with more detailed explanations.
PIC18F2331/2431/4331/4431 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B.
PIC18F2331/2431/4331/4431 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, “Migrating Designs from PIC16C74A/74B to PIC18F442.” The changes discussed, while devicespecific, are generally applicable to all mid-range to enhanced device migrations.
PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 378 2010 Microchip Technology Inc.
PIC18F2331/2431/4331/4431 INDEX A A/D .................................................................................... 239 Acquisition Requirements ......................................... 249 Associated Registers ................................................ 255 Calculating the Minimum Required Acquisition Time ............................................... 250 Configuring................................................................ 247 Configuring Analog Port Pins..............................
PIC18F2331/2431/4331/4431 CCP2 ........................................................................ 145 CCPR2H Register............................................. 145 CCPR2L Register ............................................. 145 Compare Mode. See Compare. Timer Resources....................................................... 145 CKE Bit.............................................................................. 206 CKP Bit..........................................................................
PIC18F2331/2431/4331/4431 EUSART Asynchronous Mode ................................................. 226 Associated Registers, Receive ......................... 230 Associated Registers, Transmit ........................ 228 Auto-Wake-up on Sync Break .......................... 231 Receiver............................................................ 229 Receiving a Break Character ............................ 232 Setting Up 9-Bit Mode with Address Detect...... 229 Transmitter................................
PIC18F2331/2431/4331/4431 MOVLW .................................................................... 309 MOVWF .................................................................... 309 MULLW ..................................................................... 310 MULWF ..................................................................... 310 NEGF ........................................................................ 311 NOP ..........................................................................
PIC18F2331/2431/4331/4431 MPLINK Object Linker/MPLIB Object Librarian ................ 326 MULLW ............................................................................. 310 MULWF ............................................................................. 310 N NEGF ................................................................................ 311 NOP .................................................................................. 311 O Opcode Field Descriptions ................................
PIC18F2331/2431/4331/4431 Run Modes.................................................................. 40 PRI_RUN ............................................................ 40 RC_RUN ............................................................. 41 SEC_RUN........................................................... 40 Selecting ..................................................................... 39 Sleep Mode ................................................................. 43 Summary (table) ..............
PIC18F2331/2431/4331/4431 DEVID2 (Device ID 2) ............................................... 273 DFLTCON (Digital Filter Control) .............................. 169 DTCON (Dead-Time Control) ................................... 192 EECON1 (Data EEPROM Control 1) .......................... 87 EECON1 (EEPROM Control 1)................................... 80 FLTCONFIG (Fault Configuration)............................ 201 INTCON (Interrupt Control).........................................
PIC18F2331/2431/4331/4431 Timer2 ............................................................................... 136 Associated Registers ................................................ 137 Interrupt..................................................................... 137 Operation .................................................................. 136 Postscaler. See Postscaler, Timer2. Prescaler. See Prescaler, Timer2. PR2 Register.............................................................
PIC18F2331/2431/4331/4431 Example SPI Mode Requirements (Slave Mode, CKE = 0) ..................................... 355 Example SPI Slave Mode Requirements (CKE = 1) .......................................................... 356 External Clock Requirements ................................... 346 Internal RC Accuracy ................................................ 347 I2C Bus Data Requirements (Slave Mode) ............... 358 I2C Bus Start/Stop Bits Requirements (Slave Mode) ................................
PIC18F2331/2431/4331/4431 NOTES: DS39616D-page 388 2010 Microchip Technology Inc.
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PIC18F2331/2431/4331/4431 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device PIC18F2331/2431/4331/4431(1), PIC18F2331/2431/4331/4431T(1,2); VDD range 4.2V to 5.5V c) PIC18LF4431-I/P 301 = Industrial temp., PDIP package, Extended VDD limits, QTP pattern #301. PIC18LF2331-I/SO = Industrial temp.
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