Stereo System User Manual

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DSP56012UM/D

Rev. 0

Published 11/98

DSP56012

24-Bit Digital Signal Processor

User’s Manual

Motorola, Incorporated

Semiconductor Products Sector

DSP Division

6501 William Cannon Drive West

Austin, TX 78735-8598

Summary of content (270 pages)

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DSP56012UM/D Rev.
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DSP56012UM/D Rev. 0 Published 11/98 This document (and other documents) can be viewed on the World Wide Web at http://www.motorola-dsp.com. This manual is one of a set of three documents. You need the following manuals to have complete product information: Family Manual, User’s Manual, and Technical Data. OnCE is a trademark of Motorola, Inc.  MOTOROLA INC., 1998 Order this document by DSP56012UM/AD Motorola reserves the right to make changes without further notice to any products herein.
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Table of Contents 1.1 1.1.1 1.1.2 1.2 1.3 1.3.1 1.3.2 1.3.2.1 1.3.2.2 1.3.2.3 1.3.2.4 1.3.2.5 1.3.2.6 1.3.2.7 1.3.3 1.3.3.1 1.3.3.2 1.3.3.3 1.3.3.4 1.3.3.5 1.3.3.6 1.3.3.7 1.3.3.8 1.3.4 1.3.4.1 1.3.4.2 1.3.4.3 1.3.4.4 1.3.4.5 2.1 2.2 2.3 2.4 2.5 Motorola INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Manual Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Manual Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2.6 2.7 2.8 2.8.1 2.8.2 2.9 2.10 2.11 3.1 3.2 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.3.3 3.4 3.4.1 3.4.2 HOST INTERFACE (HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 SERIAL HOST INTERFACE (SHI) . . . . . . . . . . . . . . . . . . . 2-13 SERIAL AUDIO INTERFACE (SAI) . . . . . . . . . . . . . . . . . . 2-16 SAI Receive Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 SAI Transmit Section . . . . . . . . . . . . . . . . . . . . . . . . . . .
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4.4.4.1.2 4.4.4.1.3 4.4.4.1.4 4.4.4.1.5 4.4.4.1.6 4.4.4.2 4.4.4.2.1 4.4.4.2.2 4.4.4.2.3 4.4.4.2.4 4.4.4.2.5 4.4.4.2.6 4.4.4.2.7 4.4.4.3 4.4.4.4 4.4.4.5 4.4.4.6 4.4.4.7 4.4.5 4.4.5.1 4.4.5.2 4.4.5.3 4.4.5.3.1 4.4.5.3.2 4.4.5.3.3 4.4.5.3.4 4.4.5.3.5 4.4.5.3.6 4.4.5.3.7 4.4.5.4 4.4.5.5 4.4.5.5.1 4.4.5.5.2 4.4.5.5.3 4.4.5.6 4.4.5.6.1 4.4.5.6.2 4.4.5.6.3 Motorola HCR HI Transmit Interrupt Enable (HTIE)—Bit 1 . 4-15 HCR HI Command Interrupt Enable (HCIE)—Bit 2 4-15 HCR HI Flag 2 (HF2)—Bit 3 . . . . . . . . . . .
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4.4.5.6.4 4.4.5.6.5 4.4.5.6.6 4.4.5.6.7 4.4.5.6.8 4.4.5.7 4.4.5.8 4.4.5.9 4.4.5.10 4.4.6 4.4.6.1 4.4.6.2 4.4.6.3 4.4.6.4 4.4.6.5 4.4.6.6 4.4.7 4.4.7.1 4.4.7.2 4.4.7.3 4.4.7.4 4.4.7.5 4.4.8 4.4.8.1 4.4.8.2 4.4.8.2.1 4.4.8.2.2 4.4.8.2.3 4.4.8.2.4 4.4.8.3 4.4.8.3.1 4.4.8.3.2 4.4.8.3.3 4.4.8.3.4 4.4.8.4 4.4.8.4.1 4.4.8.4.2 4.4.8.4.3 vi ISR HI Flag 2 (HF2)—Bit 3 (read only) . . . . . . . . . 4-31 ISR HI Flag 3 (HF3)—Bit 4 (read only) . . . . . . . . . 4-31 ISR Reserved—Bit 5 . . . . . . . . . . . . . . . . . .
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4.4.8.4.4 Overwriting the Host Vector . . . . . . . . . . . . . . . . . 4-66 4.4.8.4.5 Cancelling a Pending Host Command interrupt . . 4-66 4.4.8.4.6 Coordinating Data Transfers . . . . . . . . . . . . . . . . . 4-67 4.4.8.4.7 Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 5.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2 SERIAL HOST INTERFACE INTERNAL ARCHITECTURE . 5-4 5.3 SHI CLOCK GENERATOR . . . . . . . . . . . . . . . . . . . . . .
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5.4.6.16 Host Receive Overrun Error (HROE)—Bit 20 . . . . . . 5-18 5.4.6.17 Host Bus Error (HBER)—Bit 21 . . . . . . . . . . . . . . . . . 5-18 5.4.6.18 HCSR Host Busy (HBUSY)—Bit 22. . . . . . . . . . . . . . 5-19 5.5 CHARACTERISTICS OF THE SPI BUS. . . . . . . . . . . . . . . 5-19 5.6 CHARACTERISTICS OF THE I2C BUS . . . . . . . . . . . . . . . 5-20 5.6.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.6.2 I2C Data Transfer Formats . . . . . . . . . . . . . . . . .
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6.3.2.10 6.3.2.11 6.3.2.12 6.3.2.13 6.3.2.14 6.3.3 6.3.4 6.3.4.1 6.3.4.2 6.3.4.3 6.3.4.4 6.3.4.5 RCS Receiver Data Word Truncation (RDWT)—Bit 106-14 RCS Receiver Interrupt Enable (RXIE)—Bit 11 . . . . . 6-15 RCS Receiver Interrupt Location (RXIL)—Bit 12 . . . . 6-15 RCS Receiver Left Data Full (RLDF)—Bit 14 . . . . . . 6-16 RCS Receiver Right Data Full (RRDF)—Bit 15 . . . . . 6-16 SAI Receive Data Registers (RX0 and RX1) . . . . . . . . . 6-17 Transmitter Control/Status Register (TCS). . . . . . . . . . .
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8.3 DAX FUNCTIONAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . 8-5 8.4 DAX PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . 8-6 8.5 DAX INTERNAL ARCHITECTURE. . . . . . . . . . . . . . . . . . . . 8-6 8.5.1 DAX Audio Data Registers A and B (XADRA/XADRB) . . 8-7 8.5.2 DAX Audio Data Buffer (XADBUF). . . . . . . . . . . . . . . . . . 8-7 8.5.3 DAX Audio Data Shift Register (XADSR) . . . . . . . . . . . . . 8-8 8.5.4 DAX Control Register (XCTR) . . . . . . . . . . . . . . . . . . . . .
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B.1 B.2 B.3 B.4 B.5 B.6 Motorola INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PERIPHERAL ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . INTERRUPT ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . INTERRUPT PRIORITIES . . . . . . . . . . . . . . . . . . . . . . . . . . INSTRUCTION SET SUMMARY . . . . . . . . . . . . . . . . . . . . . PROGRAMMING SHEETS. . . . . . . . . . . . . . . . . . . . . . . . . .
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xii Motorola
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List of Figures Figure 1-1 DSP56012 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Figure 2-1 DSP56012 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Figure 3-1 Memory Maps for PEA = 0, PEB = 0. . . . . . . . . . . . . . . . . . . . . . 3-5 Figure 3-2 Memory Maps for PEA = 1, PEB = 0. . . . . . . . . . . . . . . . . . . . . . 3-6 Figure 3-3 Memory Maps for PEA = 0, PEB = 1. . . . . . . . . . . . . . . . . . . . . .
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Figure 4-13 Command Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-29 Figure 4-14 Host Processor Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . .4-37 Figure 4-15 Interrupt Vector Register Read Timing . . . . . . . . . . . . . . . . . . . .4-40 Figure 4-16 HI Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-40 Figure 4-17 DMA Transfer Logic and Timing . . . . . . . . . . . . . . . . . . . . . . . . .
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Figure 4-36 DMA Transfer and HI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .4-61 Figure 4-37 Host to DSP DMA Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . .4-63 Figure 5-1 Serial Host Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . .5-4 Figure 5-2 SHI Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5 Figure 5-3 SHI Programming Model—Host Side . . . . . . . . . . . . . . . . . . . . . .
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Figure 6-11 Transmitter Left/Right Selection (TLRS) Programming . . . . . . .6-19 Figure 6-12 Transmitter Clock Polarity (TCKP) Programming . . . . . . . . . . . .6-20 Figure 6-13 Transmitter Relative Timing (TREL) Programming. . . . . . . . . . .6-20 Figure 6-14 Transmitter Data Word Expansion (TDWE) Programming . . . . .6-21 Figure 7-1 GPIO Control/Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3 Figure 7-2 GPIO Circuit Diagram . . . . . . . . . . . . . . . . . . . . .
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List of Tables Table 1-1 High True / Low True Signal Conventions. . . . . . . . . . . . . . . . . . 1-6 Table 1-2 DSP56012 Internal Memory Configurations . . . . . . . . . . . . . . . . 1-7 Table 1-3 Interrupt Starting Addresses and Sources Table 1-4 Internal Memory Configurations Table 1-5 On-chip Peripheral Memory Map . . . . . . . . . . . . . . . . . . . . . . . 1-17 Table 2-1 DSP56012 Functional Signal Groupings . . . . . . . . . . . . . . . . . . 2-3 Table 2-2 Power Inputs . . . . . . . .
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Table 3-5 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17 Table 4-1 HI Registers after Reset—DSP CPU Side . . . . . . . . . . . . . . . .4-19 Table 4-2 HOREQ Pin Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-25 Table 4-3 HI Mode Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-26 Table 4-4 HOREQ Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table B-2 Interrupt Priorities Within an IPL . . . . . . . . . . . . . . . . . . . . . . . . B-6 Table B-3 Instruction Set Summary (Sheet 1 of 7). . . . . . . . . . . . . . . . . . .
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xx Motorola
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SECTION 1 OVERVIEW MOTOROLA DSP56012 User’s Manual 1-1
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Overview 1.1 1.1.1 1.1.2 1.2 1.3 1.3.1 1.3.2 1.3.3 1.3.4 1-2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Manual Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Manual Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 DSP56012 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 DSP56012 ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . 1-8 Peripheral Modules . . . . . . . . . . . . . . . . . . . .
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Overview Introduction 1.1 INTRODUCTION This manual describes in detail the DSP56012 24-bit Digital Signal Processor (DSP), its memory, operating modes, and peripheral modules. This manual is intended to be used with the DSP56000 Family Manual (DSP56KFAMUM/AD) and the DSP56012 Technical Data sheet (DSP56012/D). The family manual describes the Central Processing Unit (CPU), programming models, and the instruction set.
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Overview Introduction 1.1.1 Manual Organization This manual includes the following sections: • Section 1—Overview furnishes a description of the manual organization and provides a brief description of the DSP56012. • Section 2—Signal Descriptions describes the DSP56012 signals and signal groupings. • Section 3—Memory, Operating Modes, and Interrupts describes the internal memory organization, operating modes, interrupt processing, and chip initialization during hardware reset.
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Overview Introduction 1.1.2 Manual Conventions The following conventions are used in this manual: • The word “reset” is used in three different contexts in this manual. There is a reset pin that is always written as “RESET”, there is a reset instruction that is always written as “RESET”, and the word reset, used to refer to the reset function, is written in lower case (with a leading capital letter as grammar dictates.
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Overview DSP56012 Features Table 1-1 High True / Low True Signal Conventions Signal/Symbol Logic State Signal State Voltage PIN1 True Asserted VCC3 PIN1 False Deasserted Ground2 PIN1 True Asserted Ground2 PIN1 False Deasserted VCC3 Notes: 1. 2. 3. 1.2 PIN is a generic term for any pin on the device. Ground is an acceptable low voltage level. See the appropriate data sheet for the range of acceptable low voltage levels (typically a TTL logic low).
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Overview DSP56012 Features – PLL-based clocking with a wide range of frequency multiplications (1 to 4096) and power saving clock divider (2i: i = 0 to 15), which reduces clock noise – Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories • Memory – Modified Harvard architecture allows simultaneous access to program and data memories – 15360 × 24-bit on-chip Program ROM1 – 4096 × 24-bit on-chip X-data RAM and 3584 × 2
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Overview DSP56012 Architectural Overview • Two sets of SAI interrupt vectors – SHI features: • Single master capability • SPI and I2C protocols • 10-word receive FIFO • Support for 8-, 16- and 24-bit words. 1.3 – Byte-wide Parallel Host Interface with DMA support capable of reconfiguration as fifteen General Purpose Input/Output (GPIO) lines – DAX features one serial transmitter capable of supporting S/PDIF, IEC958, CP-340, and AES/EBU formats.
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Overview DSP56012 Architectural Overview 8 15 Parallel Host Interface (HI) General Purpose I/O (GPIO) 5 9 Serial Audio Interface (SAI) 2 Serial Digital Host Audio Interface Transmitter (SHI) (DAX) Program Memory X Data Memory Y Data Memory Expansion Area 24-Bit DSP56000 Core GDB Internal Data Bus Switch PDB XDB YDB OnCETM Port Program Interrupt Controller Clock PLL Gen.
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Overview DSP56012 Architectural Overview 1.3.1 Peripheral Modules The following peripheral modules are included on the DSP56012: • Parallel Host Interface—The Host Interface (HI) provides a byte-wide parallel interface for parallel data transfer between the DSP56012 and a host processor or another parallel peripheral device.
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Overview DSP56012 Architectural Overview 1.3.2.1 Data Arithmetic and Logic Unit (Data ALU) The Data Arithmetic and Logic Unit (Data ALU) has been designed to be fast and provide the capability to process signals having a wide dynamic range. Special circuitry has been provided to facilitate the processing of data overflows and round-off errors. The Data ALU performs all of the arithmetic and logical operations on data operands.
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Overview DSP56012 Architectural Overview AGU registers may be read from or written to via the Global Data Bus as 16-bit operands. The AGU has two modulo arithmetic units that can generate two independent 16-bit addresses every instruction cycle for any two of the XAB, YAB, or PAB. 1.3.2.3 Program Control Unit The program control unit performs instruction prefetch, instruction decoding, hardware DO loop control, and exception processing.
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Overview DSP56012 Architectural Overview 1.3.2.7 On-Chip Emulation (OnCE) Port The On-Chip Emulation (OnCE) port provides a sophisticated debugging tool that allows simple, inexpensive, and speed-independent access to the processor’s internal registers and peripherals. The OnCE port tells the application programmer the exact status of most of the on-chip registers, memory locations, and buses, as well as storing the addresses of the last five instructions that were executed. 1.3.
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Overview DSP56012 Architectural Overview Table 1-3 Interrupt Starting Addresses and Sources (Continued) Interrupt Starting Address IPL P:$000E Reserved P:$0010 0–2 SAI Left Channel Transmitter if TXIL = 0 P:$0012 0–2 SAI Right Channel Transmitter if TXIL = 0 P:$0014 0–2 SAI Transmitter Exception if TXIL = 0 P:$0016 0–2 SAI Left Channel Receiver if RXIL = 0 P:$0018 0–2 SAI Right Channel Receiver if RXIL = 0 P:$001A 0–2 SAI Receiver Exception if RXIL = 0 P:$001C Reserved P:$001E 3 P
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Overview DSP56012 Architectural Overview Table 1-3 Interrupt Starting Addresses and Sources (Continued) Interrupt Starting Address IPL P: $0050 0–2 DAX Transmit Underrun Error P: $0052 0–2 DAX Block Transferred P: $0054 Interrupt Source Reserved; available for Host Command, see p. B-5–B-6. P: $0056 0–2 DAX Transmit Register Empty P: $0058 Reserved; available for Host Command, see p. B-5–B-6. : Reserved; available for Host Command, see p. B-5–B-6.
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Overview DSP56012 Architectural Overview 1.3.3.5 Memory Configuration Bits Through the use of bits PEA and PEB in the Operating Mode Register (OMR), four different memory configurations are possible, to provide appropriate memory sizes for a variety of applications (see Table 1-4). 1.3.3.6 External Memory The DSP56012 does not extend internal memory off chip. 1.3.3.7 Bootstrap ROM The bootstrap ROM occupies locations 0–31 ($0–$1F) in the memory map on the DSP56012.
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Overview DSP56012 Architectural Overview Table 1-5 On-chip Peripheral Memory Map Address Register X:$FFFF Interrupt Priority Register (IPR) X:$FFFE Reserved X:$FFFD PLL Control Register (PCTL) X:$FFFC Reserved X:$FFFB Reserved X:$FFFA Reserved X:$FFF9 Reserved X:$FFF8 Reserved X:$FFF7 GPIO Control/Data Register (GPIOR) X:$FFF6 Reserved X:$FFF5 Reserved X:$FFF4 Reserved X:$FFF3 SHI Receive FIFO/Transmit Register (HRX/HTX) X:$FFF2 SHI I2C Slave Address Register (HSAR) X:$FFF1 S
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Overview DSP56012 Architectural Overview Table 1-5 On-chip Peripheral Memory Map (Continued) Address Register X:$FFDE DAX Control Register (XCTR) X:$FFDD Reserved X:$FFDC DAX Transmit Data Registers (XADRA/XADRB) X:$FFDB Reserved : : X:$FFC0 Reserved 1.3.4.1 Parallel Host Interface (HI) The parallel Host Interface (HI) is a byte-wide, full-duplex, double-buffered, parallel port that can be connected directly to the data bus of a host processor.
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Overview DSP56012 Architectural Overview 1.3.4.3 Serial Audio Interface (SAI) The DSP can communicate with other devices through its serial audio interfaces. The Serial Audio Interface (SAI) provides a synchronous full-duplex serial port for serial connection with a variety of audio devices such as Analog-to-Digital (A/D) converters, Digital-to-Analog (D/A) converters, Compact Disc (CD) devices, etc. The SAI implements a wide range of serial data formats in use by audio manufacturers.
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Overview DSP56012 Architectural Overview 1-20 DSP56012 User’s Manual MOTOROLA
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SECTION 2 SIGNAL DESCRIPTIONS MOTOROLA DSP56012 User’s Manual 2-1
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Signal Descriptions 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2-2 SIGNAL GROUPINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 GROUND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 PHASE LOCK LOOP (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 INTERRUPT AND MODE CONTROL . . . . . . . . . . . . . . . . . . 2-8 HOST INTERFACE (HI) . . . . . .
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Signal Descriptions Signal Groupings 2.1 SIGNAL GROUPINGS The DSP56012 input and output signals are organized into the ten functional groups shown in Table 2-1. The individual signals are shown in Figure 2-1 on page 2-4.
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Signal Descriptions Signal Groupings DSP56012 VCCP VCCQ VCCA VCCD VCCH VCCS GNDP GNDQ GNDA GNDD GNDH GNDS PLOCK PCAP PINIT EXTAL 4 2 1 3 2 4 3 2 4 3 Power Inputs: PLL Internal Logic A D HI SHI Grounds: PLL Internal Logic A D HI SHI PLL Host Interface (HI) Port 8 Serial Host Interface (SHI) MOSI/HA0 SS/HA2 MISO/SDA SCK/SCL HREQ Serial Audio Interface (SAI) Rec0 Rec1 WSR SCKR SDI0 SDI1 WST SCKT SDO0 SDO1 SDO2 Tran0 Tran1 Tran2 MODA/IRQA MODB/IRQB MODC/NMI RESET Interrupt /Mode Control H0–H7 H
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Signal Descriptions Power 2.2 POWER Table 2-2 Power Inputs Power Name Description VCCP PLL Power—VCCP is VCC dedicated for Phase Lock Loop (PLL) use. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. VCCP should be bypassed to GNDP by a 0.1 µF capacitor located as close as possible to the chip package. VCCQ Quiet Power—VCCQ is an isolated power for the internal processing logic.
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Signal Descriptions Ground 2.3 GROUND Table 2-3 Grounds Ground Name Description GNDP PLL Ground—GNDP is ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.1 µF capacitor located as close as possible to the chip package. GNDQ Internal Logic Ground—GNDQ is an isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections.
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Signal Descriptions Phase Lock Loop (PLL) 2.4 PHASE LOCK LOOP (PLL) Table 2-4 Phase Lock Loop Signals Type State During Reset Output Indeterminate Signal Name PLOCK Signal Description Phase Locked—PLOCK is an output signal that, when driven high, indicates that the PLL has achieved phase lock. After Reset, PLOCK is driven low until lock is achieved. Note: PCAP Input Input PLOCK is a reliable indicator of the PLL lock state only after the chip has exited the Reset state.
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Signal Descriptions Interrupt and Mode Control 2.5 INTERRUPT AND MODE CONTROL Table 2-5 Interrupt and Mode Control Signal Name MODA/IRQA Type State During Reset Input Input Signal Description Mode Select A/External Interrupt Request A—This input has two functions: 1. to select the initial chip operating mode, and 2. after synchronization, to allow an external device to request a DSP interrupt. MODA is read and internally latched in the DSP when the processor exits the Reset state.
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Signal Descriptions Interrupt and Mode Control Table 2-5 Interrupt and Mode Control (Continued) Signal Name MODC/NMI Type State During Reset Input Input Signal Description Mode Select C/Non-maskable Interrupt Request— This input has two functions: 1. to select the initial chip operating mode, and 2. after internal synchronization, to allow an external device to request a non-maskable DSP interrupt. MODC is read and internally latched in the DSP when the processor exits the Reset state.
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Signal Descriptions Host Interface (HI) 2.6 HOST INTERFACE (HI) The HI provides a fast parallel data to 8-bit port, which may be connected directly to the host bus. The HI supports a variety of standard buses, and can be directly connected to a number of industry standard microcomputers, microprocessors, DSPs, and DMA hardware.
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Signal Descriptions Host Interface (HI) Table 2-6 Host Interface (Continued) Signal Name HR/W PB11 Type State During Reset Input Input Input/ Output Signal Description Host Read/Write—This input selects the direction of data transfer for each host processor access. If HR/W is high and HEN is asserted, H0–H7 are outputs and DSP data is transferred to the host processor. If HR/W is low and HEN is asserted, H0–H7 are inputs and host data is transferred to the DSP.
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Signal Descriptions Host Interface (HI) Table 2-6 Host Interface (Continued) Signal Name HACK Type State During Reset Input Input Signal Description Host Acknowledge— This input has two functions. It provides a host acknowledge handshake signal for DMA transfers and it receives a host interrupt acknowledge compatible with MC68000 family processors. Note: PB14 Input/ Output HACK should always be pulled high when it is not in use.
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Signal Descriptions Serial Host Interface (SHI) 2.7 SERIAL HOST INTERFACE (SHI) The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode. Table 2-7 Serial Host Interface (SHI) Signals Signal Name SCK/ SCL Signal Type Input or Output State during Reset Tri-stated Signal Description SPI Serial Clock/I2C Serial Clock—The SCK signal is an output when the SPI is configured as a master, and a Schmitt-trigger input when the SPI is configured as a slave.
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Signal Descriptions Serial Host Interface (SHI) Table 2-7 Serial Host Interface (SHI) Signals (Continued) Signal Name MISO/ SDA Signal Type Input or Output State during Reset Tri-stated Signal Description SPI Master-In-Slave-Out/I2C Data and Acknowledge—When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data.
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Signal Descriptions Serial Host Interface (SHI) Table 2-7 Serial Host Interface (SHI) Signals (Continued) Signal Name SS/HA2 Signal Type Input State during Reset Tri-stated Signal Description SPI Slave Select/I2C Slave Address 2—This signal is an active low Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI Master mode, this signal should be kept deasserted.
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Signal Descriptions Serial Audio Interface (SAI) 2.8 SERIAL AUDIO INTERFACE (SAI) The SAI is composed of separate receiver and transmitter sections. 2.8.1 SAI Receive Section The receive section of the SAI has four dedicated signals. Table 2-8 Serial Audio Interface (SAI) Receive Signals Signal Name SDI0 Signal Type Input State during Reset Signal Description Tri-stated Serial Data Input 0—This is the receiver 0 serial data input.
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Signal Descriptions Serial Audio Interface (SAI) 2.8.2 SAI Transmit Section The transmit section of the SAI has five dedicated signals. Table 2-9 Serial Audio Interface (SAI) Transmit Signals Signal Name Signal Type State during Reset Signal Description SDO0 Output Driven high Serial Data Output 0—SDO0 is the transmitter 0 serial output. SDO0 is driven high if transmitter 0 is disabled, during personal reset, hardware reset and software reset, or when the chip is in the Stop state.
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Signal Descriptions General Purpose Input/Output (GPIO) 2.9 GENERAL PURPOSE INPUT/OUTPUT (GPIO) Table 2-10 General Purpose I/O (GPIO) Signals Signal Name GPIO0– GPIO7 2.10 Signal Type Input or Output (standard or open-drain) State during Reset Disconnected internally Signal Description General Purpose Input/Output—These signals are used for control and handshake functions between the DSP and external circuitry.
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Signal Descriptions OnCE Port 2.11 OnCE PORT Table 2-12 On-Chip Emulation Port (OnCE) Signals Signal Name Signal Type State during Reset DSI/OS0 Input/O utput Low Output Signal Description Debug Serial Input/Chip Status 0—Serial data or commands are provided to the OnCE controller through the DSI/OS0 signal when it is an input. The data received on the DSI signal will be recognized only when the DSP has entered the Debug mode of operation.
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Signal Descriptions OnCE Port Table 2-12 On-Chip Emulation Port (OnCE) Signals (Continued) Signal Name DSO Signal Type Output State during Reset Pulled high Signal Description Debug Serial Output—Data contained in one of the OnCE controller registers is provided through the DSO output signal, as specified by the last command received from the external command controller. Data is always shifted out the OnCE serial port MSB first. Data is clocked out of the OnCE serial port on the rising edge of DSCK.
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SECTION 3 MEMORY, OPERATING MODES, AND INTERRUPTS
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Memory, Operating Modes, and Interrupts SECTION 3.1 3.2 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.5 3.6 3.7 3.8 3-2 3 MEMORY, OPERATING MODES, AND INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 DSP56012 DATA AND PROGRAM MEMORY . . . . . . . . . . . 3-3 X and Y Data ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Bootstrap ROM . . . . . . . . . . . . . . . . . .
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Memory, Operating Modes, and Interrupts Introduction 3.1 INTRODUCTION The DSP56012 program and data memories are independent, and the on-chip data memory is divided into two separate memory spaces, X and Y. There are also two on-chip data ROMs in the X and Y data memory spaces, and a bootstrap ROM that can overlay part of the Program RAM. The data memories are divided into two independent spaces to work with the two Address ALUs to feed two operands simultaneously to the Data ALU.
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Memory, Operating Modes, and Interrupts DSP56012 Data and Program Memory Maps 3.2.1 X and Y Data ROM The X data ROM occupies locations $2000–$2DFF in the X memory space. The Y data ROM occupies locations $2000–$27FF in the Y memory space. 3.2.2 Bootstrap ROM The bootstrap ROM allows the user to use the on-chip pre-loaded Program ROM or load a program into the first 256 words of Program RAM and use it for applications. The bootstrap ROM occupies locations 0–31 ($0–$1F) in the DSP56012 memory map.
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Memory, Operating Modes, and Interrupts DSP56012 Data and Program Memory Maps 3.3.1 Reserved Memory Spaces Certain areas of the memory maps are labelled ‘reserved.’ Memory spaces marked as reserved should not be accessed by the user. They are reserved to retain compatibility with future enhanced or derivative versions of this device. Write operations to the reserved range are ignored.
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Memory, Operating Modes, and Interrupts DSP56012 Data and Program Memory Maps Figure 3-2 Memory Maps for PEA = 1, PEB = 0 3-6 DSP56012 User’s Manual MOTOROLA
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Memory, Operating Modes, and Interrupts DSP56012 Data and Program Memory Maps Figure 3-3 Memory Maps for PEA = 0, PEB = 1 MOTOROLA DSP56012 User’s Manual 3-7
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Memory, Operating Modes, and Interrupts DSP56012 Data and Program Memory Maps Figure 3-4 Memory Maps for PEA = 1, PEB = 1 3.3.2 Dynamic Switch of Memory Configurations The internal memory configuration is altered by re-mapping RAM modules from X and Y data memories into program memory space and vice versa. Data contents of the switched RAM modules are preserved. The memory can be dynamically switched from one configuration to another by changing the PEA and PEB bits in the OMR.
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Memory, Operating Modes, and Interrupts DSP56012 Data and Program Memory Maps • No accesses (including instruction fetches) to/from P:$0200–$0AFF are allowed during the switch cycle. Note: The switch actually occurs three instruction cycles after the instruction that modifies the PEA/PEB bits. Any sequence that complies with the switch conditions is valid.
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Memory, Operating Modes, and Interrupts DSP56012 Data and Program Memory Maps ANDI ANDI #$F3,OMR #$FC,MR JMP >Next_Address ; ; ; ; Clear PEA/PEB bit in OMR Allow a delay for remapping, meanwhile re-enable interrupts 2-word (long) jump instruction (uninterruptable) “Next_Address” is any valid program address in the new memory configuration (after the switch).
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Memory, Operating Modes, and Interrupts DSP56012 Data and Program Memory Maps Table 3-2 Internal I/O Memory Map (Continued) Location Register X: $FFF5 Reserved X: $FFF4 Reserved X: $FFF3 SHI Receive FIFO/Transmit Register (HRX/HTX) X: $FFF2 SHI I2C Slave Address Register (HSAR) X: $FFF1 SHI Host Control/Status Register (HCSR) X: $FFF0 SHI Host Clock Control Register (HCKR) X: $FFEF Reserved X: $FFEE Port B Data Register (PBD) X: $FFED Port B Data Direction Register (PBDDR) X: $FFEC Por
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Memory, Operating Modes, and Interrupts Operating Mode Register (OMR) 3.4 OPERATING MODE REGISTER (OMR) The Operating Mode Register (OMR) is illustrated in Figure 3-5. 23 7 6 SD 5 4 3 2 1 MC PEB PEA MB 0 MA Operating Mode A,B Program RAM Enable A Program RAM Enable B Operating Mode C Stop Delay Bits 5 and 7–23 are reserved, read as 0s, and should be written with 0s for future compatibility. AA0291k Figure 3-5 Operating Mode Register (OMR) 3.4.
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Memory, Operating Modes, and Interrupts Operating Modes T states). When the DSP is driven by a stable external clock source, setting the SD bit before executing the STOP instruction will allow a faster start up of the DSP. 3.5 OPERATING MODES The DSP56012 operating modes are defined as described below and summarized in Table 3-3. The operating modes are latched from pins MODA, MODB, and MODC during reset and can be changed by writing to the OMR.
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Memory, Operating Modes, and Interrupts Operating Modes ends up in the first location of the Program ROM (program address $0A00). Note: It is not possible to reach operating Mode 4 during hardware reset. Any attempt to start up in Mode 4 defaults to Mode 1. Mode 5 In this mode, the bootstrap ROM is enabled and the bootstrap program is executed after hardware reset. The internal Program RAM is loaded with 256 words from the Serial Host Interface (SHI).
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Memory, Operating Modes, and Interrupts Interrupt Priority Register 3.6 INTERRUPT PRIORITY REGISTER Interrupt priorities are determined in the 24-bit Interrupt Priority Register (IPR). The Interrupt Priority Level (IPL) for each on-chip peripheral device and for two of the external interrupt sources can be programmed, under software control, to one of three maskable priority levels (IPL 0,1 or 2). IPLs are set by writing to the IPR. The IPR configuration is shown in Figure 3-6.
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Memory, Operating Modes, and Interrupts Interrupt Priority Register 11 10 9 8 7 6 SAL1 SAL0 5 4 3 2 1 0 IBL2 IBL1 IBL0 IAL2 IAL1 IAL0 IRQA Mode IRQB Mode Reserved SAI IPL 23 22 21 20 19 18 17 16 15 14 13 12 DTL1 DTL0 HPL1 HPL0 SHL1 SHL0 SHI IPL Host IPL DAX IPL Reserved Reserved, read as 0, and should be written with 0 for future compatibility AA0292.
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Memory, Operating Modes, and Interrupts Interrupt Priority Register Table 3-4 Interrupt Priorities (Continued) Priority Interrupt SAI Right Channel Receiver SAI Right Channel Transmitter SHI Bus Error SHI Receive Overrun Error SHI Transmit Underrun Error SHI Receive FIFO Full SHI Transmit Data SHI Receive FIFO Not Empty HOST Command Interrupt HOST Receive Data Interrupt HOST Transmit Data Interrupt DAX Transmit Underrun Error DAX Block Transferred Lowest DAX Transmit Register Empty Table 3-5 Interrupt
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Memory, Operating Modes, and Interrupts Interrupt Priority Register Table 3-5 Interrupt Vectors (Continued) Address Interrupt Source P: $0018 SAI Right Channel Receiver if RXIL = 0 P: $001A SAI Receiver Exception if RXIL = 0 P: $001C Reserved P: $001E NMI P: $0020 SHI Transmit Data P: $0022 SHI Transmit Underrun Error P: $0024 SHI Receive FIFO Not Empty P: $0026 Reserved P: $0028 SHI Receive FIFO Full P: $002A SHI Receive Overrun Error P: $002C SHI Bus Error P: $002E Reserved P: $
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Memory, Operating Modes, and Interrupts Phase Lock Loop (PLL) Configuration Table 3-5 Interrupt Vectors (Continued) Address Interrupt Source P: $0052 DAX Block Transferred P: $0054 Reserved P: $0056 DAX Transmit Register Empty P: $0058 Reserved . . . . . . P: $007E Reserved 3.7 PHASE LOCK LOOP (PLL) CONFIGURATION Section 9 of the DSP56000 Family Manual provides detailed information about the PLL. The information included here is a brief overview of the PLL.
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Memory, Operating Modes, and Interrupts Operation on Hardware Reset EXTAL Phase Detector (PD) Charge Pump Loop Filter Voltage Controlled Oscillator (VCO) Low Power Divider 20 to 215 Divider Out DF[3:0] VCO Out Frequency Multiplier Multiplication Factor 1 to 4096 MF[11:0] AA0293k Figure 3-7 PLL Configuration 3.8 OPERATION ON HARDWARE RESET The processor enters the Reset processing state when the external RESET pin is asserted (hardware reset occurs).
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SECTION 4 PARALLEL HOST INTERFACE MOTOROLA DSP56012 User’s Manual 4-1
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Parallel Host Interface 4.1 4.2 4.3 4.4 4-2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PORT B CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . PROGRAMMING THE GPIO. . . . . . . . . . . . . . . . . . . . . . . . . HOST INTERFACE (HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Parallel Host Interface Introduction 4.1 INTRODUCTION The parallel Host Interface (HI) can serve as an 8-bit, bidirectional parallel port or, as Port B, a set of General Purpose Input/Output (GPIO) signals (see Figure 4-1). When configured as the HI, the port provides a convenient connection to another processor. Port B supports up to fifteen GPIO pins, each pin individually configurable as an output or an input.
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Parallel Host Interface Port B Configuration 23 X:$FFEC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Parallel I/O (Reset Condition) 0 1 HI 1 0 HI (with HACK pin as GPIO) 1 1 Reserved 0 0 0 0 0 0 0 0 0 0 0 Function 0 Port B Data BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD Direction 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register (PBDDR) 0 23 0 0 BC0 BDx X:$FFEE 0 0 BC1 23 X:$FFED 0 0 0 Port B Control BC BC Register 0 1 0 (PBC) 0 Data Direction 0 Input (Rese
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Parallel Host Interface Port B Port B Configuration PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 Enabled by bits in X:$FFEC Direction Selected by bits in X:$FFED Input/Output Data X:$FFEE BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BC0/BC1 BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9 BD10 BD11 BD12 BD13 BD14 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PBDDR PBD PBC AA0309.
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Parallel Host Interface Port B Configuration Port Control Register Bit Data Direction Register Bit Pin Function 0 0 Port B Input Pin 0 1 Port B Output Pin 1 X HI Function Port B Data (PBD) Register Bit Port B Registers Pin (GPIO Position) Data Direction Register (PBDDR) Bit Port B Control Register (PBC) Bit (Input Position) Port B Input Data Bit HI Output Data Bit Peripheral Logic HI Data Direction Bit HI Input Data Bit AA0310.11 Figure 4-4 Port B I/O Pin Control Logic 4.2.
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Parallel Host Interface Port B Configuration 4.2.2 Port B Data Direction Register (PBDDR) For pins configured as GPIO by the PBC Register, the Port B Data Direction Register (PBDDR) determines whether the pins are inputs (bit = 0) or outputs (bit = 1). Note: The default setting after reset is input. 4.2.
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Parallel Host Interface Programming the GPIO 4.3 PROGRAMMING THE GPIO The DSP56012 on-chip peripheral memory map is illustrated in Section 3, Memory, Operating Modes, and Interrupts and in Appendix B, Programming Reference. The standard MOVE instruction transfers data between Port B and a register. As a result, MOVE takes two instructions to perform a memory-to-memory data transfer and uses a temporary holding register.
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Parallel Host Interface Host Interface (HI) Step 1. Activate Port B For General Purpose I/O: Write 0s to Bits 0 And 1 15 0 BC BC 1 0 X:$FFEC Port B Control Register (PBC) Step 2. Set Individual Pins To Input Or Output: BDxx = 0 Input or BDxx = 1 Output 15 0 BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X:$FFED Port B Data Direction Register (PBDDR) Step 3.
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Parallel Host Interface Host Interface (HI) 4.4.1 HI Features • Speed—6.6 million words/sec (19.
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Parallel Host Interface Host Interface (HI) – I/O short addressing provides faster execution with fewer instruction words. • Interface—Host side – Mapping: • Eight consecutive memory locations • Memory-mapped peripheral for microprocessors, DMA controllers, etc.
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Parallel Host Interface Host Interface (HI) • $0 ICR Interrupt Control Register (Read/Write) $1 CVR Command Vector Register (Read/Write) $2 ISR Interrupt Status Register (Read Only) $3 IVR Host MPU Data Bus Interrupt Vector Register (Read/write) 8 H[7:0] $5 RXH $6 RXM Receive Byte Registers (Read Only) 24 DSP CPU Global Data Bus X:$FFE8 HCR X:$FFE9 HSR $5 TXH Host Status Register (Read Only) Control Logic X:$FFEB HOTX $7 RXL Transmit Byte Registers Host Control Register (Read/Write) X
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Parallel Host Interface Host Interface (HI) standard instructions and addressing modes. The MOVEP instruction allows host-to-memory and memory-to-host data transfers with no intermediate register. 4.4.4 Programming Model—DSP Viewpoint The HI has two programming models: one for the DSP programmer and one for the host processor programmer. In most cases, the notation used reflects the DSP perspective. The host-to-HI programming model is shown in Figure 4-8.
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Parallel Host Interface Host Interface (HI) DSP CPU Flags Host Flag 3 Host Flag 2 7 0 X:$FFE8 0 0 HF3 (0) 0 HF2 HCIE HTIE HRIE Host Control Register (HCR) (0) (0) (0) (0) (Read/Write) Interrupt Enables Host Receive Host Transmit Host Command Host Flags Host Flag 1 Host Flag 0 7 X:$FFE9 0 DMA (0) 0 HF1 (0) 0 HF0 (0) HCP HTDE HRDF Host Status Register (HSR) (0) (1) (0) (Read Only) Host Receive Data Full Host Transmit Data Empty Host Command Pending 23 16 15 8 7 0 X:$FFEB Receive High By
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Parallel Host Interface Host Interface (HI) portion is 0-filled. Any reserved bits are read as 0s and should be written with 0s for compatibility with future revisions. Bit manipulation instructions are useful for accessing the individual bits in the HCR. The control bits are described in the following paragraphs. Note: The contents of the HCR are cleared by hardware reset or software reset. 4.4.4.1.
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Parallel Host Interface Host Interface (HI) Note: Hardware reset and software reset clear HF3. Note: There are four general purpose host flags: two used by the host to signal the DSP (HF0 and HF1), and two used by the DSP to signal the host processor (HF2 and HF3). They are not designated for any specific purpose. These four flags do not generate interrupts; they must be polled. These flags can be used individually or as encoded pairs. See Section 4.4.4.
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Parallel Host Interface Host Interface (HI) 4.4.4.2.3 HSR HI Command Pending (HCP)—Bit 2 The HI Command Pending (HCP) bit indicates that the host has set the HC bit and that a host command interrupt is pending. The HCP bit reflects the status of the Host Command (HC) bit in the Command Vector Register (CVR). HC and HCP are cleared by the DSP interrupt hardware when the interrupt is taken. The host can clear HC, which also clears HCP.
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Parallel Host Interface Host Interface (HI) Host to DSP56012 Status Flags 7 Host $0 0 INIT HM1 HM0 HF1 HF0 0 TREQ RREQ 7 DSP56012 X:$FFE9 0 DMA 0 0 HF1 HF0 HCP HTDE HRDF Interrupt Control Register (ICR) (Read/write) Host Status Register (HSR) (Read Only) DSP56012 to Host Status Flags 7 Host 0 $2 HOREQ DMA 0 HF3 HF2 TRDY TXDE RXDF 7 DSP56012 X:$FFE8 0 0 0 0 HF3 HF2 HCIE HTIE HRIE Interrupt Status Register (ISR) (Read Only) Host Control Register (HCR) (Read/write) AA
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Parallel Host Interface Host Interface (HI) (TXDE) and DSP HI Receive Data Full (HRDF) bits are cleared. This transfer operation sets TXDE and HRDF. The HORX register contains valid data when the HRDF bit is set. Reading HORX clears HRDF. The DSP can program the HRIE bit to cause a host-receive-data interrupt when HRDF is set. Note: Resets do not affect HORX. 4.4.4.4 HI Transmit Data Register (HOTX) The HI Transmit data register (HOTX) is used for DSP-to-host data transfers.
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Parallel Host Interface Host Interface (HI) Table 4-1 HI Registers after Reset—DSP CPU Side (Continued) Reset Type 4.4.4.6 Register Name Register Data HSR X:$FFE9 HW Reset SW Reset IR Reset ST Reset DMA 0 0 0 0 HF[1:0] 0 0 0 0 HCP 0 0 0 0 HTDE 1 1 1 1 HRDF 0 0 0 0 HORX X:$FFEB HORX [23:0] — — — — HOTX X:$FFEB HOTX [23:0] — — — — DSP Interrupts The HI interface can request interrupt service from either the DSP or the host processor.
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Parallel Host Interface Host Interface (HI) 4.4.4.7 HI Usage Considerations—DSP Side Synchronization is a common problem when two asynchronous systems are connected, and careful synchronization is required when reading multiple-bit registers that are written by another asynchronous system. The considerations for proper operation on the DSP CPU side are discussed in the following paragraphs, and considerations for the host processor side are discussed in Section 4.4.8.
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Parallel Host Interface Host Interface (HI) transfers. The 32-bit MC68020 host processor can use its dynamic bus sizing feature to address the HI using standard MOVE word (16-bit), long-word (32-bit) or quad-word (64-bit) instructions. The HOREQ and HACK handshake flags are provided for polled or interrupt-driven data transfers with the host processor.
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Parallel Host Interface Host Interface (HI) Modes Flags 7 0 INIT (0) $0 HM1 (0) HM0 (0) 0 0 Interrupt Mode (DMA Off) 0 1 24-Bit DMA Mode 1 0 GPIO-Bit DMA Mode 1 1 8-Bit DMA Mode 7 HF0 (0) TREQ RREQ Interrupt Control Register (ICR) (Read/Write) (1) (0) 0 5 HC (0) $1 HF1 (0) 0 Host Vector ($17) 0 Flags Command Vector Register (CVR) (Read/Write) Status 7 $2 0 HOREQ DMA (0) (0) 0 HF3 (0) HF2 (0) TRDY TXDE RXDF Interrupt Status Register (ISR) (Read Only) (1) (1) (0) 7
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Parallel Host Interface Host Interface (HI) $0 ICR Interrupt Control $1 CVR Command Vector $2 ISR Interrupt Status Host Address $3 HOA[2:0] $4 IVR Interrupt Vector 00000000 $5 RXH/TXH $6 RXM/TXM $7 RXL/TXL Unused Receive/Transmit Bytes HI Data Bus H[7:0] AA0320k Figure 4-11 HI Register Map 4.4.5.3 Interrupt Control Register (ICR) The Interrupt Control Register (ICR) is an 8-bit read/write control register used by the host processor to control the HI interrupts and flags.
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Parallel Host Interface Host Interface (HI) In DMA modes, TREQ must be set or cleared by software to select the direction of DMA transfers. Setting TREQ sets the direction of DMA transfer to be host to DSP and enables the HOREQ pin to request data transfer. Note: Hardware reset, software reset, individual reset, and Stop mode clear TREQ. Table 4-2 summarizes the effect of RREQ and TREQ on the HOREQ pin.
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Parallel Host Interface Host Interface (HI) Mask 7 X:$FFE8 0 0 0 0 HF3 HF2 HCIE HTIE HRIE HCR DSP CPU Interrupts Receive Data Full P:$0030 Transmit Data Empty P:$0032 Host Command P:(2 × HV → $0000–$007E) Reset → HV = $0017 in CVR 7 X:$FFE9 DMA 0 0 0 HF1 HF0 HCP HTDE HRDF HSR Status AA0317.11 Figure 4-12 HSR and HCR Operation 4.4.5.3.5 ICR HI Flag 1 (HF1)—Bit 4 The HI Flag 1 (HF1) bit is used as a general purpose flag for host-to-DSP communication.
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Parallel Host Interface Host Interface (HI) When both HM1 and HM0 are cleared, the DMA mode is disabled, and the TREQ and RREQ control bits are used for host processor interrupt control via the external HOREQ output pin. Also, in the non-DMA mode, the HACK input pin is used for the MC68000-family vectored interrupt acknowledge input. When HM1 or HM0 are set, the DMA mode is enabled, and the HOREQ pin is used to request DMA transfers.
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Parallel Host Interface Host Interface (HI) Using the INIT bit to initialize the HI hardware may or may not be necessary, depending on the software design of the interface. The type of initialization performed when the INIT bit is set depends on the state of TREQ and RREQ in the HI. The INIT command, which is local to the HI, is designed to conveniently configure the HI into the desired data transfer mode. The commands are described in the following paragraphs and in Table 4-4.
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Parallel Host Interface Host Interface (HI) counter is not automatically updated, and, as a result, the DMA counter will point to the wrong data register immediately after HM1 and HM0 are changed. The INIT function must be used to correctly preset the internal DMA counter. Always set INIT after changing HM0 and HM1. However, the DMA counter can not be initialized in the middle of a DMA transfer.
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Parallel Host Interface Host Interface (HI) 4.4.5.5.2 CVR Reserved—Bit 6 This reserved bit is unused and read by the host processor as 0. 4.4.5.5.3 CVR Host Command (HC)—Bit 7 The Host Command (HC) bit is used by the host processor to handshake the execution of host command interrupts. Normally, the host processor sets HC to request the host command interrupt from the DSP. When the host command interrupt is acknowledged by the DSP, the HC bit is cleared by the HI hardware.
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Parallel Host Interface Host Interface (HI) 4.4.5.6.2 ISR Transmit Data Register Empty (TXDE)—Bit 1 The Transmit Data Register Empty (TXDE) bit indicates that the Transmit byte registers (TXH, TXM, and TXL) are empty and can be written by the host processor. TXDE is set when the transmit byte registers are transferred to the HORX register. TXDE is cleared when the Transmit byte Low (TXL) register is written by the host processor.
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Parallel Host Interface Host Interface (HI) 4.4.5.6.7 ISR DMA Status (DMA)—Bit 6 The DMA status (DMA) bit indicates that the host processor has enabled the DMA mode of the HI (HM1 or HM0 = 1). When the DMA status bit is clear, it indicates that the DMA mode is disabled (HM0 = HM1 = 0) and no DMA operations are pending.
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Parallel Host Interface Host Interface (HI) Receive Low (RXL). These three registers receive data from the high byte, middle byte, and low byte, respectively, of the HOTX register and are selected by three external host address inputs (HOA[2:0]) during a host processor read operation or by an on-chip address counter in DMA operations. The receive byte registers (at least RXL) contain valid data when the Receive Data Register Full (RXDF) bit is set.
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Parallel Host Interface Host Interface (HI) Table 4-5 HI Registers after Reset (Host Side) Reset Type Register Name Register Data ICR HW Reset SW Reset IR Reset ST Reset INIT 0 0 0 0 HM (1–0) 0 0 0 0 TREQ 0 0 0 0 RREQ 0 0 0 0 HF (1–0) 0 0 0 0 HC 0 0 0 0 HV (5–0) $17 $17 $17 $17 HOREQ 0 0 0 0 DMA 0 0 0 0 HF (3–2) 0 0 — — TRDY 1 1 1 1 TXDE 1 1 1 1 RXDF 0 0 0 0 IVR $3 IV (7–0) $0F $0F — — RXH $5 RXH (23–16) — — — — RXM $6 RXM
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Parallel Host Interface Host Interface (HI) 4.4.6 HI Signals The fifteen HI signals are described here for convenience. Additional information, including timing, is provided in the DSP56012 Technical Data sheet (DSP56012/D). 4.4.6.1 HI Data Bus (H0–H7) This bidirectional data bus transfers data between the host processor and the DSP56012. It acts as an input unless HEN is asserted and HR/W is high, making H[7:0] become outputs and allowing the host processor to read DSP56012 data.
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Parallel Host Interface Host Interface (HI) transfer request pin of a DMA controller, or a control input of external circuitry. HOREQ is asserted when an enabled request occurs in the HI. HOREQ is deasserted when the enabled request is cleared or masked, DMA HACK is asserted, or the DSP is reset. HOREQ can be programmed as a GPIO pin (not open-drain) called PB13 when the HI is not being used. 4.4.6.
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Parallel Host Interface Host Interface (HI) DSP56012 3 HOA0–HOA2 HOA0–HOA2 HR/W HR/W HEN HEN 8 H[7:0] H[7:0] +5 Write Data Latched In Host Read HOREQ +5 HACK AA0322.11 Figure 4-14 Host Processor Transfer Timing 4.4.
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Parallel Host Interface Host Interface (HI) 3. strobes the data transfer using HEN. When data is being written to the HI by the host processor, the positive-going edge of HEN latches the data in the selected HI register. When data is being read by the host processor, the negative-going edge of HEN strobes the data onto the data bus H0–H7. This process is illustrated in Figure 4-16 on page 4-40. The timing relationships are specified in the DSP56012 Technical Data sheet. 4.4.7.
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Parallel Host Interface Host Interface (HI) 5. DMA = 1, signifying the HI is currently being used for DMA transfers; if DMA transfers are possible in the system, deactivate HACK prior to reading the ISR so both DMA data and the contents of ISR are not simultaneously output on H0–H7. 6. If HOREQ = 1, the HOREQ pin has been asserted, and one of the previous five conditions exists. Generally, after the appropriate data transfer has been made, the corresponding status bit will toggle.
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Parallel Host Interface Host Interface (HI) 7 0 Interrupt Vector Number $3 Interrupt Vector Register (IVR) (Read/Write) +5 V MC68000 DSP56012 1. The DSP56012 Asserts HOREQ to interrupt the host processor. 1K IPL2 IPL1 IPL0 HOREQ 2. The host processor asserts HACK with its interrupt acknowledge cycle. HACK IACK A1–A31 IACK LOGIC FC0–FC2 AS 3. When HOREQ and HACK are asserted simultaneously, the contents of the IVR are placed on the host data bus.
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Parallel Host Interface Host Interface (HI) To IRQB +5 V IRQ CI +5 V D Q REQ0 DSP56012 MC68440 HOREQ +5 V ACK0 HACK A0 A1 AS OWN Burst REQ0 8T High Byte HACK Fast Interrupt To Transfer 24-bit Word Middle Byte High Byte Low Byte 1 DMA Cycle = 8T = 4 DMA Clock Cycles Max. MC68440 Clock = 10 MHz = > T = 50 ns DMA ACK Gated Off AA0325k Figure 4-17 DMA Transfer Logic and Timing 4.4.7.5 Servicing DMA Interrupts When HM0 ≠ 0 and/or HM1 ≠ 0, HOREQ will be asserted to request a DMA transfer.
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Parallel Host Interface Host Interface (HI) 4.4.8 Host Interface Application Examples The following paragraphs describe examples of initializing the HI, transferring data with the HI, bootstrapping via the HI, and performing DMA transfers through the HI. 4.4.8.1 HI Initialization Initializing the HI takes two steps (see Figure 4-18).
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Parallel Host Interface Host Interface (HI) STEP 1 of HI Port Configuration 1.Enable/Disable Host Receive Data Full Interrupt Enable Interrupt:Bit 0 = 1 Disable Interrupt:Bit 0 = 0 2.Enable/Disable Host Transmit Data Empty Interrupt Enable Interrupt: Bit 1 = 1 Disable Interrupt: Bit 1 = 0 3.Enable/Disable Host Command Pending Interrupt Enable Interrupt: Bit 2 = 1 Disable Interrupt: Bit 2 = 0 4.Set/Clear Host Flag 2 (Optional) Enable Flag: Bit 3 = 1 Disable Flag: Bit 3 = 0 5.
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Parallel Host Interface Host Interface (HI) Step 2 Of HI Port Configuration 2.
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Parallel Host Interface Host Interface (HI) Modes 7 Host Sets INIT Bit 6 5 INIT HM1 HM0 4 HF1 3 2 1 0 (Read/Write) 0 0 1 1 0 1 0 1 Reset Condition Interrupt Mode (DMA Off) 24-Bit DMA Mode 16-Bit DMA Mode 8-Bit DMA Mode DMA Mode Interrupt Mode (DMA Off) TREQ RREQ Interrupt Control Register HF0 HF00 TREQ RREQ (ICR) INIT Execution TREQ RREQ INIT Execution 0 0 INIT = 0; Address Counter = 00 0 0 INIT = 0; Address Counter = HM1, HM0 0 1 INIT = 0; RXDF = 0; HTDE = 1; Address Counter
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Parallel Host Interface Host Interface (HI) 10 Step 2 of HI Port configuration 2. Option 2: Select polling mode for Host-to-DSP communication Initialize DSP And HI Port Disable Interrupts Bit 0 = 0 Bit 1 = 0 DMA Off Bit 5 = 0 Bit 6 = 0 7 $0 INIT 6 Optional 5 HM1 HM0 4 3 HF1 HF0 2 1 0 Interrupt Control Register (ICR) TREQ RREQ (Read/Write) AA0330k Reserved; write as 0. Figure 4-22 HI Initialization—Host Side, Polling Mode Step 2 Of HI Port Configuration 1.
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Parallel Host Interface Host Interface (HI) 5. Assert HEN to enable the HI. 6. When HEN is deasserted, the data can be latched or read as appropriate if the timing requirements have been observed. 7. HOREQ will be deasserted if the operation is complete. This transfer description is an overview. Specific and exact information for HI data transfers and their timing can be found in 4.4.8.3 DMA Data Transfer and in the DSP56012 Technical Data sheet (DSP56012/D). Step 2 Of Host Port configuration 2.
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4-48 6 HF3 5 0 4 HF3 3 HF2 2 TRDY 1 TXDE 0 INTERRUPT STATUS REGISTER (ISR) (READ ONLY) $0 DSP56012 User’s Manual HM0 0 1 0 1 0 0 1 1 5 HM1 6 HF0 3 0 2 8 Bit DMA Mode 16 Bit DMA Mode 24 Bit DMA Mode 1 0 TREQ RREQ Interrupt Mode (DMA Off) HF1 4 INTERRUPT CONTROL REGISTER (ICR) (READ/WRITE) DMA 0 6 0 5 HF1 4 HF0 3 HCP 2 DSP56012 HTDE 1 HOST STATUS HRDF REGISTER (HSR) (READ ONLY) 0 HOREQ 7 HM1 6 HM0 5 HF1 4 HF0 3 DSP INTERRUPT IS CAUSED BY HRDF = 1 1 = INTER
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Parallel Host Interface Host Interface (HI) 4.4.8.2.1 Host to DSP—Data Transfer Figure 4-26 on page 4-50 shows the bits in the ISR and ICR used by the host processor and the bits in the HSR and HCR used by the DSP to transfer data from the host processor to the DSP. The registers shown are the status register and control register as they are seen by the host processor, and the status register and control register as they are seen by the DSP.
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4-50 6 0 5 INIT HF2 3 0 2 HM0 HM1 HF1 4 HF0 3 0 2 TREQ TRANSMIT REQUEST ENABLE 0 0 5 1 1 1 1 RREQ 0 DSP56012 User’s Manual LAST WRITE TRANSMIT BYTE REGISTERS (TBR) TXL $6 $7 TXH TXM $5 7 5. WRITE TO TXL CLEARS TXDE IN ISR. 0 0 0 5 HF0 3 HCP 2 HTDE HRDF HOST RECEIVE DATA FULL HF1 4 23 HIGH BYTE MIDDLE BYTE 0 0 6 HF3 4 HF2 3 HCIE 2 P:$0030 HTIE HRIE HOST RECEIVE INTERRUPT ENABLE 0 5 FAST INTERRUPT OR LONG INTERRUPT HOST RECEIVE DATA VECTOR 10.
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Parallel Host Interface Host Interface (HI) The MAIN PROGRAM initializes the Host and then hangs in a wait loop while it allows interrupts to transfer data from the host processor to the DSP. The first three MOVEP instructions enable the Host and configure the interrupts. The following MOVE enables the interrupts (this should always be done after the interrupt programs and hardware are completely initialized) and prepares the DSP CPU to look for the host flag, HF0 = 1.
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4-52 DSP56012 User’s Manual 0 HC HOST COMMAND 1 5 COMMAND VECTOR REGISTER (CVR) $1 5 0 7 0 HC—HOST COMMAND (STATUS) HOST VECTOR (HV) 0 DMA 0 6 HF1 4 HF0 3 HCP HOST COMMAND PENDING 0 5 0 6 0 5 HF3 4 HF2 3 P:$007E P:$0034 1 2 1 2 FAST INTERRUPT OR LONG INTERRUPT AVAILABLE FOR HOST COMMAND AVAILABLE FOR HOST COMMAND AVAILABLE FOR HOST COMMAND HOST COMMAND DEFAULT VECTOR interrupt VECTOR TABLE HCIE HOST COMMAND INTERRUPT ENABLE 0 P:$0000 X:$FFE8 7 4.
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Parallel Host Interface Host Interface (HI) The process to execute an HC (see Figure 4-28) is as follows: 1. The host processor writes the CVR with the desired HV (the HV is the DSP’s interrupt vector (IV) location divided by two, i.e., if HV = $17, IV = $34). 2. The HC bit is then set. 3. The HCP bit in the HSR is set when the HC bit is set. 4. If the HCIE bit in the HCR has been set by the DSP, the HC interrupt processing will start.
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Parallel Host Interface Host Interface (HI) 4.4.8.2.3 Host to DSP—Bootstrap Loading Using the HI The circuit shown in Figure 4-31 will cause the DSP to boot through the HI on power up. During the bootstrap program, the DSP looks at the MODC, MODB, and MODA bits. If the MODC:MODB:MODA bits = 001, the DSP will load from the HI.
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Parallel Host Interface Host Interface (HI) +5 V FROM OPEN COLLECTOR BUFFER DR HEN LDS F32 HACK AS F32 MODA/IRQA ADDRESS DECODE MODC/NMI A4–A23 MC68000 +5 V DSP56012 FROM RESET FUNCTION MDB301* LS09 DTACK RESET F32 HR/W MDB301* FROM OPEN COLLECTOR BUFFER F32 8 H[7:0] $0 (12.5 MHz) 1K 3 HOA0–HOA2 R/W D0–D7 A1–A3 MODB/IRQB HOST 7 6 5 4 3 2 1 INIT HM1 HM0 HF1 HF0 0 TREQ Notes: 1. *This diode must be a Schottky diode. 2.
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Parallel Host Interface Host Interface (HI) 4.4.8.2.4 DSP to Host—Data Transfer Data transfers from the DSP to the host processor are similar to transfers from the host processor to the DSP. Figure 4-35 on page 4-60 shows the bits in the status registers (ISR and HSR) and control registers (ICR and HCR) used by the host processor and DSP CPU, respectively.
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MOTOROLA 6 0 5 HF3 4 HF2 3 TRDY 2 TXDE 1 RXDF 0 $0 HM1 6 HM0 5 HF1 4 HF0 3 0 2 0 TREQ RREQ 1 INTERRUPT CONTROL REGISTER (ICR) (READ/WRITE) INTERRUPT STATUS REGISTER (ISR) (READ ONLY) DSP56012 User’s Manual DMA 0 6 0 5 HF1 4 HF0 3 HCP 2 DSP56012 0 7 0 6 0 5 HF3 4 HF2 3 HTIE—HOST TRANSMIT INTERRUPT ENABLE 1 = ENABLE THE DSP INTERRUPT TO P:$0032. 0 = DISABLE THE DSP INTERRUPT TO P:$0032.
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4-58 RECEIVE BYTE REGISTERS (RBR) RXL RXM $6 $7 6 DSP56012 User’s Manual HM0 HM1 INIT HF1 4 HF3 4 0 2 TXDE 1 TREQ 1 RXDF RECEIVE DATA FULL TRDY 2 RREQ RECEIVE REQUEST ENABLE HF0 3 HF2 3 1 0 1 0 INTERRUPT CONTROL REGISTER (ICR) INTERRUPT STATUS REGISTER (ISR) HOREQ PIN 0 HF1 4 0 7 HCP 2 0 5 HF3 4 HF2 3 HCIE 2 HTIE HOST TRANSMIT INTERRUPT ENABLE 0 6 HF0 3 HTDE HOST TRANSMIT DATA EMPTY 0 5 2. DSP56012 can POLL HTDE.
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Parallel Host Interface Host Interface (HI) The code shown in Figure 4-34 is essentially the same as the MAIN PROGRAM in Figure 4-29 on page 4-53 except that, since this code will transmit instead of receive data, the HTIE bit in the HCR is set instead of the HRIE bit. The transmit routine used by the code in Figure 4-34 is illustrated in Figure 4-36 on page 4-61. The interrupt vector contains a JSR, which makes it a long interrupt.
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Parallel Host Interface Host Interface (HI) +5 V DMA CONTROLLER 1K DSP56012 HOST INTERFACE HOREQ TRANSFER REQUEST INTERNAL ADDRESS COUNTER TRANSFER ACKNOWLEDGE HACK H[7:0] MEMORY R/W CONTROL ADDRESS DATA Characteristics of HI DMA Mode • The HOREQ pin is NOT available for host processor interrupts. • TREQ and RREQ select the direction of DMA transfer. —DMA to DSP56012 —DSP56012 to DMA —Simultaneous bidirectional DMA transfers are not permitted.
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Parallel Host Interface Host Interface (HI) XFEREQ HOREQ DSP56012 DMA CONTROLLER HACK XFERACK 24-BIT TRANSFER (INTERNAL COUNTER) H (01) M (10) L (11) H (01) M (10) L (11) 16-BIT TRANSFER (INTERNAL COUNTER) M (10) L (11) M (10) L (11) M (10) L (11) 8-BIT TRANSFER (INTERNAL COUNTER) L (11) HOST RECEIVE INTERRUPT L (11) L (11) L (11) L (11) FAST INTERRUPT ROUTINE P:$0030 MOVE X:$FFE8, A READ HORX P:$0031 MOVE A, Y:(R7)+; AND PUT INTO Y MEMORY L (11) AA0342.
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Parallel Host Interface Host Interface (HI) When the transfer to HORX occurs within the HI, HRDF is set. Assuming HRIE = 1, a host receive interrupt will be generated. The interrupt routine must read the HORX to clear HRDF. Note: The transfer of data from the TXH, TXM, TXL registers to the HORX register automatically loads the DMA address counter from the HM1 and HM0 bits in the DMA (in the host-to-DSP mode).
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MOTOROLA 9. TERMINATE DSP DMA MODE BY CLEARING HM1, HM0, AND TREQ. 8. TERMINATE DMA CHANNEL. 5. HOST IS FREE TO PERFORM OTHER TASKS (i.e., DSP TO HOST TRANSFER ON A POLLED BASIS). 3. TELL DSP56012 —WHERE TO STORE DATA (i.e., PROGRAM ADDRESS REGISTER R7). —ENABLE INTERRUPT HRIE (CAN BE DONE WITH A HOST COMMAND). 2. INITIALIZE DSP56012 HOST INTERFACE. —MODE 24 BIT DMA —HOST TO DSP —USE INIT BIT TO: SET TXDE CLEAR HRDF LOAD DMA COUNTER 1. PROGRAM DMA CONTROLLER.
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Parallel Host Interface Host Interface (HI) The HOREQ will be active immediately after initialization is completed (depending on hardware) because the default data direction is from the host to the DSP, and TXH, TXM, and TXL registers are empty. When the host writes data to TXH, TXM, and TXL, this data will be immediately transferred to the HORX. If the DSP is due to work in Interrupt mode, HRIE must be enabled. 4.4.8.3.
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Parallel Host Interface Host Interface (HI) 4.4.8.3.4 DSP to Host—DMA Procedure The following procedure outlines the typical steps that the host processor must take to setup and terminate a DSP-to-host DMA transfer. 1. Set up the DMA controller (1) destination address, byte count, direction, and other control registers. Enable the DMA controller channel. 2. Initialize the HI (2) by writing the ICR to select the word size (HM0 and HM1), the direction (TREQ = 0, RREQ = 1), and setting INIT = 1. 3.
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Parallel Host Interface Host Interface (HI) 4.4.8.4.2 Overwriting Transmit Byte Registers The host programmer should not write to the transmit byte registers, TXH, TXM, or TXL, unless the TXDE bit is set, indicating that the transmit byte registers are empty. This guarantees that the DSP will read stable data when it reads the HORX register. 4.4.8.4.
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Parallel Host Interface Host Interface (HI) uncertainties of pipelined interrupt processing. For this reason, the HV should not be changed at the same time the HC bit is cleared. However, the HV can be changed when the HC bit is set. 4.4.8.4.6 Coordinating Data Transfers When using the HOREQ pin for handshaking, wait until HOREQ is asserted and then start writing/reading data using HEN or the HACK pin.
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Parallel Host Interface Host Interface (HI) 4-68 DSP56012 User’s Manual MOTOROLA
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SECTION 5 SERIAL HOST INTERFACE MOTOROLA DSP56012 User’s Manual 5-1
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Serial Host Interface 5.1 5.2 5.4 5.5 5.6 5.7 5-2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 SERIAL HOST INTERFACE INTERNAL ARCHITECTURE . 5-4 SERIAL HOST INTERFACE PROGRAMMING MODEL. . . . 5-5 CHARACTERISTICS OF THE SPI BUS . . . . . . . . . . . . . . . 5-19 CHARACTERISTICS OF THE I2C BUS . . . . . . . . . . . . . . . 5-20 SHI PROGRAMMING CONSIDERATIONS . . . . . . . . . . . .
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Serial Host Interface Introduction 5.1 INTRODUCTION The Serial Host Interface (SHI) is a serial I/O interface that provides a path for communication and program/coefficient data transfers between the DSP and an external host processor. The SHI can also communicate with other serial peripheral devices.
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Serial Host Interface Serial Host Interface Internal Architecture 5.2 SERIAL HOST INTERFACE INTERNAL ARCHITECTURE The DSP views the SHI as a memory-mapped peripheral in the X data memory space. The DSP may use the SHI as a normal memory-mapped peripheral using standard polling or interrupt programming techniques. Memory mapping allows DSP communication with the SHI registers to be accomplished using standard instructions and addressing modes.
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Serial Host Interface SHI Clock Generator 5.3 SHI CLOCK GENERATOR The SHI clock generator generates the serial clock to the SHI if the interface operates in the Master mode. The clock generator is disabled if the interface operates in the Slave mode. When the SHI operates in the Slave mode, the clock is external and is input to the SHI (HMST = 0). Figure 5-2 illustrates the internal clock path connections.
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5-6 HA4 HA5 HA6 HA3 20 22 21 20 21 HBER 22 HBUSY HROE 20 DSP56012 User’s Manual HRFF 19 19 19 18 18 HA1 18 HRNE 17 17 17 16 16 16 HTDE 15 15 15 HTUE 14 14 14 11 11 11 HTIE 9 HIDLE HBIE HTX 9 9 10 10 10 FIFO (10 Words Deep) HRX HRIE1 HRIE0 12 HFM0 HFM1 13 12 12 13 13 HRQE1 6 6 5 HDM2 5 5 4 4 4 HDM1 HMST HFIFO 6 HDM3 HRQE0 7 HDM4 HDM5 8 7 7 8 8 Figure 5-4 SHI Programming Model—DSP Side Reserved bit, read as 0, should be writt
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Serial Host Interface Serial Host Interface Programming Model The interrupt vector table for the Serial Host Interface is shown in Table 5-1 and the exceptions generated by the SHI are prioritized as shown in Table 5-2.
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Serial Host Interface Serial Host Interface Programming Model 5.4.1 SHI Input/Output Shift Register (IOSR)—Host Side The variable length Input/Output Shift Register (IOSR) can be viewed as a serial-to-parallel and parallel-to-serial buffer in the SHI. The IOSR is involved with every data transfer in both directions (read and write). In compliance with the I2C and SPI bus protocols, data is shifted in and out MSB first.
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Serial Host Interface Serial Host Interface Programming Model 5.4.3 SHI Host Receive Data FIFO (HRX)—DSP Side The 24-bit Host Receive data FIFO (HRX) is a 10-word deep, First-In-First-Out (FIFO) register used for Host-to-DSP data transfers. The serial data is received via the shift register and then loaded into the HRX.
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Serial Host Interface Serial Host Interface Programming Model Note: The maximum-allowed internally generated bit clock frequency is fosc/4 for the SPI mode and fosc/6 for the I2C mode (the maximum-allowed externally generated bit clock frequency is fosc/3 for the SPI mode and fosc/5 for the I2C mode). The programmer should not use the combination HRS = 1 and HDM[5:0] = 000000, since it may cause synchronization problems and improper operation (it is therefore considered an illegal combination).
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Serial Host Interface Serial Host Interface Programming Model used in conjunction with the CPOL bit to select the desired clock-to-data relationship. The CPHA bit, in general, selects the clock edge that captures data and allows it to change states. It has its greatest impact on the first bit transmitted (MSB) in that it does or does not allow a clock transition before the data capture edge.
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Serial Host Interface Serial Host Interface Programming Model prescaler is operational. HRS is ignored when the SHI operates in the Slave mode. The HRS bit is cleared during hardware reset and software reset. 5.4.5.3 HCKR Divider Modulus Select (HDM[5:0])—Bits 8–3 The HDM[5:0] bits specify the divide ratio of the clock generator divider. A divide ratio between 1 and 64 (HDM[5:0] = 0 to $3F) may be selected. When the SHI operates in the Slave mode, the HDM[5:0] bits are ignored.
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Serial Host Interface Serial Host Interface Programming Model in noisy environments; the bit-rate transfer is strictly limited. The wide-spiketolerance filter mode is highly recommended for use in I2C bus systems as it fully conforms to the I2C bus specification and improves noise immunity. Note: HFM[1:0] are cleared during hardware reset and software reset.
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Serial Host Interface Serial Host Interface Programming Model reset be generated (HEN cleared) before changing HI2C. HI2C is cleared during hardware reset and software reset. 5.4.6.3 HCSR Serial Host Interface Mode (HM[1:0])—Bits 3–2 The read/write control bits HM[1:0] select the size of the data words to be transferred, as shown in Table 5-4 on page 5-14. HM[1:0] should be modified only when the SHI is idle (HBUSY = 0). HM[1:0] are cleared during hardware reset and software reset.
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Serial Host Interface Serial Host Interface Programming Model recommended that an SHI individual reset be generated (HEN cleared) before changing HMST. HMST is cleared during hardware reset and software reset. 5.4.6.7 HCSR Host-Request Enable (HRQE[1:0])—Bits 8–7 The read/write Host-Request Enable control bits (HRQE[1:0]) are used to enable the operation of the HREQ pin. When HRQE[1:0] are cleared, the HREQ pin is disabled and held in the high impedance state.
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Serial Host Interface Serial Host Interface Programming Model suspended before transmitting an ACK. While HIDLE is cleared the bus is busy, that is, the start event was sent but no Stop event was generated. Setting HIDLE will cause a stop event. Note: HIDLE is set while the SHI is not in the I2C Master mode. HIDLE is set during hardware reset, software reset, individual reset, and while the chip is in the Stop state. 5.4.6.
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Serial Host Interface Serial Host Interface Programming Model Table 5-6 HCSR Receive Interrupt Enable Bits HRIE[1:0] Interrupt Condition 00 Disabled Not applicable 01 Receive FIFO not empty Receive Overrun Error HRNE = 1 and HROE = 0 HROE = 1 10 Reserved Not applicable 11 Receive FIFO full Receive Overrun Error HRFF = 1 and HROE = 0 HROE = 1 Note: HRIE[1:0] are cleared by hardware and software reset.
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Serial Host Interface Serial Host Interface Programming Model CPHA = 0, HTDE is set after the end of the data word transmission. HTDE is cleared when HTX is written by the DSP. HTDE is set by hardware reset, software reset, SHI individual reset, and during the Stop state. 5.4.6.14 Host Receive FIFO Not Empty (HRNE)—Bit 17 The read-only status bit Host Receive FIFO Not Empty (HRNE) indicates that the Host Receive FIFO (HRX) contains at least one data word. HRNE is set when the FIFO is not empty.
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Serial Host Interface Characteristics Of The SPI Bus 5.4.6.18 HCSR Host Busy (HBUSY)—Bit 22 The read-only status bit Host Busy (HBUSY) indicates that the I2C bus is busy (when in the I2C mode) or that the SHI itself is busy (when in the SPI mode). When operating in the I2C mode, HBUSY is set after the SHI detects a Start event and remains set until a Stop event is detected. When operating in the Slave SPI mode, HBUSY is set while SS is asserted.
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Serial Host Interface Characteristics Of The I2C Bus 5.6 CHARACTERISTICS OF THE I2C BUS The I2C serial bus consists of two bi-directional lines, one for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. Note: Within the I2C bus specifications, a low-speed mode (2 kHz clock rate) and a high-speed mode (100 kHz clock rate) are defined. The SHI operates in the high-speed mode only. 5.6.
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Serial Host Interface Characteristics Of The I2C Bus • Data valid—The state of the data line represents valid data when, after a Start event, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the low period of the clock signal. There is one clock pulse per bit of data. SDA SCL S P Start Event Stop Event AA0423 Figure 5-8 I2C Start and Stop Events Each 8-bit word is followed by one acknowledge bit.
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Serial Host Interface Characteristics Of The I2C Bus generation of the stop event. Handshaking may also be accomplished by use of the clock synchronizing mechanism. Slave devices can hold the SCL line low, after receiving and acknowledging a byte, to force the master into a wait state until the slave device is ready for the next byte transfer. The SHI supports this feature when operating as a master device and will wait until the slave device releases the SCL line before proceeding with the data transfer.
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Serial Host Interface SHI Programming Considerations Note: The first data byte in a write-bus cycle can be used as a user-predefined control byte (e.g., to determine the location to which the forthcoming data bytes should be transferred). 5.7 SHI PROGRAMMING CONSIDERATIONS The SHI implements both SPI and I2C bus protocols and can be programmed to operate as a slave device or a single-master device.
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Serial Host Interface SHI Programming Considerations occurred, the contents of HTX are not transferred to IOSR, so the data that is shifted out when receiving is the same as the data present in the IOSR at the time. The HRX FIFO contains valid receive data, which may be read by the DSP, if the HRNE status bit is set.
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Serial Host Interface SHI Programming Considerations HBIE bit is also set, the SHI issues a request to the DSP interrupt controller to service the SHI Bus Error interrupt. In the SPI Master mode the DSP must write to HTX to receive, transmit, or perform a full-duplex data transfer. Actually, the interface performs simultaneous data receive and transmit.
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Serial Host Interface SHI Programming Considerations When the SHI is enabled and configured in the I2C Slave mode, the SHI controller inspects the SDA and SCL lines to detect a start event. Upon detection of the start event, the SHI receives the slave device address byte and enables the slave device address recognition unit.
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Serial Host Interface SHI Programming Considerations 5.7.3.2 Transmit Data In I2C Slave Mode A transmit session is initiated when the personal slave device address has been correctly identified and the R/W bit of the received slave device address byte has been set. Following a transmit initiation, the IOSR is loaded from HTX (assuming the latter was not empty) and its contents are shifted out, MSB first, on the SDA line.
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Serial Host Interface SHI Programming Considerations • SCK/SCL is the SCL serial clock output. • MISO/SDA is the SDA open drain serial data line. • MOSI/HA0 is the HA0 slave device address input. • SS/HA2 is the HA2 slave device address input. • HREQ is the Host Request input. In the I2C Master mode, a data transfer session is always initiated by the DSP by writing to the HTX register when HIDLE is set.
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Serial Host Interface SHI Programming Considerations DSPs, one operating as an I2C master device and the other as an I2C slave device, enables full hardware handshaking. 5.7.4.1 Receive Data in I2C Master Mode A receive session is initiated if the R/W direction bit of the transmitted slave device address byte is set. Following a receive initiation, data in SDA line is shifted into IOSR MSB first.
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Serial Host Interface SHI Programming Considerations complete number of words. Remember that for this purpose, the slave device address byte does not count as part of the data. In a transmit session, only the transmit path is enabled and the IOSR-to-HRX FIFO transfers are inhibited. When the HTX transfers its valid data word to the IOSR, the HTDE status bit is set and the DSP may write a new data word to HTX.
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SECTION 6 SERIAL AUDIO INTERFACE MOTOROLA DSP56012 User’s Manual 6-1
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Serial Audio Interface 6.1 6.2 6.3 6.4 6-2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 SERIAL AUDIO INTERFACE INTERNAL ARCHITECTURE 6-4 SERIAL AUDIO INTERFACE PROGRAMMING MODEL . . . 6-8 PROGRAMMING CONSIDERATIONS . . . . . . . . . . . . . . . .
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Serial Audio Interface Introduction 6.1 INTRODUCTION The DSP communicates with data sources and sinks through its Serial Audio Interface (SAI). The SAI is a synchronous serial interface dedicated for audio data transfers. It provides a full duplex serial port for serial connection with a variety of audio devices, such as Analog-to-Digital (A/D) converters, Digital-to-Analog (D/A) converters, CD devices, etc. The SAI implements a wide range of serial data formats currently in use by audio manufacturers.
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Serial Audio Interface Serial Audio Interface Internal Architecture • User programmable to support a wide variety of serial audio formats • Three receive interrupt vectors: Receive Left Channel, Receive Right Channel, and Receive with Exception • Three transmit interrupt vectors: Transmit Left Channel, Transmit Right Channel, and Transmit with Exception 6.
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Serial Audio Interface Serial Audio Interface Internal Architecture 6.2.2 Receive Section Overview The receive section contains two receivers and consists of a 16-bit control/status register, two 24-bit shift registers, and two 24-bit data registers. These two receivers share the same control mechanism, therefore the bit clock, word select line, and all control signals generated in the receive section simultaneously affect both receivers.
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Serial Audio Interface Serial Audio Interface Internal Architecture 6.2.3 SAI Transmit Section Overview The transmit section contains three transmitters and consists of a 16-bit control/status register, three 24-bit shift registers, and three 24-bit data registers. These three transmitters are controlled by the same control mechanism, therefore, the bit clock, word select line, and all control signals generated in the transmit section equally affect all three transmitters.
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Serial Audio Interface Serial Audio Interface Internal Architecture Global Data Bus (GDB) 23 15 0 0 TX0 Data Register Transmit Control/Status (TCS) 0 23 SDO0 TX0 Shift Register 0 23 Status TCLOCK TX1 Data Register Transmit Controller 0 23 Control SDO1 TX1 Shift Register 23 0 TX2 Data Register 23 0 SDO2 TX2 Shift Register AA0429k Figure 6-3 SAI Transmit Section Block Diagram .
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Serial Audio Interface Serial Audio Interface Programming Model 6.3 SERIAL AUDIO INTERFACE PROGRAMMING MODEL The Serial Audio Interface registers that are available to the programmer are shown in Figure 6-4. The registers are described in the following paragraphs.
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Serial Audio Interface Serial Audio Interface Programming Model Table 6-1 SAI Interrupt Vector Locations Interrupt TXIL = 0 TXIL = 1 RXIL = 0 RXIL = 1 Left Channel Transmit P: $0010 P: $0040 — — Right Channel Transmit P: $0012 P: $0042 — — Transmit Exception P: $0014 P: $0044 — — Left Channel Receive — — P: $0016 P: $0046 Right Channel Receive — — P: $0018 P: $0048 Receive Exception — — P: $001A P: $004A Table 6-2 SAI Internal Interrupt Priorities Priority Highest Interr
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Serial Audio Interface Serial Audio Interface Programming Model 6.3.1.1 Prescale Modulus select (PM[7:0])—Bits 7–0 The PM[7:0] bits specify the divide ratio of the prescale divider in the SAI baud-rate generator. A divide ratio between 1 and 256 (PM[7:0] = $00 to $FF) may be selected. The PM[7:0] bits are cleared during hardware reset and software reset.
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Serial Audio Interface Serial Audio Interface Programming Model which is equivalent to the individual reset state. The R0EN bit is cleared during hardware reset and software reset. 6.3.2.2 RCS Receiver 1 Enable (R1EN)—Bit 1 The read/write Receiver 1 Enable (R1EN) control bit enables the operation of SAI Receiver 1. When R1EN is set, Receiver 1 is enabled. When R1EN is cleared, Receiver 1 is disabled.
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Serial Audio Interface Serial Audio Interface Programming Model discarded according to the Receiver Data Word Truncation (RDWT) control bit (see below). RWL[1:0] are also used to generate the word select indication when the receiver section is configured as master (RMST = 1). The RWL[1:0] bits are cleared during hardware reset and software reset. 6.3.2.
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Serial Audio Interface Serial Audio Interface Programming Model 6.3.2.8 RCS Receiver Clock Polarity (RCKP)—Bit 8 The read/write Receiver Clock Polarity (RCKP) control bit selects the polarity of the receiver serial clock. When RCKP is cleared, the receiver clock polarity is negative. When RCKP is set, the receiver clock polarity is positive.
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Serial Audio Interface Serial Audio Interface Programming Model RREL = 0 Left WSR Right MSB LSB MSB LSB MSB SDI RREL = 1 WSR Left Right LSB MSB LSB MSB LSB MSB SDI AA0434 Figure 6-8 Receiver Relative Timing (RREL) Programming 6.3.2.10 RCS Receiver Data Word Truncation (RDWT)—Bit 10 The read/write Receiver Data Word Truncation (RDWT) control bit selects which 24-bit portion of a received 32-bit word will be transferred from the shift register to the data register.
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Serial Audio Interface Serial Audio Interface Programming Model 6.3.2.11 RCS Receiver Interrupt Enable (RXIE)—Bit 11 When the read/write Receiver Interrupt Enable (RXIE) control bit is set, receiver interrupts for both left and right data words are enabled, and the DSP is interrupted if either the RLDF or RRDF status bit is set. When RXIE is cleared, receiver interrupts are disabled, however, RLDF and RRDF bits still indicate the receive data register full conditions and can be polled for status.
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Serial Audio Interface Serial Audio Interface Programming Model 6.3.2.13 RCS Receiver Left Data Full (RLDF)—Bit 14 Receiver Left Data Full (RLDF) is a read-only status bit that, together with RRDF (see below), indicates the status of the enabled receive data registers. RLDF is set when the left data word (as indicated by WSR pin and the RLRS bit in the RCS) is transferred to the receive data registers after it was shifted in via the shift register of the enabled receiver.
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Serial Audio Interface Serial Audio Interface Programming Model 6.3.3 SAI Receive Data Registers (RX0 and RX1) The Receive data registers (RX0 and RX1) are 24-bit read-only registers that accept data from the receive shift registers when all bits of the incoming data words have been received. The receive data registers alternately contain left-channel and right-channel data.
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Serial Audio Interface Serial Audio Interface Programming Model 6.3.4.3 TCS Transmitter 2 Enable (T2EN)—Bit 2 The read/write control bit T2EN enables the operation of the SAI Transmitter 2. When T2EN is set, Transmitter 2 is enabled. When T2EN is cleared, Transmitter 2 is disabled and the SDO2 line is set to high level. If T0EN, T1EN, and T2EN are cleared, the SAI transmitter section is disabled and enters the individual reset state. The T2EN bit is cleared during hardware reset and software reset. 6.3.4.
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Serial Audio Interface Serial Audio Interface Programming Model 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCKT MSB LSB LSB MSB SDO TDIR = 0 TDIR = 1 SDO AA0436k Figure 6-10 Transmitter Data Shift Direction (TDIR) Programming 6.3.4.7 TCS Transmitter Left Right Selection (TLRS)—Bit 7 The read/write Transmitter Left Right Selection (TLRS) control bit switches the polarity of the Word Select Transmit (WST) signal that identifies the left or right word in the output bit stream.
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Serial Audio Interface Serial Audio Interface Programming Model TCKP = 0 TCKP = 1 SCKT SCKT SDO SDO WST WST AA0438k Figure 6-12 Transmitter Clock Polarity (TCKP) Programming 6.3.4.9 TCS Transmitter Relative Timing (TREL)—Bit 9 The read/write Transmitter Relative timing (TREL) control bit selects the relative timing of the WST signal in reference to the serial data output lines (SDOx).
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Serial Audio Interface Serial Audio Interface Programming Model register, the last bit is transmitted eight times. When TDWE is set, the first bit is transmitted 8 times and then the 24-bit data word from the transmit data register is transmitted. The TDWE bit is ignored if TWL[1:0] are set for a word length other than 32 bits (see Figure 6-14). The TDWE bit is cleared during hardware reset and software reset.
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Serial Audio Interface Serial Audio Interface Programming Model To clear TLDE or TRDE during left or right channel interrupt service, the transmit data registers of the enabled transmitters must be written. Clearing TLDE or TRDE will clear the respective interrupt request. If the “Transmit interrupt with exception” indication is signaled (TLDE = TRDE = 1), then TLDE and TRDE are both cleared by reading the TCS register, followed by writing to the transmit data register of the enabled transmitters.
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Serial Audio Interface Serial Audio Interface Programming Model condition. TLDE is cleared by hardware reset and software reset, when the DSP is in the Stop state, and when all transmitters are disabled (T2EN, T1EN, and T0EN cleared). 6.3.4.15 TCS Transmitter Right Data Empty (TRDE)—Bit 15 Transmitter Right Data Empty (TRDE) is a read-only status bit that, in conjunction with TLDE, indicates the status of the enabled transmit data registers.
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Serial Audio Interface Programming Considerations 6.4 PROGRAMMING CONSIDERATIONS This section discusses some important considerations for programming the SAI. 6.4.1 SAI Operation During Stop The SAI operation cannot continue when the DSP is in the Stop state, since no DSP clocks are active. Incoming serial data will be ignored. While the DSP is in the Stop state, the SAI sections will remain in the individual reset state and the status bits in the RCS and TCS registers will be cleared.
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Serial Audio Interface Programming Considerations When operating in the Master mode, the following initialization procedure is recommended: 1. Write the left data words to the transmit data registers. 2. Enable the operation of the SAI receivers while ensuring that RXIE = 1 (RCS register). 3. Enable the operation of the SAI transmitters while ensuring that TXIE = 0 (TCS register). Enabling the transmitters will transfer the left data words from the transmit data registers to the shift registers. 4.
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Serial Audio Interface Programming Considerations As a result, when the WSR/WST transition appears earlier than expected, the transition is ignored and the next pair of data words (right and left) is lost. Likewise, when the WSR/WST transition appears later than expected, in the time period between the completion of the previous word and the appearance of the late WSR/WST transition, the data bits being received are ignored and no data is transmitted.
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SECTION 7 GPIO MOTOROLA DSP56012 User’s Manual 7-1
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GPIO 7.1 7.2 7.3 7-2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 GPIO PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . 7-3 GPIO REGISTER (GPIOR) . . . . . . . . . . . . . . . . . . . . . . . . . .
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GPIO Introduction 7.1 INTRODUCTION The General Purpose Input/Output (GPIO) pins are used for control and handshake functions between the DSP and external circuitry. The GPIO port has eight I/O pins (GPIO0–GPIO7) that are controlled through a memory-mapped register. Each GPIO pin may be individually programmed as an output or as an input. 7.2 GPIO PROGRAMMING MODEL The GPIO pins are controlled through the GPIO control/data Register (GPIOR), which is illustrated in Figure 7-1.
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GPIO GPIO Register (GPIOR) 7.3.1 GPIOR Data Bits (GD[7:0])—Bits 7–0 The read/write GPIO Data bits (GD[7:0]) are used to read from or write to the corresponding GPIO[7:0] pins. If the GPIOx pin is defined as an input, the GDx bit will reflect the logic value present on the GPIOx pin. If the GPIOx pin is defined as an output, the GPIOx pin will reflect the value written to the GDx bit. The GD[7:0] bits are cleared during hardware reset and software reset. 7.3.
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GPIO GPIO Register (GPIOR) • When the GCx bit is cleared and the GDDx bit is cleared (the pin is defined as an input), the corresponding GPIOx pin input buffer is disconnected from the pin and does not require an external pull-up (see Table 7-1 and Figure 7-2). • When the GCx bit is set and the GDDx bit is cleared (the pin is defined as input), the corresponding GPIOx pin input buffer is connected to the pin (see Table 7-1 and Figure 7-2).
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GPIO GPIO Register (GPIOR) 7-6 DSP56012 User’s Manual MOTOROLA
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SECTION 8 DIGITAL AUDIO TRANSMITTER MOTOROLA DSP56012 User’s Manual 8-1
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Digital Audio Transmitter 8.1 8.2 8.3 8.4 8.5 8.6 8-2 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 DAX SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 DAX FUNCTIONAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . 8-5 DAX PROGRAMMING MODEL. . . . . . . . . . . . . . . . . . . . . . . 8-6 DAX INTERNAL ARCHITECTURE . . . . . . . . . . . . . . . . . . . . 8-6 DAX PROGRAMMING CONSIDERATIONS . . . . . . . . . . . .
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Digital Audio Transmitter Overview 8.1 OVERVIEW The Digital Audio Transmitter (DAX) is a serial audio interface module that outputs digital audio data in the AES/EBU, CP-340 and IEC958 formats. Some of the key features of the DAX are listed below. • Operates on a frame basis—The DAX can handle one frame (consisting of two sub-frames) of audio and non-audio data at a time.
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Digital Audio Transmitter DAX Signals Global Data Bus 23 0 23 0 XSTR 23 XCTR 0 23 XADRA Upload 0 XADRB Upload MUX XADBUF Upload MUX XNADBUF DAX State Machine Control Signals 23 0 XADSR PRTYG DAX Clocks Biphase Encoder MUX C-U-V MUX 26 Preamble Generator ADO ACI DAX Clock MUX DSP Core Clock AA0606k Figure 8-1 Digital Audio Transmitter (DAX) Block Diagram 8.
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Digital Audio Transmitter DAX Functional Overview 8.
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Digital Audio Transmitter DAX Programming Model The second sub-frame transmission (Channel B) starts with the preamble generator generating the Channel B preamble (Y-preamble). At the same time, Channel B audio and non-audio data is transferred to the XADSR shift-register from the XADBUF and XNADBUF registers.
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Digital Audio Transmitter DAX Internal Architecture 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 XCB XUB XVB XCA XUA XVA 23 22 21 20 19 18 17 16 15 14 13 12 11 10 4 3 2 1 XCS1 XCS0 XSTP XIEN XEN 9 8 7 6 5 4 3 2 1 XTIP XBLK XAUR 23 0 0 XADE XCTR X:$FFDE XSTR X:$FFDF 0 XADRA XADRB X:$FFDC Accessed Alternately Reserved bit AA0607k Figure 8-2 DAX Programming Mode 8.5.
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Digital Audio Transmitter DAX Internal Architecture 8.5.3 DAX Audio Data Shift Register (XADSR) The XADSR is a 27-bit shift register that shifts the 24-bit audio data and the 3-bit non-audio data for one sub-frame. The contents of XADRA are directly transferred to the XADSR at the beginning of the frame transmission (at the beginning of the Channel A sub-frame transmission).
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Digital Audio Transmitter DAX Internal Architecture 8.5.4.4 DAX Clock Input Select (XCS[1:0])—Bits 3–4 The XCS[1:0] bits select the source of the DAX clock and/or its frequency. Table 8-3 shows the configurations selected by these bits. These bits should be changed only when the DAX is disabled.
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Digital Audio Transmitter DAX Internal Architecture 8.5.4.10 DAX Channel B User Data (XUB)—Bit 14 The value of the XUB bit is transmitted as the thirtieth bit (Bit 29) of the Channel B sub-frame in the next frame. Note: This bit is not affected by any of the DAX reset states. 8.5.4.11 DAX Channel B Channel Status (XCB)—Bit 15 The value of the XCB bit is transmitted as the thirty-first bit (Bit 30) of the Channel B sub-frame in the next frame. Note: This bit is not affected by any of the DAX reset states.
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Digital Audio Transmitter DAX Internal Architecture Note: The XAUR bit is cleared by reading the XSTR register with XAUR set, followed by writing data to XADRA and XADRB. It is also cleared by software reset and hardware reset, and by the Stop state. 8.5.5.4 DAX Block Transfer Flag (XBLK)—Bit 3 The XBLK flag indicates that the frame being transmitted is the last frame in a block. This bit is set at the beginning of the transmission of the last frame (the 191st frame). This bit does not cause any interrupt.
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Digital Audio Transmitter DAX Internal Architecture 8.5.6 DAX Non-Audio Data Buffer (XNADBUF) The XNADBUF is a 3-bit register that temporarily holds Channel B non-audio data (XVB, XUB and XCB) for the current transmission while the Channel A data is being transmitted. This mechanism provides programmers more instruction cycles to store the next frame’s non-audio data to the XCB, XUB, XVB, XCA, XUA and XVA bits in the XCTR.
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Digital Audio Transmitter DAX Internal Architecture There is no programmable control for the preamble selection. The first sub-frame to be transmitted (immediately after the DAX is enabled) is the beginning of a block, and therefore it has a “Z” preamble. This is followed by the second sub-frame, which has an “Y” preamble. After that, “X” and “Y” preambles are transmitted alternately until the end of the block transfer (192 frames transmitted). See Figure 8-4 for an illustration of the preamble sequence.
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Digital Audio Transmitter DAX Programming Considerations Note: For proper operation of the DAX, the DSP core clock frequency must be at least five times higher than the DAX bit shift clock frequency (64 × Fs). 8.5.11 DAX State Machine The DAX state machine generates a set of sequencing signals used in the DAX. 8.6 8.6.1 DAX PROGRAMMING CONSIDERATIONS Initiating A Transmit Session To initiate the DAX operation, follow this procedure: 1. Write the audio data in the XADRA/XADRB registers 2.
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Digital Audio Transmitter DAX Programming Considerations 8.6.4 DAX Operation During Stop The DAX operation cannot continue when the DSP is in the Stop state since no DSP clocks are active. While the DSP is in the Stop state, the DAX will remain in the individual reset state and the status flags are initialized as described for resets. No DAX control bits are affected. It is recommended that the DAX be disabled, by clearing the XEN bit in the XCTR, before the DSP enters the Stop state.
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Digital Audio Transmitter DAX Programming Considerations 8-16 DSP56012 User’s Manual MOTOROLA
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APPENDIX A BOOTSTRAP ROM CONTENTS 00 11 00 00 0100101001011010 1 0 0 1010101010110110 0 1010101010010111 0 1 0100101001011010 1 0 0 0101001010010111 1 00 11 1010101010110110 0 11 1000101010100100 0 1010101010010111 0 1 0100010101011101 00 0101001010010111 11 1 1 0 11 0 1000101010100100 00 1 0100010101011101 1 0 MOTOROLA DSP56012 User’s Manual 1 A-1
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Bootstrap ROM Contents A.1 A.2 A.3 A-2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 BOOTSTRAPPING THE DSP . . . . . . . . . . . . . . . . . . . . . . . . A-3 BOOTSTRAP PROGRAM LISTING . . . . . . . . . . . . . . . . . . .
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Bootstrap ROM Contents A.1 INTRODUCTION This section presents the bootstrap programs (ROM code) contained in the DSP. A.2 BOOTSTRAPPING THE DSP The bootstrap ROM for the DSP occupies locations 0–31 ($0–$1F) of the DSP56012 memory map. The DSP can bootstrap from an external device attached to the Host Interface (HI), through the Serial Host Interface (SHI) using the SPI protocol, or through the SHI using the I2C protocol, depending on how the three mode pins (MODC, MODB, and MODA) are configured.
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Bootstrap ROM Contents A.3 BOOTSTRAP PROGRAM LISTING ; BOOTSTRAP CODE FOR DSP56012—(C) Copyright 1997 Motorola Inc. ; Revised August 28, 1997. ; ; bootstrap through HOST, SHI-SPI and SHI-I2C,according to op-modes MC:MB:MA.
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Bootstrap ROM Contents bcr equ $fffe ; BCR Register pbc hsr horx hf0 hrdf equ equ equ equ equ $ffec $ffe9 $ffeb 3 0 ; ; ; ; ; Port HOST HOST HOST HOST hrne hrx hcsr hi2c equ equ equ equ 17 $fff3 $fff1 1 ; ; ; ; SHI SHI SHI SHI ma mb mc equ equ equ 0 1 4 ; OMR Mode A ; OMR Mode B ; OMR Mode C org p:$0 ; bootstrap code starts at $0 move move jclr #$000A00,a0 #<0,r0 #ma,omr,exit ; Program ROM starting address($0A00) ; r0 points to internal Program RAM ; if MC:MB:MA = xx0 goto Program RO
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Bootstrap ROM Contents ; ; ; ; ; ; ; ; ; “shild” is the routine that loads from the Serial Host Interface. MC:MB:MA = 101—bootstrap from SHI (SPI) MC:MB:MA = 111—bootstrap from SHI (IIC) If MC:MB:MA = 1X1, the internal Program RAM is loaded with 256 words received through the Serial Host Interface (SHI). The SHI operates in the Slave mode with the 10-word FIFO enabled, and with the HREQ pin enabled for receive operation. The word size for transfer is 24 bits.
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APPENDIX B PROGRAMMING REFERENCE MOTOROLA DSP56012 User’s Manual B-1
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Programming Reference B.1 B.2 B.3 B.4 B.5 B.6 B-2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 PERIPHERAL ADDRESSES. . . . . . . . . . . . . . . . . . . . . . . . . B-3 INTERRUPT ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 INTERRUPT PRIORITIES. . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 INSTRUCTION SET SUMMARY. . . . . . . . . . . . . . . . . . . . . . B-3 PROGRAMMING SHEETS . . . . . . . . . . . . . . . . . . . . . . . . . .
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PERIPHERAL ADDRESSES B.1 Programming Reference INTRODUCTION This section has been compiled as a reference for programmers. It contains a memory map showing the addresses of all the DSP’s memory-mapped peripherals, an interrupt priority table, an instruction set summary, and programming sheets for all the programmable registers on the DSP.
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Programming Reference 23 16 15 87 0 X:$FFFF X:$FFFE X:$FFFD X:$FFFC X:$FFFB X:$FFFA X:$FFF9 X:$FFF8 X:$FFF7 X:$FFF6 X:$FFF5 X:$FFF4 X:$FFF3 X:$FFF2 X:$FFF1 X:$FFF0 X:$FFEF X:$FFEE X:$FFED X:$FFEC X:$FFEB X:$FFEA X:$FFE9 X:$FFE8 X:$FFE7 X:$FFE6 X:$FFE5 X:$FFE4 X:$FFE3 X:$FFE2 X:$FFE1 X:$FFE0 X:$FFDF X:$FFDE X:$FFDD X:$FFDC X:$FFDB X:$FFDA X:$FFD9 X:$FFD8 X:$FFD7 X:$FFD6 X:$FFD5 X:$FFD4 X:$FFD3 Interrupt Priority Register (IPR) Reserved PLL Control Register (PCTL) Reserved Reserved Reserved Reserved Res
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Programming Reference Table B-1 Interrupt Starting Addresses and Sources Interrupt Starting Address P:$0000 P:$0002 P:$0004 P:$0006 P:$0008 P:$000A P:$000C P:$000E P:$0010 P:$0012 P:$0014 P:$0016 P:$0018 P:$001A P:$001C P:$001E P:$0020 P:$0022 P:$0024 P:$0026 P:$0028 P:$002A P:$002C P:$002E P:$0030 P:$0032 P:$0034 P:$0036 P:$0038 P:$003A P:$003C P:$003E P: $0040 P: $0042 P: $0044 P: $0046 P: $0048 MOTOROLA IPL 3 3 3 3 0–2 0–2 0–2 0–2 0–2 0–2 0–2 0–2 3 0–2 0–2 0–2 0–2 0–2 0–2 0–2 0–2 0–2 3 0–2 0–2 0–2 0
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Programming Reference Table B-1 Interrupt Starting Addresses and Sources (Continued) Interrupt Starting Address P: $004A P: $004C : P: $004E P: $0050 P: $0052 P: $0054 P: $0056 P: $0058 : P: $007E IPL Interrupt Source 0–2 SAI Receiver Exception if RXIL = 1 Available for Host Command : Available for Host Command 0–2 DAX Transmit Underrun Error 0–2 DAX Block Transferred Available for Host Command 0–2 DAX Transmit Register Empty Available for Host Command : Available for Host Command Table B-2 Interrupt P
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Programming Reference Table B-2 Interrupt Priorities Within an IPL (Continued) Priority Interrupt Levels 0, 1, 2 (Maskable) Highest IRQA IRQB SAI Receiver Exception SAI Transmitter Exception SAI Left Channel Receiver SAI Left Channel Transmitter SAI Right Channel Receiver SAI Right Channel Transmitter SHI Bus Error SHI Receive Overrun Error SHI Transmit Underrun Error SHI Receive FIFO Full SHI Transmit Data SHI Receive FIFO Not Empty HI Command Interrupt HI Receive Data Interrupt HI Transmit Data Interr
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Programming Reference Table B-3 Instruction Set Summary (Sheet 1 of 7) Mnemonic ABS ADC ADD ADDL ADDR AND AND(I) ASL ASR BCHG Syntax Parallel Moves Instruction Osc.
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Programming Reference Table B-3 Instruction Set Summary (Sheet 2 of 7) Mnemonic BTST CLR CMP CMPM DEBUG DEBUGcc DEC DIV DO ENDDO EOR ILLEGAL INC Jcc JCLR Syntax #n,X: #n,X: #n,X: #n,Y: #n,Y: #n,Y: #n,D D S1,S2 S1,S2 Parallel Moves (parallel move) (parallel move) (parallel move) D S,D X:,expr X:,expr Y:,expr Y:,expr #xxx,expr S,expr S,D (parallel move) Instruction Osc.
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Programming Reference Table B-3 Instruction Set Summary (Sheet 3 of 7) Mnemonic Syntax Parallel Moves Instruction Osc.
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Programming Reference Table B-3 Instruction Set Summary (Sheet 4 of 7) Mnemonic Syntax MAC (+)S2,S1,D (+)S1,S2,D (+)S,#n,D MACR (+)S2,S1,D (+)S1,S2,D (+)S,#n,D MOVE S,D No parallel data move Immediate short data move Register to register data move Address register update X memory data move Register and X memory data move Y memory data move Parallel Moves (parallel move) (parallel move) (no parallel move) (parallel move) (parallel move) (no parallel move) Instruction Osc.
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Programming Reference Table B-3 Instruction Set Summary (Sheet 5 of 7) Mnemonic Syntax Register and Y memory data move Long memory data move XY memory data move MOVE(C) Parallel Moves (.....)S1,D1 (.....)S1,D1 (.....)S1,D1 (.....)Y0,A (.....)Y0,B (.....)L:,D (.....)L:,D (.....)S,L: (.....)S,L: (.....)X:,D1 (.....)X:,D1 (.....)S1,X: (.....)S1,X: Instruction Osc.
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Programming Reference Table B-3 Instruction Set Summary (Sheet 6 of 7) Mnemonic MPY MPYR NEG NOP NORM NOT OR ORI REP Syntax X:,Y: X:,P: S,X: #xxxxxx,X: X:,X: Y:,X: P:,X: Y:,D Y:,X: Y:,Y: Y:,P: S,Y: #xxxxxx,Y: X:,Y: Y:,Y: P:,Y: (+)S2,S1,D (+)S1,S2,D (+)S,#n,D (+)S2,S1,D (+)S1,S2,D (+)S,#n,D D Rn,D D S,D #xx,D X: X: Y: Parallel Moves (parallel move) (parallel move) (no parallel move)
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Programming Reference Table B-3 Instruction Set Summary (Sheet 7 of 7) Mnemonic Syntax Parallel Moves Instruction Osc.
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Programming Reference Date: Application: Programmer: Sheet 1 of 4 CENTRAL PROCESSOR SR Carry Overflow Zero Negative Unnormalized Extension Limit FFT Scaling Interrupt Mask Scaling Mode Reserved Trace Mode Double Precision Multiply Mode Loop Flag 15 14 13 12 11 10 9 Status Register (SR) Read/Write Reset = $0300 LF DM T *0 S1 S0 I1 8 7 6 5 4 3 2 1 0 I0 S L E U N Z V C Mode Register (MR) * = Reserved, write as 0 Condition Code Register (CCR) Status Register (SR) Note: The opera
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B-16 * DAX IPL Enabled No Yes Yes Yes HI IPL HPL0 0 1 0 1 DSP56012 User’s Manual ILA2 0 1 ILA2 0 1 = Reserved, write as 0 0 *0 *0 *0 *0 *0 *0 0 IBL1 0 0 1 1 SAI IPL 8 7 6 IPL — 0 1 2 IBL0 0 1 0 1 *0 *0 *0 *0 9 Interrupt Priority Register (IPR) DTL1 DTL0 HPL1 HPL0 SHL1 SHL0 SAL1 SAL0 IAL0 0 1 0 1 IRQB Mode IAL1 0 0 1 1 IRQA Mode SAL1 SAL0 Enabled 0 0 No 0 1 Yes 1 0 Yes 1 1 Yes Trigger Level Neg. Edge Trigger Level Neg.
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MOTOROLA DSP56012 User’s Manual 1 0 0 0 Operating Mode Register (OMR) 0 *0 2 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 3 4 MC PEB PEA MB 5 6 SD 8 7 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Stop Delay 0 = 128 K T Stabilization 1 = 16 T Stabilization Normal operation, bootstrap disabled Bootstrap from HI Wake up in Program ROM address $0B00 Reserved Reserved Bootstrap from SHI (SPI) Reserved Bootstrap from SHI (I2C) Operating Mode 0 MA Application: * = Bits 5 and 7 through 2
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B-18 DSP56012 User’s Manual * = Reserved, write as 0 *0 *0 CSRC *0 *0 PEN PSTP *0 DF2 DF1 DF0 MF11 MF10 MF9 8 MF8 PLL Control Register (PCTL) DF3 9 MF7 7 MF6 6 MF5 5 MF4 4 MF3 3 MF2 2 Division Factor Bits DF0–DF11 DF11–DF0 Division Factor MF $0 20 $1 21 $2 22 • • • • • • $E 214 $F 215 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PLL Enable Bit (PEN) 0 = Disable PLL 1 = Enable PLL 1 MF1 0 MF0 Application: PLL Control Register (PCTL) X:$FFFD Read/Write Reset = $000002(PINIT = GND)
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Programming Reference Date: Application: Programmer: Sheet 1 of 5 HI Port B PBC1 PBC0 Function 0 0 General Purpose I/O (Reset Condition) 0 1 Host Interface 1 0 Host Interface (with HACK Pin as GPIO) 1 1 Reserved 23 • • • 15 14 13 12 Port B * * * * * Control Register 0 0 0 0 0 (PBC) X:$FFEC Read/Write $0 Reset = $000000 * = Reserved, write as 0 11 10 9 8 7 6 5 4 3 2 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 * 0 2 $0 1 0 PBC1 PBC0 $0 Port B Control Register (PBC) DSP Side Host Re
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Programming Reference Date: Application: Programmer: Sheet 2 of 5 DSP Side HI Host Receive Data Full (HRDF) 0 = wait/1 = read Host Transmit Data Empty (HTDE) 0 = wait/1 = write Host Command Pending (HCP) 0 = wait/1 = ready Host Flags (HFO, HF1) read only DMA Status (DMA) read only 0 = disabled/1 = enabled Host Status Register (HSR) X:$FFE9 Read Only Reset = $000002 23 • • • 7 DMA * 0 6 5 4 3 * 0 * 0 HF1 HF0 2 1 HCP HTDE 0 HRDF * = Reserved, write as 0 Host Status Register (HSR) Host
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Programming Reference Date: Application: Programmer: Sheet 3 of 5 HI Processor Side Receive Request Enable (RREQ) DMA Off: 0 = interrupts disabled/1 = interrupts enabled DMA On: 0 = Host → DSP/1 = DSP → Host Transmit Request Enable (TREQ) DMA Off: 0 = interrupts disabled/1 = interrupts enabled DMA On: 0 = DSP → Host/1 = Host → DSP Host Flags (HF0, HF1) Write Only Host Mode Control (HM0, HM1) 00 = DMA off/01 = 24 Bit DMA 10 = 16 Bit DMA/11 = 8 Bit DMA Initialize (INIT) Write Only 0 = no action/1 = initi
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Programming Reference Date: Application: Programmer: Sheet 4 of 5 HI Processor Side Receive Data Register Full (RXDF) 0 = wait/1 = read Transmit Data Register Empty (TXDE) 0 = wait/1 = write Transmitter Ready (TRDY) 0 = data in HI/1 = data not in HOST8 Host Flags (HF3, HF2) Read Only DMA Status (DMA) 0 = DMA disabled/1 = DMA enabled Host Request (HOREQ) 0 = HOREQ deasserted/1 = HOREQ asserted 7 6 HOREQ DMA Interrupt Status Register (ISR) $2 Read/Write Reset = $06 5 4 * 0 HF3 3 2 1 0 HF2 TRD
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MOTOROLA DSP56012 User’s Manual $6 $7 0 7 $5 Transmit High Byte Transmit Byte Registers Transmit Middle Byte 7 $5 Receive High Byte Host Transmit Data (Usually Loaded by Program) Transmit Low Byte 0 7 0 0 0 7 0 7 0 0 0 0 0 $4 0 0 Not Used $4 0 Not Used 0 0 0 0 0 0 0 0 Application: 7 0 Receive Byte Registers $6 $7 7 Receive Middle Byte 0 Host Receive Data (Usually Read by Program) Processor Side Receive Low Byte Transmit Byte Registers $7, $6, $5, $4 Write
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B-24 HA6 HA5 HA4 HA3 *0 DSP56012 User’s Manual 0 6 5 4 3 2 1 0 0 Result Prescaler operational Prescaler bypassed *0 *0 *0 9 0 7 6 5 4 3 2 1 0 HDM5 HDM4 HDM3 HDM2 HDM1 HDM0 HRS CPOL CPHA 8 HCKR Divider Modulus Select HRS 0 1 * = Reserved, write asSHI0 Clock Control Register (HCKR) 0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 HFM1 HFM0 0 CPOL CPHA Result 0 0 SCK active low, strobe on rising edge 0 1 SCK active low, strobe on falling edge 1 0 SCK active high, strobe on falling edge 1 1 SC
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MOTOROLA 7 8 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 Application: DSP56012 User’s Manual SHI Host Receive Data Register (HRX) SHI Host Receive 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Data Register (HRX) X:$FFF3 Read Only Reset = $xxxxxx Host Receive Data Register Contents SHI Host Transmit Data Register (HTX) 8 Host Transmit Data Register Contents SHI Host Transmit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Data Register (HTX) X:$FFF3 Write Only Reset = $xxxxxx S.H.I.
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B-26 I2C Stop event SHI detects Start DSP56012 User’s Manual MOTOROLA * = Reserved, write as 0 *0 HBUSY HBER HROE HRFF *0 HRNE 8 7 6 5 *0 4 HM1 3 HI2C 0 1 1 HM0 HI2C 2 Result SPI mode I2C mode HEN 0 HEN Description 0 SHI disabled 1 SHI enabled Description 8 bit data 16 bit data 24 bit data Reserved HMST Result 0 Slave mode 1 Master mode SHI Host Control/Status Register (HCSR) *0 9 HM0 0 1 0 1 HFIFO Description 0 1 level FIFO 1 10 level HM1 0 0 1 1 HTDE HTUE HRIE1 HRIE0 HTIE HB
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Programming Reference Date: Application: Programmer: Sheet 1 of 4 S.A.I.
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Programming Reference Date: Application: Programmer: Sheet 2 of 4 TLRS 0 S.A.I.
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MOTOROLA 5 4 3 2 PM4 PM3 PM2 1 DSP56012 User’s Manual SAI Receive Data Register 1 (RX1) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Receive Data Register 1 Contents 8 Receive Data Register 0 Contents 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 Application: SAI Receive Data Register 1 (RX1) X:$FFE3 Read Only Reset = $xxxxxx 0 PM1 PM0 Baud Rate Control Register (BRC) * = Bits 9 through 15 are reserved.
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B-30 DSP56012 User’s Manual 8 SAI Transmit Data Register 2 (TX2) 8 7 7 7 6 6 6 5 5 5 4 4 4 3 3 3 2 2 2 1 1 1 0 0 0 Application: SAI Transmit Data 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Register 2 (TX2) X:$FFE7 Write Only Reset = $xxxxxx Transmit Data Register 2 Contents SAI Transmit Data Register 1 (TX1) SAI Transmit Data 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Register 1 (TX1) X:$FFE6 Write Only Reset = $xxxxxx Transmit Data Register 1 Contents SAI Transmit Data R
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MOTOROLA GPIO Control/Data Register (GPIOR) X:$FFF7 Reset = $000000 GPIO GDDx 0 1 0 1 GPIO Pin Definition Disconnected Standard output Input Open-drain output GC7 GC6 GC5 GC4 GC3 GC2 9 8 7 6 GD6 4 3 2 GD5 GD4 GD3 GD2 5 GPIO Data Bits 1 0 GD1 GD0 Application: DSP56012 User’s Manual GPIO Control/Data Register (GPIOR) GC1 GC0 GDD7 GDD6 GDD4 GDD4 GDD3 GDD2 GDD1 GDD0 GD7 23 22 21 20 19 18 17 16 15 14 13 12 11 10 GCx 0 0 1 1 Programming Reference Date: Programmer: Sheet 1 of 1 B-31
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B-32 XCS0 0 1 0 1 DSP56012 User’s Manual 7 6 5 8 * = Reserved; write as 0 2 7 6 5 3 2 XTIP XBLK XAUR 4 XAUR DAX Underrun error 0 No error 1 Underrun error *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 3 1 0 XCS1 XCS0 XSTP XIEN XEN 4 XEN DAX Enable 0 DAX disabled 1 DAX enabled 0 XADE 1 *0 XADE DAX Audio Data Empty 0 Register(s) full 1 Register(s) empty *0 *0 *0 *0 *0 XBLK DAX Block transfer 0 not last frame 1 191st frame transm
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Index A Address Buses 1-12 Address Generation Unit 1-11 AES/EBU 8-3 B bootstrap loading using the HI 4-54 Bootstrap Program Listing A-4 bootstrap ROM 1-16 Bootstrap ROM — See Appendix A C CDP Format 1-19, 6-3 Clock 2-7 Command Vector Register (CVR) 4-29 CP-340 8-3 CPHA and CPOL (HCKR Clock Phase and Polarity Controls) 5-10 CVR register 4-29 bit 0–5—Host Vector bits (HV) 4-29 bit 6—reserved 4-30 bit 7—Host Command bit (HC) 4-30 D Data ALU 1-11 Data Buses 1-12 data transfer DMA 4-59 DSP to host 4-19, 4-56
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Circuit Diagram 7-5 Control/Data Register 7-3 GPIOR Control Bits 7-4 Data Bits 7-4 Data Direction Bits 7-4 Pin Definition 7-4 Programming Model 7-3 programming port B 4-8 Ground 2-6 PLL 2-6 H H0–H7 pins 4-35 HA1, HA3-HA6 (HSAR I2C Slave Address) 5-9 HACK pin 4-36 HBER (HCSR Bus Error) 5-18 HBIE (HCSR Bus Error Interrupt Enable) 5-16 HBUSY (HCSR Host Busy) 5-19 HC bit 4-30 HCKR (SHI Clock Control Register) 5-9 HCP bit 4-21 HCR register bit 5–7—reserved 4-16 HCSR Receive Interrupt Enable Bits 5-17 SHI Contro
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Host Mode Control bits (HM1–HM0) 4-26 host port usage considerations 2-10 host registers after reset as seen by host processor 4-33 Host Request bit (HOREQ) 4-32 Host Request pin (PB13/HOREQ) 4-35 Host Status Register (HSR) 4-16 host to DSP DMA procedure 4-62 host to DSP internal processing 4-61 Host Transmit Data Empty bit (HTDE) 4-16 Host Transmit Data register (HOTX) 4-19 HOTX register 4-19 HR/W 4-35 HRDF bit 4-21 HREQ Function In SHI Slave Modes 5-15 HRFF (HCSR Host Receive FIFO Full) 5-18 HRIE0-HRIE1 (
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Low Power Divider 1-12 HI 4-13, 4-21 Programming Reference — See Appendix B PSR (BRC Prescaler Range) 6-10 M R Manual Conventions 1-5 MEC Format 1-19, 6-3 Memories 1-13 Memory — See Section 3 Memory Maps 1-17 MF0-MF11 (PLL Multiplication Factor) 3-19 MODB/IRQB 2-8 mode control 2-8 Mode Select A/External Interrupt Request A 2-8 Mode Select B/External Interrupt Request B 2-8, 2-9 Multiplication Factor 3-19 R0EN (RCS Receiver 0 Enable) 6-10 R1EN (RCS Receiver 1 Enable) 6-11 RCKP (RCS Receiver Clock Polari
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Programming Model 6-8 RCS Receiver 0 Enable 6-10 Receiver 1 Enable 6-11 Receiver Clock Polarity 6-13 Receiver Data Shift Direction 6-12 Receiver Data Word Truncation 6-14 Receiver Interrupt Enable 6-15 Receiver Interrupt Location 6-15 Receiver Left Data Full 6-16 Receiver Left Right Selection 6-12 Receiver Master 6-11 Receiver Relative Timing 6-13 Receiver Right Data Full 6-16 Receiver Word Length Control 6-11 Receive Data Registers 6-17 Receive Section 6-5 Receive Section Block Diagram 6-5 Receiver Clock P
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HCSR Bus Error 5-18 Host Busy 5-19 Host Receive FIFO Full 5-18 Host Receive FIFO Not Empty 5-18 Host Receive Overrun Error 5-18 Host Transmit Data Empty 5-17 Host Transmit Underrun Error 5-17 Receive Interrupt Enable 5-16 Master Mode 5-24 Slave Mode 5-23 SPI Data-To-Clock Timing 5-10 SPI Data-To-Clock Timing Diagram 5-10 SPI Mode 5-3 T T0EN (TCS Transmitter 0 Enable) 6-17 T1EN (TCS Transmitter 1 Enable) 6-17 T2EN (TCS Transmitter 2 Enable) 6-18 TCKP (TCS Transmitter Clock Polarity) 6-19 TCS 6-22 TDIR (TCS