Stereo System User Manual

5-6 DSP56012 User’s Manual MOTOROLA
Serial Host Interface
Serial Host Interface Programming Model
Figure 5-4 SHI Programming Model—DSP Side
815 14 13 12 11 10 9
1623 22 21 20 19 18 17
023
SHI Receive Data FIFO (HRX) (read only, X: $FFF3)
HRX
SHI Transmit Data Register (HTX) (write only, X: $FFF3)
Reserved bit, read as 0, should be written with 0 for future compatibility.
HDM5
HFM1
07654321
HFM0 HDM2
HDM0HDM1 HRSHDM3HDM4 CPHACPOL
SHI Clock Control Register (HCKR) X: $FFF0
023
HTX
815 14 13 12 11 10 9
1623 22 21 20 19 18 17
HEN
07 654321
HM1
HI
2
C
HM0HRQE0 HMST
HRNEHBER HRFFHROE
HBUSY
HRQE1HIDLE
SHI Control/Status Register (HCSR)
HRIE0HRIE1HTUEHTDE HTIE
X: $FFF1
FIFO (10 Words Deep)
HBIE
HFIFO
815 14 13 12 11 10 9
1623 22 21 20 19 18 17
HA6
07654321
HA3
HA4HA5
SHI I
2
C Slave Address Register (HSAR)
X: $FFF2
HA1
AA0419k