MVME172LX VME Embedded Controller Installation and Use VME172LXA/IH4
Notice While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
Preface This document provides general board level hardware description, hardware preparation and installation instructions, as well as debugger general information and instructions for the MVME172LX VME Embedded Controller (which is available in the versions listed below).
Safety Summary Safety Depends On You The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design, manufacture, and intended use of the equipment. Motorola, Inc. assumes no liability for the customer’s failure to comply with these requirements.
All Motorola PWBs (printed wiring boards) are manufactured by UL-recognized manufacturers, with a flammability rating of 94V-0. ! WARNING This equipment generates, uses, and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used in a cabinet with adequate EMI protection. European Notice: Board products with the CE marking comply with the EMC Directive (89/336/EEC).
Contents CHAPTER 1 Hardware Preparation and Installation Introduction................................................................................................................1-1 Getting Started ...........................................................................................................1-1 Overview of Installation Procedure ....................................................................1-1 Equipment Required ........................................................................
Bringing up the Board ............................................................................................... 2-5 Autoboot ............................................................................................................. 2-8 ROMboot............................................................................................................ 2-9 Network Boot ................................................................................................... 2-10 Restarting the System .......
I/O Interfaces ....................................................................................................4-10 Serial Communications Interface ..............................................................4-11 IP Interfaces...............................................................................................4-11 Ethernet Interface ......................................................................................4-12 SCSI Interface........................................................
APPENDIX D Disk/Tape Controller Data Disk/Tape Controller Modules Supported ................................................................ D-1 Disk/Tape Controller Default Configurations .......................................................... D-2 IOT Command Parameters ....................................................................................... D-3 APPENDIX E Related Documentation MCG Documents ..............................................................................................
Table 5-2. IndustryPack Interconnect Signals............................................................5-3 Table 5-3. DB15 Ethernet Connector Pin Assignments.............................................5-4 Table 5-4. Serial Connector Pin Assignments ...........................................................5-4 Table 5-5. Mezzanine Connector J22 Pin Assignments.............................................5-5 Table 5-6. Mezzanine Connector J15 Pin Assignments.............................................
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1Hardware Preparation and Installation 1 Introduction This chapter provides unpacking instructions, hardware preparation guidelines, and installation instructions for the MVME172LX VME Embedded Controller. Getting Started This section supplies an overview of startup procedures applicable to the MVME172LX. Equipment requirements, directions for unpacking, and ESD precautions that you should take complete the section.
1 Hardware Preparation and Installation Table 1-1. Startup Overview (Continued) What you need to do... Refer to... Connect any other equipment you will be using. Connector Pin Assignments in Chapter 5. Power up the system. Applying Power on page 2-2. For more information on optional devices and equipment, refer to the documentation provided with the equipment. Troubleshooting; Solving Startup Problems on page B-1. Note that the firmware initializes and tests the board. Applying Power on page 2-2.
Getting Started Unpack the equipment from the shipping carton. Refer to the packing list and verify that all items are present. Save the packing material for storing and reshipping of equipment. ! Avoid touching areas of integrated circuitry; static discharge can damage circuits. Caution ESD Precautions This section applies to all hardware installations you may perform that involve the MVME172LX board.
1 Hardware Preparation and Installation ! Warning Turn the system’s power off before you perform these procedures. Failure to turn the power off before opening the enclosure can result in personal injury or damage to the equipment. Hazardous voltage, current, and energy levels are present in the chassis. Hazardous voltages may be present on power switch terminals even when the power switch is off. Never operate the system with the cover removed. Always replace the cover before powering up the system.
Preparing the Board Table 1-2. MVME172LX Jumper Settings Jumper Function Settings J1 VMEbus system controller selection J11 IP bus clock selection J12 No jumper [1-2] 2-3 Not system controller. System controller. Automatic system controller. [1-2] 2-3 IP bus clock = 8MHz. IP bus clock = local bus clock (30MHz / 32MHz). SCSI terminator status No jumper [1-2] Onboard SCSI bus terminators disabled. Onboard SCSI bus terminators enabled.
Hardware Preparation and Installation 1 MVME 172-2XX A1 B1 C1 27 26 2 1 27 26 2 1 RESET J6 J5 DS2 49 50 24 25 49 50 24 25 1 2 P1 49 50 24 25 49 50 24 25 J8 J7 J9 1 2 3 S2 1 9 ETHERNET PORT 15 J4 8 J3 J1 S1 49 50 J2 1 ABORT 1 2 FUSES SCON 49 50 19 20 DS1 A32 B32 C32 27 26 2 1 27 26 2 1 34 33 68 67 1 J11 J13 1 J12 1 3 2 2 16 2 16 2 4 2 J21 J20 A1 B1 C1 15 1 15 1 1 2 1 1 1 J19 3 J14 J18 2 J16 2 5 6 J23 PRIMARY SIDE SCSI INTERFACE 1 2 1 2 2 1 36 3
Preparing the Board System Controller Select Header (J1) The MVME172LX is factory-configured as a VMEbus system controller (i.e., a jumper is installed across pins 1 and 2 of header J1). Remove the J1 jumper if the MVME172LX is not to be the system controller. Note that when the MVME172LX is functioning as system controller, the SCON LED is turned on. Note On MVME172s without the optional VMEbus interface (i.e.
1 Hardware Preparation and Installation ! Caution The setting of the IP32 CSR bit (IP2 chip, register at offset $1D, bit 0) must correspond to that of the jumper. The bit is cleared (0) for 8MHz, or set (1) for 30/32MHz. If the jumper and the CSR bit are not configured the same, the board may not run properly.
Preparing the Board SRAM Backup Power Source Select Header (J14) Header J14 determines the source for onboard static RAM backup power on the MVME172LX. The following backup power configurations are available for onboard SRAM through header J14. In the factory configuration, the VMEbus +5V standby voltage serves as primary and secondary power source (the onboard battery is disconnected). Note For MVME172LXs without the optional VMEbus interface (i.e.
1 Hardware Preparation and Installation Flash Write Protect Header (J16) When the Flash write protect jumper is installed (factory configuration), the Flash memory can be written to via the normal software routines. When the jumper is removed, Flash memory cannot be written. J16 2 1 Flash Write Protect (Factory configuration) IP Bus Strobe Select Header (J18) Some IP bus implementations make use of the Strobe∗ signal (pin 46) as an input to the IP modules from the IP2 chip.
Preparing the Board IP DMA Snoop Jumper (J19) J19 defines the state of the snoop control bus when an IP DMA controller is local bus master. J19 pins 1 and 2 enable/disable the Snoop Control signal on the MC68060 processor (pins 3-4 have no function on MVME172LX boards). J19 J19 1 2 3 4 Snoop Inhibited (factory configuration) 1 2 3 4 Snoop Enabled For the MVME172LX, shorting pins 1-2 enables snooping. Leaving pins 1-2 disconnected (the factory configuration) inhibits snooping.
1 Hardware Preparation and Installation J20 supplies eight jumper headers for configuration of the EPROM sockets.
Preparing the Board The next four tables show the address range for each EPROM socket in all four configurations. GPI4 (J21 pins 9-10) is a control bit in the MC2chip ASIC that allows reset code to be fetched from Flash memory or from EPROMs. Table 1-3.
1 Hardware Preparation and Installation Table 1-5. EPROM/Flash Mapping — 1M x 8 EPROMs GPI4 Removed Installed Address Range 1 0 Device Accessed $FF800000 - $FF8FFFFF EPROM A (XU1) $FF900000 - $FF9FFFFF EPROM B (XU2) $FFA00000 - $FFBFFFFF Onboard Flash $FF800000 - $FF9FFFFF Onboard Flash $FFA00000 - $FFAFFFFF EPROM A (XU1) $FFB00000 - $FFBFFFFF EPROM B (XU2) Table 1-6.
Preparing the Board If the MVME172BUG firmware is installed, three jumpers are userdefinable (i.e., pins 11-12, 13-14, 15-16). If the MVME172BUG firmware is not installed, seven jumpers are user-definable (i.e., pins 1-2, 3-4, 5-6, 7-8, 11-12, 13-14, 15-16). Note Pins 9-10 (GPI4) are reserved to select either the Flash memory map (jumper installed) or the EPROM memory map (jumper removed). They are not user-definable.
1 Hardware Preparation and Installation Memory Mezzanine Options Two 100-pin connectors (J15 and J22) are provided on the MVME172LX to accommodate optional memory mezzanine boards. Two memory mezzanine options are available for the MVME172LX: ❏ 4, 8, 16MB parity DRAM ❏ 4, 8, 16, 32, 64MB ECC DRAM The mezzanine boards may either be used individually or be combined in a stack (not more than two deep).
Installation Instructions Installation Instructions This section covers: ❏ Installation of IndustryPacks (IPs) on the MVME172LX ❏ Installation of the MVME172LX in a VME chassis ❏ System considerations relevant to the installation. Ensure that EPROM devices are installed as needed. Ensure that all header jumpers are configured as desired. IP Installation on the MVME172LX Up to two IP modules may be installed on the MVME172LX. Install the IPs on the MVME172LX as follows: 1.
1 Hardware Preparation and Installation MVME172LX Installation With EPROMs and IP modules installed and headers properly configured, proceed as follows to install the MVME172LX in the VME chassis: 1. Turn all equipment power OFF and disconnect the power cable from the AC power source. ! Inserting or removing modules while power is applied could result in damage to module components. Caution ! Warning Dangerous voltages, capable of causing death, are present in this equipment.
Installation Instructions 6. On the chassis backplane, remove the INTERRUPT ACKNOWLEDGE (IACK) and BUS GRANT (BG) jumpers from the header for the card slot occupied by the MVME172LX. 7. Connect the appropriate cable(s) to the MVME172LX panel connectors for the EIA-232-D serial ports, SCSI port, and LAN Ethernet port. – Note that some cables are not provided with the MVME172LX and must be made or purchased by the user. (Motorola recommends shielded cable for all peripheral connections to minimize radiation.
1 Hardware Preparation and Installation The MVME172LX contains shared onboard DRAM whose base address is software-selectable. Both the onboard processor and offboard VMEbus devices see this local DRAM at base physical address $00000000, as programmed by the MVME172Bug firmware. This may be changed via software to any other base address. Refer to the MVME172 VME Embedded Controller Programmer’s Reference Guide for more information.
Installation Instructions The following circuits are protected by solid-state fuses that open during overload conditions and reset themselves once the overload is removed: ❏ LAN AUI ❏ SCSI terminator ❏ Remote reset connector ❏ IndustryPack 5V ❏ ±12V The FUSES LED illuminates to indicate that all fuses are functioning correctly. If a fuse opens, power must be removed for several minutes to allow the fuse to return to a closed or shorted condition.
1 Hardware Preparation and Installation Figure 1-2 diagrams the pin assignments required in a cable to adapt a DB25 DTE device to the RJ-45 connectors. DB-25 DTE DEVICE RJ-45 JACK DSR 6 DCD 8 1 DCD RTS 4 2 RTS 3 GND TXD 2 4 TXD RXD 3 5 RXD SG 7 6 GND CTS 5 7 CTS DTR 20 8 DTR Figure 1-2. DB-25 DTE-to-RJ-45 Adapter Figure 1-3 diagrams the pin assignments required in a cable to adapt a DB25 DCE device to an RJ-45 connector.
Installation Instructions Figure 1-4 diagrams the pin assignments required in a typical 8-conductor serial cable having RJ-45 connectors at both ends. Note that all wires are crossed. RJ-45 CONNECTOR RJ-45 CONNECTOR DCD 1 1 RTS 2 2 SG 3 3 TXD 4 4 RXD 5 5 SG 6 6 CTS 7 7 DTR 8 8 Figure 1-4. Typical RJ-45 Serial Cable http://www.mcg.mot.
1 Hardware Preparation and Installation 1-24 Computer Group Literature Center Web Site
2Startup and Operation 2 Introduction This chapter provides information on powering up the MVME172LX VME Embedded Controller after its installation in a system, and describes the functionality of the switches, status indicators, and I/O ports. For programming information, consult the MVME172 Embedded Controller Programmer’s Reference Guide.
Startup and Operation Table 2-1. MVME172LX Front Panel Controls 2 Control/Indicator Function FAIL LED (red) Board failure. Lights when the BRDFAIL* signal line is active. Part of DS1. RUN LED (green/amber) CPU activity. Lights when the local bus TIP* signal line is active. This indicates that one of the local bus masters is executing a local bus cycle. Part of DS1. SCON LED (green) System controller. Lights when the MVME172LX is functioning as VMEbus system controller. Part of DS2.
Applying Power Applying Power 2 When you power up (or when you reset) the system, the firmware executes some self-checks and proceeds to the hardware initialization. The system startup flows in a predetermined sequence, following the hierarchy inherent in the processor and the MVME172LX hardware. The figure below charts the flow of the basic initialization sequence that takes place during system startup.
Startup and Operation 2 Pre-Startup Checklist Before you power up the MVME172LX system, be sure that the following conditions exist: 1. Jumpers and/or configuration switches on the MVME172LX VME Embedded Controller and associated equipment are set as required for your particular application. 2. The MVME172LX board is installed and cabled up as appropriate for your particular chassis or system, as outlined in Chapter 1. 3.
Bringing up the Board Bringing up the Board 2 The MVME172LX comes with 172Bug firmware installed. For the firmware to operate properly with the board, you must follow the steps below. ! Inserting or removing boards with power applied may damage board components. Caution 1. Turn all equipment power OFF. Refer to MVME172LX Configuration on page 1-4 and configure jumpers on headers as necessary for your particular application. a.
Startup and Operation 2 Table 2-2. Software-Readable Jumpers J21 Bit No. Pins Function Bit #0 (GPI0) 1-2 When set to 1 (high), this bit instructs the debugger to use local static RAM for its work page (i.e., variables, stack, vector tables, etc.). Bit #1 (GPI1) 3-4 When set to 1 (high), this bit instructs the debugger to use the default setup/operation parameters in ROM instead of the user setup/operation parameters in Non-Volatile RAM (NVRAM).
Bringing up the Board Note In order for high-baud-rate serial communication between 172Bug and the terminal to work, the terminal must do some form of handshaking. If the terminal being used does not do hardware handshaking via the CTS line, then it must do XON/XOFF handshaking. If you get garbled messages and missing characters, then you should check the terminal to make sure XON/XOFF handshaking is enabled. 2 4.
Startup and Operation The board’s self-tests and operating systems require that the realtime clock be running. 2 Autoboot Autoboot is a software routine that is contained in the 172Bug Flash/PROM to provide an independent mechanism for booting an operating system. This autoboot routine automatically scans for controllers and devices in a specified sequence until a valid bootable device containing a boot media is found or the list is exhausted.
Bringing up the Board However, if the MVME172LX loses power but the controller does not, and the tape happens to be at load point, the necessary command sequences (attach and rewind) cannot be given to the controller and the autoboot will not succeed. 2 ROMboot As shipped from the factory, 172Bug occupies an EPROM installed in socket XU2. This leaves one socket (XU1) and the Flash memory available for your use.
Startup and Operation ❏ 2 Your routine passes a checksum test, which ensures that this routine was really intended to receive control at powerup. For complete details on using the ROMboot function, refer to the Debugging Package for Motorola 68K CISC CPUs User’s Manual. Network Boot Network Auto Boot is a software routine contained in the 172Bug Flash/PROM that provides a mechanism for booting an operating system using a network (local Ethernet interface) as the boot device.
Restarting the System Restarting the System 2 You can initialize the system to a known state in three different ways: Reset, Abort, and Break. Each method has characteristics which make it more suitable than the others in certain situations. A special debugger function is accessible during resets. This feature instructs the debugger to use the default setup/operation parameters in ROM instead of your own setup/operation parameters in NVRAM.
Startup and Operation You will need to reset your system if the processor ever halts, or if the 172Bug environment is ever lost (vector table is destroyed, stack corrupted, etc.). 2 Abort Aborts are invoked by pressing and releasing the ABORT switch on the MVME172LX front panel. When you invoke an abort while executing a user program (running target code), a snapshot of the processor state is stored in the target registers.
Diagnostic Facilities Diagnostic Facilities 2 The 172Bug package includes a set of hardware diagnostics for testing and troubleshooting the MVME172LX. To use the diagnostics, switch directories to the diagnostic directory. If you are in the debugger directory, you can switch to the diagnostic directory with the debugger command Switch Directories (SD). The diagnostic prompt 172-Diag> appears.
Startup and Operation 2 2-14 Computer Group Literature Center Web Site
3172Bug Firmware 3 Introduction The 172Bug firmware is the layer of software just above the hardware. The firmware supplies the appropriate initialization for devices on the MVME172LX board upon power-up or reset. This chapter describes the basics of 172Bug and its architecture, describes the monitor (interactive command portion of the firmware) in detail, and gives information on using the debugger and special commands. A list of 172Bug commands appears at the end of the chapter.
172Bug Firmware 172Bug includes: 3 ❏ Commands for display and modification of memory ❏ Breakpoint and tracing capabilities ❏ A powerful assembler/disassembler useful for patching programs ❏ A “self-test at power-up” feature which verifies the integrity of the system In addition, the TRAP #15 system calls make various 172Bug routines that handle I/O, data conversion, and string functions available to user programs.
172Bug Implementation If you have used one or more of Motorola’s other debugging packages, you will find the CISC 172Bug very similar. Some effort has also been made to make the interactive commands more consistent. For example, delimiters between commands and arguments may be commas or spaces interchangeably. 172Bug Implementation MVME172Bug is written largely in the "C" programming language, providing benefits of portability and maintainability.
172Bug Firmware . Table 3-1. Memory Offsets with 172Bug Type of Memory Present Default DRAM Base Address Default SRAM Base Address Single DRAM mezzanine $00000000 $FFE00000 (onboard SRAM) Single SRAM mezzanine N/A $00000000 DRAM mezzanine stacked with SRAM mezzanine $00000000 $E1000000 Two DRAM mezzanines stacked $00000000 $FFE00000 (onboard SRAM) 3 DRAM can be ECC or parity type. DRAM mezzanines are mapped in contiguously starting at zero ($00000000), largest first.
Using 172Bug Using 172Bug 172Bug is command-driven; it performs its various operations in response to commands that you enter at the keyboard. When the 172-Bug> prompt appears on the terminal screen, the debugger is ready to accept debugger commands. When the 172-Diag> prompt appears on the screen, the debugger is ready to accept diagnostics commands. To switch from one mode to the other, enter SD (Switch Directories).
172Bug Firmware ❏ One or more options. Precede an option or a string of options with a semicolon (;). If no option is entered, the command’s default option conditions are used. 3 Debugger Commands The 172Bug debugger commands are summarized in the following table. The commands are described in detail in the Debugging Package for Motorola 68K CISC CPUs User’s Manual. Table 3-2.
Debugger Commands Table 3-2.
172Bug Firmware Table 3-2.
Modifying the Environment Modifying the Environment You can use the factory-installed debug monitor, 172Bug, to modify certain parameters contained in the MVME172LX’s Non-Volatile RAM (NVRAM), also known as Battery Backed-Up RAM (BBRAM). ❏ The Board Information Block in NVRAM contains various elements concerning operating parameters of the hardware. Use the 172Bug command CNFG to change those parameters. ❏ Use the 172Bug command ENV to change configurable 172Bug parameters in NVRAM.
172Bug Firmware ECC Memory Mezzanine #1 Artwork (PWA) Identifier = " ECC Memory Mezzanine #1 (PWA) Serial Number = " " ECC Memory Mezzanine #2 Artwork (PWA) Identifier = " ECC Memory Mezzanine #2 (PWA) Serial Number = " " Serial Port 2 Personality Artwork (PWA) Identifier = " Serial Port 2 Personality Module (PWA) Serial Number = " IndustryPack A Board Identifier = " " IndustryPack A (PWA) Serial Number = " " IndustryPack A Artwork (PWA) Identifier = " " IndustryPack B Board Identifier = " " IndustryPack B
ENV - Set Environment ENV - Set Environment Use the ENV command to view and/or configure interactively all 172Bug operational parameters that are kept in Non-Volatile RAM (NVRAM). Refer to the Debugging Package for Motorola 68K CISC CPUs User’s Manual for a description of the use of ENV. Additional information on registers in the MVME172LX that affect these parameters appears in your MVME172 VME Embedded Controller Programmer’s Reference Guide.
172Bug Firmware Table 3-3. ENV Command Parameters (Continued) 3 ENV Parameter and Options Default Industry Pack Reset on Debugger Startup [Y/N] Y IP modules are reset on debugger startup. Meaning of Default Ignore CFGA Block on a Hard Disk Boot [Y/N] Y Configuration Area (CFGA) Block contents are disregarded at boot (hard disk only). Auto Boot Enable [Y/N] N Auto Boot function is disabled. Auto Boot at power-up only [Y/N] Y Auto Boot is attempted at power-up reset only.
ENV - Set Environment Table 3-3. ENV Command Parameters (Continued) Default Meaning of Default Network Auto Boot Controller LUN ENV Parameter and Options 00 Specifies LUN of a disk/tape controller module currently supported by the Bug. Default is $0. Network Auto Boot Device LUN 00 Specifies LUN of a disk/tape device currently supported by the Bug. Default is $0. Network Auto Boot Abort Delay 5 The time in seconds that the Network Boot sequence will delay before starting the boot.
172Bug Firmware Table 3-3. ENV Command Parameters (Continued) ENV Parameter and Options 3 Memory Search Increment Size Memory Search Delay Enable [Y/N] Memory Search Delay Address Memory Size Enable [Y/N] Default Meaning of Default 00010000 Multi-CPU feature used to offset the location of the Bug work page. This must be a multiple of the debugger work page, modulo $10000 (64KB). Typically, Memory Search Increment Size is the product of CPU number and size of the Bug work page.
ENV - Set Environment Table 3-3. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Note Memory Configuration Defaults. The default configuration for Dynamic RAM mezzanine boards will position the mezzanine with the largest memory size to start at the address selected with the ENV parameter "Base Address of Dynamic Memory". The Base Address parameter defaults to 0. The smaller sized mezzanine will follow immediately above the larger in the memory map.
172Bug Firmware Table 3-3. ENV Command Parameters (Continued) ENV Parameter and Options 3 Default Meaning of Default ENV asks the following series of questions to set up the VMEbus interface for the MVME172 series modules. You should have a working knowledge of the VMEchip2 as given in the MVME172 VME Embedded Controller Programmer’s Reference Guide in order to perform this configuration. Also included in this series are questions for setting ROM and Flash access time.
ENV - Set Environment Table 3-3. ENV Command Parameters (Continued) ENV Parameter and Options Slave Address Translation Select #2 Slave Control #2 Master Enable #1 [Y/N] Default Meaning of Default 00000000 Works the same as Slave Address Translation Select #1. Default is 0. 0000 Defines the access restriction for the address space defined with this slave address decoder. Default is $0000. Y Yes, set up and enable Master Address Decoder #1.
172Bug Firmware Table 3-3. ENV Command Parameters (Continued) ENV Parameter and Options 3 Default Meaning of Default Master Starting Address #3 00000000 Base address of the VMEbus resource that is accessible from the local bus. If enabled, the value is calculated as one more than the calculated size of memory. If not enabled, the default is $00000000. Master Ending Address #3 00000000 Ending address of the VMEbus resource that is accessible from the local bus.
ENV - Set Environment Table 3-3. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default F-Page (VMEbus A24) Enable [Y/N] Y Yes, Enable the F-Page Address Decoder. F-Page (VMEbus A24) Control 02 Defines the access characteristics for the address space defined with the F-Page address decoder. Default is $02. ROM Access Time Code 04 Defines the ROM access time. The default is $04, which sets an access time of five clock cycles of the local bus.
172Bug Firmware Note 3 The IP2 ASIC on the MVME172LX supports up to four IndustryPack (IP) interfaces, designated IP_a through IP_d. The MVME172LX itself accommodates two IPs: IP_a and IP_b. In the following discussion, the segments applicable to IP_c and IP_d are not used in the MVME172LX. IP A Base Address IP B Base Address IP C Base Address IP D Base Address = 00000000? = 00000000? = 00000000? = 00000000? Base address for mapping IP modules. Only the upper 16 bits are significant.
ENV - Set Environment IP D/C/B/A Interrupt 0 Control = 00000000? Define the interrupt control requirements for the IP modules channel 0: Bits IP Register Address 31-24 D FFFBC016 23-16 C FFFBC014 15-08 B FFFBC012 07-00 A FFFBC010 3 IP D/C/B/A Interrupt 1 Control = 00000000? Define the interrupt control requirements for the IP modules channel 1: ! Caution Bits IP Register Address 31-24 D FFFBC017 23-16 C FFFBC015 15-08 B FFFBC013 07-00 A FFFBC011 If you have specified envi
172Bug Firmware ENV warning example: WARNING: Memory MAP Overlap Condition Exists 3 S-Address $00000000 $FFE00000 $01000000 $00000000 $00000000 $00000000 $F0000000 $FFFF0000 $FF800000 $FFF00000 $00000000 $00000000 $00000000 $00000000 $00000000 $00000000 3-22 E-Address $FFFFFFFF $FFE7FFFF $EFFFFFFF $00000000 $00FFFFFF $00000000 $FF7FFFFF $FFFFFFFF $FFBFFFFF $FFFEFFFF $00000000 $00000000 $00000000 $00000000 $00000000 $00000000 Enable Yes Yes Yes No Yes No Yes Yes Yes Yes No No No No No No Overlap Yes Y
4Functional Description 4 Introduction This chapter describes the MVME172LX VME embedded controller on a block diagram level. The Description of Features provides an overview of the MVME172LX, followed by a detailed description of several blocks of circuitry. Figure 4-1 shows a block diagram of the overall board architecture.
Functional Description Table 4-1.
Block Diagram Input/Output (I/O) signals are routed through industry-standard connectors on the MVME172LX front panel; no adapter boards or transition modules are required. I/O connections include an optional 68-pin SCSI connector, an optional DB-15 Ethernet connector, and four 8-pin RJ-45 serial connectors on the front panel. In addition, the panel has cutouts for routing of flat cables to the optional IndustryPack modules. 4 The following ASICS are used on the MVME172LX: ❏ VMEchip2.
4-4 Optional MC68060 MC68LC060 MPU IP2 IndustryPack Interface VMEchip2 VMEbus Interface A32/D32 IndustryPack I/O 2 Channels 4,8,16,32,64MB ECC DRAM Memory Array 53C710 SCSI Coprocessor SCSI Peripherals 68-pin Front Panel SCSI Connector Configuration Dependent 4,8,16MB Parity DRAM Memory Array i82596CA Ethernet Controller Ethernet Transceiver DB-15 Front Panel Connector Optional MC2chip Two 32-pin EPROM Sockets 128KB SRAM Memory Array w/Battery M48T58 Battery Backed 8KB RAM/Clock Dual 85230
Functional Description Functional Description This section contains a functional description of the major blocks on the MVME172LX. Data Bus Structure 4 The local bus on the MVME172LX is a 32-bit synchronous bus that is based on the MC68060 bus, and which supports burst transfers and snooping. The various local bus master and slave devices use the local bus to communicate.
Functional Description Note The snoop capabilities of the MC68xx060 differ from those of the MC68xx040. Software must take these differences into consideration. No-VMEbus-Interface Option 4 The MVME172LX may be operated as an embedded controller without the VMEbus interface. To support this feature, certain logic in the VMEchip2 has been duplicated in the MC2chip. This logic is inhibited in the MC2chip when the VMEchip2 is present.
Functional Description Most DRAM devices require a certain number of access cycles before the DRAMs are fully operational. Normally this requirement is met by the onboard refresh circuitry and normal DRAM initialization. However, software should insure a minimum of 10 initialization cycles are performed to each bank of RAM. 4 SRAM Options The MVME172LX provides 128KB of 32-bit-wide onboard static RAM in a single non-interleaved architecture with onboard battery backup.
Functional Description The SRAM is controlled by the MC2chip, and the access time is programmable. Refer to the MC2chip description in the MVME172 VME Embedded Controller Programmer’s Reference Guide for more detail. About the Batteries The power source for the onboard SRAM is an Electro Marketing EM1275 device (or equivalent, such as RAYOVAC FB1225) with two BR1225type lithium cells. The battery is socketed for easy removal and replacement.
Functional Description ! Warning Lithium batteries incorporate inflammable materials such as lithium and organic solvents. If lithium batteries are mistreated or handled incorrectly, they may burst open and ignite, possibly resulting in injury and/or fire. When dealing with lithium batteries, carefully follow the precautions listed below in order to prevent accidents. ❏ Do not short circuit. ❏ Do not disassemble, deform, or apply excessive pressure. ❏ Do not heat or incinerate.
Functional Description Battery Backed Up RAM and Clock An M48T58 RAM and clock chip is used on the MVME172LX. This chip provides a time-of-day clock, oscillator, crystal, power fail detection, memory write protection, 8KB of RAM, and a battery in one 28-pin package. The clock provides seconds, minutes, hours, day, date, month, and year in BCD 24-hour format. Corrections for 28-, 29- (leap year), and 30-day months are automatically made. No interrupts are generated by the clock.
Functional Description Serial Communications Interface The MVME172LX uses two Zilog Z85230 serial port controllers to implement the four serial communications interfaces. Each interface supports CTS, DCD, RTS, and DTR control signals, as well as the TXD and RXD transmit/receive data signals. Because the serial clocks are omitted in the MVME172LX implementation, serial communications are strictly asynchronous. The MVME172LX hardware supports serial baud rates of 110b/s to 38.4Kb/s.
Functional Description Ethernet Interface The MVME172LX uses the Intel 82596CA LAN coprocessor to implement the Ethernet transceiver interface. The 82596CA accesses local RAM using DMA operations to perform its normal functions. Because the 82596CA has small internal buffers and the VMEbus has an undefined latency period, buffer overrun may occur if the DMA is programmed to access the VMEbus. Therefore, the 82596CA should not be programmed to access the VMEbus.
Functional Description Support functions for the 53C710 are provided by the MC2chip. Refer to the NCR 53C710 user’s guide and to the MC2chip in the MVME172 VME Embedded Controller Programmer’s Reference Guide for detailed programming information. SCSI Termination 4 It is important that the SCSI bus be properly terminated at both ends. The MVME172LX main board provides terminators for the SCSI bus. The SCSI terminators are enabled/disabled by a jumper on header J12.
Functional Description Watchdog Timer A watchdog timer is provided in both the MC2chip and the optional VMEchip2. The timers operate independently but in parallel. When the watchdog timers are enabled, they must be reset by software within the programmed time or they will time out. The watchdog timers may be programmed to generate a SYSRESET signal, local reset signal, or board fail signal if they time out.
Functional Description The access timer logic is duplicated in the VMEchip2 and MC2chip ASICs. Because the local bus timer in the VMEchip2 can detect an offboard access and the MC2chip local bus timer cannot, the timer in the VMEchip2 is used in all cases except for the version of the MVME172LX which does not include the VMEbus interface ("No VMEbus Interface option"). 4 Local Bus Arbiter The local bus arbiter implements a fixed priority (see Table 4-2). Table 4-2.
Functional Description Table 4-3. J2 Pin Assignments 4 1 P5VF LANLED 2 3 P12VLED SCSILED 4 5 VMELED No connection 6 7 RUNLED FAILSTAT STSLED No connection 8 9 11 SCONLED ABORTSW 12 13 RESETSW GND 14 15 GND GPI1 16 17 GPI2 GPI3 18 19 No connection GND 20 10 The serial ports on the MVME172LX are connected to four 8-pin RJ-45 female connectors (J17) on the front panel. The two IPs connect to the MVME172LX by two pairs of 50-pin connectors.
5Pin Assignments 5 Connector Pin Assignments This chapter summarizes the pin assignments for the following groups of interconnect signals on the MVME172LX: Connector Location Table J2 Table 5-1 J4/5/6, J3/7/8 Table 5-2 Ethernet port, DB15 J9 Table 5-3 Serial ports, RJ45 J17 Table 5-4 Memory Mezzanine connector 1 J22 Table 5-5 Memory Mezzanine connector 2 J15 Table 5-6 SCSI connector J23 Table 5-7 VMEbus connector P1 P1 Table 5-8 VMEbus connector, P2 P2 Table 5-9 Remote Reset co
Pin Assignments Remote Reset Connector - J2 The MVME172LX has a 20-pin connector (J2) mounted behind the front panel. When the MVME172LX board is enclosed in a chassis and the front panel is not visible, this connector enables you to extend the reset, abort and LED functions to the control panel of the system, where they remain accessible. Table 5-1.
Connector Pin Assignments Table 5-2.
Pin Assignments Ethernet Connector - J9 The MVME172LX’s Ethernet interface is implemented with a DB15 connector located on the front panel of the board. The pin assignments for this connector are listed in the following table. Table 5-3.
Connector Pin Assignments Memory Mezzanine Connector 1 - J22 Connector J22 is a standard double-row 100-pin socket connector mounted on the MVME172LX Embedded Controller PWB. It connects to a corresponding 100-pin plug connector on the ECC DRAM mezzanine board and (together with J15) carries the DRAM address, data, and control signals to and from the mezzanine board. The following table lists the pin assignments for J22. 5 Table 5-5.
Pin Assignments Table 5-5.
Connector Pin Assignments Memory Mezzanine Connector 2 - J15 Connector J15 is a standard double-row 100-pin socket connector mounted on the MVME172LX Embedded Controller PWB. It connects to a corresponding 100-pin plug connector on the ECC DRAM mezzanine board and (together with J22) carries the DRAM address, data, and control signals to and from the mezzanine board. The following table lists the pin assignments for J15. 5 Table 5-6.
Pin Assignments Table 5-6.
Connector Pin Assignments SCSI Connector - J23 Connector J23 is a standard 68-pin SCSI connector mounted on the front panel of the MVME172LX Embedded Controller. Table 5-7 lists the pin assignments for J23. VMEbus Connectors (P1, P2) Two three-row 96-pin DIN type connectors, P1 and P2, supply the interface between the base board and the VMEbus. P1 provides power and VME signals for 24-bit addressing and 16-bit data. Its pin assignments are set by the IEEE P1014-1987 VMEbus Specification.
Pin Assignments Table 5-7. SCSI Connector J23 Pin Assignments 5 5-10 1 GND GND 2 3 GND GND 4 5 GND GND 6 7 GND GND 8 9 GND GND 10 11 GND GND 12 13 GND GND 14 16 15 GND GND 17 +5.0V TERMPWR +5.
Connector Pin Assignments Table 5-8.
Pin Assignments Table 5-9.
ASpecifications A Board Specifications The following table lists the general specifications for the MVME172LX VME embedded controller. The subsequent sections detail cooling requirements and EMC regulatory compliance. A complete functional description of the MVME172LX boards appears in Chapter 4. Specifications for the optional IndustryPack modules can be found in the documentation for those modules. Table A-1.
A Cooling Requirements Cooling Requirements The Motorola MVME172LX VME Embedded Controller is specified, designed, and tested to operate reliably with an incoming air temperature range from 0° to 55° C (32° to 131° F) with forced air cooling of the entire assembly (base board and modules) at a velocity typically achievable by using a 100 CFM axial fan. Temperature qualification is performed in a standard Motorola VME system chassis.
Specifications Special Considerations for Elevated-Temperature Operation The following information is for users whose applications for the MVME172LX may subject it to high temperatures. The MVME172LX uses commercial-grade devices. Therefore, it can operate in an environment with ambient air temperatures from 0° C to 70° C. Several factors influence the ambient temperature seen by components on the MVME172LX.
A EMC Regulatory Compliance EMC Regulatory Compliance The MVME172LX was tested in an EMC-compliant chassis and meets the requirements for Class B equipment. Compliance was achieved under the following conditions: ❏ Shielded cables on all external I/O ports. ❏ Cable shields connected to chassis ground via metal shell connectors bonded to a conductive module front panel. ❏ Conductive chassis rails connected to chassis ground. This provides the path for connecting shields to chassis ground.
BTroubleshooting B Solving Startup Problems In the event of difficulty with your MVME172LX VME embedded controller, try the simple troubleshooting steps on the following pages before calling for help or sending the board back for repair. Some of the procedures will return the board to the factory debugger environment. (The board was tested under these conditions before it left the factory.) The selftests may not run in all user-customized environments. Table B-1.
Solving Startup Problems Table B-1. Troubleshooting MVME172LX Boards B Condition Possible Problem Try This: II. There is a display on the terminal, but input from the keyboard has no effect. A. The keyboard may be connected incorrectly. Recheck the keyboard connections and power. B. Board jumpers may be configured incorrectly. Check the board jumpers as described in this manual. C.
Troubleshooting Table B-1. Troubleshooting MVME172LX Boards Condition Possible Problem IV. Continued V. The debugger is in system mode and the board autoboots, or the board has passed self-tests. B Try This: 2. At the command line prompt, type in: env;d This sets up the default parameters for the debugger environment. 3. When prompted to Update Non-Volatile RAM, type in: y 4. When prompted to Reset Local System, type in: y 5.
Solving Startup Problems Table B-1. Troubleshooting MVME172LX Boards B Condition Possible Problem Try This: VI. The board has failed one or more of the tests listed above, and cannot be corrected using the steps given. A. There may be some fault in the board hardware or the on-board debugging and diagnostic firmware. 1. Document the problem and return the board for service. 2. Phone 1-800-222-5640. TROUBLESHOOTING PROCEDURE COMPLETE.
CNetwork Controller Data C Network Controller Modules Supported The 172Bug firmware supports following VMEbus network controller modules. The default address for each module type and position is shown to indicate where the controller must reside to be supported by the 172Bug. The controllers are accessed via the specified CLUN and DLUNs listed here.
Network Controller Modules Supported C C-2 Computer Group Literature Center Web Site
DDisk/Tape Controller Data D Disk/Tape Controller Modules Supported The 172Bug firmware supports the following VMEbus disk/tape controller modules. The default address for each controller type is First Address. The controller can be addressed by First CLUN during execution of the BH, BO, or IOP commands, or during execution of the TRAP #15 calls .DSKRD or .DSKWR.
Disk/Tape Controller Default Configurations Disk/Tape Controller Default Configurations Note SCSI Common Command Set (CCS) devices are the only ones tested by Motorola Computer Group.
Disk/Tape Controller Data IOT Command Parameters The following table lists the proper IOT command parameters for floppy disks used with boards such as the MVME328 and MVME172LX.
IOT Command Parameters D D-4 Computer Group Literature Center Web Site
ERelated Documentation E MCG Documents The Motorola Computer Group publications listed below are referenced in this manual. You can obtain paper or electronic copies of MCG publications by: ❏ Contacting your local Motorola sales office ❏ Visiting MCG’s World Wide Web literature site, http://www.mcg.mot.com/literature .. Table E-1.
Manufacturers’ Documents Manufacturers’ Documents For additional information, refer to the following table for manufacturers’ data sheets or user’s manuals. As a further help, sources for the listed documents are also provided. Please note that in many cases, the information is preliminary and the revision levels of the documents are subject to change without notice. Table E-2.
Related Documentation Table E-2. Manufacturers’ Documents (Continued) Document Title and Source Z85230 Serial Communications Controller Product Brief Zilog Inc. 210 Hacienda Avenue Campbell, CA 95008-6609 Web: http://www.zilog.com/products Publication Number Z85230pb.pdf E Related Specifications For additional information, refer to the following table for manufacturers’ data sheets or user’s manuals. As a further help, sources for the listed documents are also provided.
Related Specifications Table E-3. Related Specifications (Continued) Publication Number Document Title and Source NOTE: An earlier version of the VME specification is available as: E Versatile Backplane Bus: VMEbus Institute of Electrical and Electronics Engineers, Inc.
Index Numerics 172Bug firmware 3-9 implementation 3-3 overview 3-1 stack space 3-4 27C040 EPROM 3-3 53C710 SCSI controller 4-12 82596CA LAN coprocessor 4-12 A abort process 2-12 address ranges, EPROM 1-13 address/data configurations 1-19 addressing modes 1-19 altitude (operating) A-1 ambient air temperature A-2 arbitration priority 4-15 arguments, firmware command 3-5 autoboot process 2-8 B backplane jumpers 1-19 batteries 4-8 BBRAM (battery-backed-up RAM) and clock 3-9, 4-10 BG (bus grant) signal 1-19 b
Index connector pin assignments 5-1 connectors 4-15 console port 2-6 control/status registers 1-20 controller data D-1 controller LUN (CLUN) C-1, D-2 cooling requirements A-2 CSR bit IP32 1-8 CTS (Clear To Send) signal 2-7 D data bus structure, MVME172 4-5 data sheets E-2 data terminal equipment (DTE) 4-11 date and time, setting 2-7, B-2 debugger commands 3-6 firmware (172Bug) 3-9 prompt 3-5 default baud rate 2-6 device LUN (DLUN) C-1, D-2 diagnostic facilities 2-13 dimensions, base board A-1 direct acces
H J handshaking 2-7 hardware features 4-1 initialization 2-3 interrupts 4-14 preparation 1-1 high-temperature operation A-3 humidity, relative A-1 jumper headers J1 (system controller selection) 1-7 J11 (IP bus clock) 1-7 J12 (SCSI termination) 1-8 J14 (SRAM backup power) 1-9 J18 (IP bus strobe) 1-10 J19 (IP DMA snoop control) 1-11 J20 (EPROM/Flash configuration) 1-11 J21 (software-readable headers) 2-5 J23 (Flash write protection) 1-10 jumper headers, location of 1-4 jumpers, backplane 1-19 I I/O inter
Index MVME172 continued features 4-1 installation 1-18 regulatory compliance A-4 MVME172Bug documentation E-1 MVME328 SCSI Controller D-1 MVME374 network controller C-1 MVME376 network controller C-1 N network boot process 2-10 network controller modules C-1 non-volatile RAM (NVRAM) 3-9, 3-11 no-VMEbus-interface option 4-6 O operating parameters 3-9 operating temperature A-1 option fields, in firmware command 3-6 P P1 and P2 connectors 5-9 parameters, ENV command 3-11 parity DRAM 1-16 pin assignments, c
switches 2-1, 4-5 switching directories 2-13 system considerations 1-19 system console setup 2-6 system controller function 2-5 system controller select header (J1) 1-7 System Fail (SYSFAIL*) signal 2-9 system reset 2-11 system startup 2-3 T temperature operating A-1 storage A-1 terminal configuration 2-4 input/output control 3-5 thermal sensing header (J13) 1-8 tick timers 4-13 timeout global bus 1-20 local bus 4-14 troubleshooting procedures B-1 types of reset 2-11 U user-definable jumpers 1-15 V vibra
Index I N D E X IN-6 Computer Group Literature Center Web Site
MVME172LX VME Embedded Controller Installation and Use
