Technical data

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Hardware Preparation and Installation
1
The MVME172LX contains shared onboard DRAM whose base address
is software-selectable. Both the onboard processor and offboard VMEbus
devices see this local DRAM at base physical address $00000000, as
programmed by the MVME172Bug firmware. This may be changed via
software to any other base address. Refer to the MVME172 VME
Embedded Controller Programmer’s Reference Guide for more
information.
If the MVME172LX tries to access offboard resources in a nonexistent
location and is not system controller, and if the system does not have a
global bus timeout, the MVME172LX waits forever for the VMEbus cycle
to complete. This will cause the system to lock up. There is only one
situation in which the system might lack this global bus timeout: when the
MVME172LX is not the system controller and there is no global bus
timeout elsewhere in the system.
Multiple MVME172LXs may be installed in a single VME chassis. In
general, hardware multiprocessor features are supported.
Note If you are installing multiple MVME172LXs in an
MVME945 chassis, do not install an MVME172LX in slot
12. The height of the IP modules may cause clearance
difficulties in that slot position.
Other MPUs on the VMEbus can interrupt, disable, communicate with,
and determine the operational status of the processor(s). One register of the
GCSR (global control/status register) set includes four bits that function as
location monitors to allow one MVME172LX processor to broadcast a
signal to any other MVME172LX processors. All eight registers are
accessible from any local processor as well as from the VMEbus.