Technical data

3-4 Computer Group Literature Center Web Site
172Bug Firmware
3
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DRAM can be ECC or parity type. DRAM mezzanines are mapped in
contiguously starting at zero ($00000000), largest first. With two
mezzanines of the same size but different types, parity DRAM is mapped
to the selected base address and the ECC mezzanine will follow. If both
mezzanines are ECC type, the bottom one is first.
The 172Bug requires 2KB of NVRAM for storage of board configuration,
communication, and booting parameters. This storage area begins at
$FFFC16F8 and ends at $FFFC1EF7.
172Bug requires a minimum of 64KB of contiguous read/write memory to
operate. The ENV command controls where this block of memory is
located. Regardless of where the onboard RAM is located, the first 64KB
is used for 172Bug stack and static variable space and the rest is reserved
as user space. Whenever the MVME172LX is reset, the target PC is
initialized to the address corresponding to the beginning of the user space,
and the target stack pointers are initialized to addresses within the user
space, with the target Interrupt Stack Pointer (ISP) set to the top of the user
space.
Table 3-1. Memory Offsets with 172Bug
Type of Memory Present Default DRAM
Base Address
Default SRAM
Base Address
Single DRAM mezzanine $00000000 $FFE00000
(onboard SRAM)
Single SRAM mezzanine N/A $00000000
DRAM mezzanine stacked with SRAM mezzanine $00000000 $E1000000
Two DRAM mezzanines stacked $00000000 $FFE00000
(onboard SRAM)