Technical data

Block Diagram
http://www.mcg.mot.com/literature 4-3
4
Input/Output (I/O) signals are routed through industry-standard connectors
on the MVME172LX front panel; no adapter boards or transition modules
are required. I/O connections include an optional 68-pin SCSI connector,
an optional DB-15 Ethernet connector, and four 8-pin RJ-45 serial
connectors on the front panel. In addition, the panel has cutouts for routing
of flat cables to the optional IndustryPack modules.
The following ASICS are used on the MVME172LX:
❏ VMEchip2. (VMEbus interface). Provides two tick timers, a
watchdog timer, programmable map decoders for the master and
slave interfaces, and a VMEbus to/from local bus DMA controller,
a VMEbus to/from local bus non-DMA programmed access
interface, a VMEbus interrupter, a VMEbus system controller, a
VMEbus interrupt handler, and a VMEbus requester.
Processor-to-VMEbus transfers are D8, D16, or D32. VMEchip2
DMA transfers to the VMEbus, however, are D16, D32, D16/BLT,
D32/BLT, or D64/MBLT.
❏ MC2chip. Provides four tick timers, the interface to the LAN chip,
SCSI chip, serial port chip, BBRAM, EPROM/Flash, parity-DRAM
and SRAM.
❏ MCECC memory controller. Provides the programmable
interface for the ECC-protected 16MB DRAM mezzanine board.
❏ IndustryPack Interface Controller (IP2). The IP2 provides
control and status information for up to two single-wide IPs or one
double-wide IP that can be plugged into the MVME172LX main
board.
Block Diagram
The block diagram in Figure 4-1 on page 4-4 illustrates the
MVME172LX’s overall architecture.