Technical data

4-6 Computer Group Literature Center Web Site
Functional Description
4
Note The snoop capabilities of the MC68xx060 differ from those
of the MC68xx040. Software must take these differences into
consideration.
No-VMEbus-Interface Option
The MVME172LX may be operated as an embedded controller without
the VMEbus interface. To support this feature, certain logic in the
VMEchip2 has been duplicated in the MC2chip. This logic is inhibited in
the MC2chip when the VMEchip2 is present. The enables for these
functions are controlled by software and MC2chip hardware initialization.
Memory Options
The following memory options are available on the different versions of
MVME172LX boards.
DRAM Options
The MVME172LX offers the following DRAM options: either 4MB,
8MB, or 16MB shared DRAM with programmable parity on a mezzanine
module, or 4MB, 8MB, 16MB, 32MB, and 64MB ECC DRAM on a
mezzanine board. The DRAM architecture for non-ECC memory is non-
interleaved for 4MB or 8MB and interleaved for 16MB. Parity protection
is enabled with interrupts or bus exception when a parity error is detected.
DRAM performance is specified in the section on the DRAM Memory
Controller in the MC2chip Programming Model in the MVME172 VME
Embedded Controller Programmer’s Reference Guide.
The DRAM map decoder may be programmed to accommodate different
base address(es) and sizes of mezzanine boards. The onboard DRAM is
disabled by a local bus reset and must be programmed before the DRAM
may be accessed. Refer to the MC2chip and MCECC descriptions in the
MVME172 VME Embedded Controller Programmer’s Reference Guide
for detailed programming information.