Technical data

PMCspan Features
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PMCspan Features
PMCspans have the following features:
❏ They are operational with the MVME2300/2600/2700/3600/4600
processor modules.
❏ They provide support for two single-width PMC adapters or one
double-width PMC adapter.
❏ They incorporate 5V bus signaling voltage.
❏ They incorporate both PMC Bus and VMEbus connectors with the
following features:
– Two sets of three EIA E700 AAAB connectors for 32-bit PMC
interface to secondary PCI bus and user specific I/O.
– P1 connector for power and BGNT and IACK daisy chaining.
– 5-row P2 connector for power and PMC I/O.
❏ They incorporate a DEC 21150 PCI-to-PCI Bridge Interface device,
with the following features (PMCspan-001/-002 only):
– PCI Revision 2.1 compliant.
– 32-bit primary bus interface.
– 32-bit secondary bus interface.
– Delayed transactions for all PCI configuration, I/O, and memory
read commands, allowing up to three transactions
simultaneously in each direction
– Buffering (data and address) for posted memory write
commands in each direction, allowing up to five posted write
transactions simultaneously in each direction.
– Read data buffering in each direction.
– Concurrent primary and secondary bus operation to isolate
traffic.
– Enhanced address decoding.
– PCI transaction forwarding.