Technical data

3-6
Functional Description
3
T
start
Start-up time (TS# to PCI bus Request).
T
start
is 6 system clocks.
T
arb
On-board PCI bus arbitration time.
T
ac
On-board PCI access time (FRAME# to TRDY#).
T
lat
Latency through PCI-to-PCI bridge.
T
delay
Delay time from TRDY# on PCI to TA# on 60X bus. T
delay
is 4 system clocks.
Table 3-1 shows the access timings for various types of transfers initiated
by a 60X system bus master to a PMCspan module.
Table 3-1. PowerPC 60x Bus to PMCspan PMC Access Timing
Access Type
System Clock Periods Required for:
Total
Clocks
1st Beat 2nd Beat 3rd Beat 4th Beat
4-Beat Read
(32-bit PCI Target)
49 1 1 1 52
4-Beat Write
(32-bit PCI Target)
41117
1-Beat Read
(aligned, 4 bytes or less)
38 - - - 38
1-Beat Write 4 - - - 4
Notes Write cycles are posted by the Raven ASIC.
Assumes no pipeline. Pipelined cycles would improve
these numbers.
T
arb
is assumed to be 4 system clocks (2 PCI clocks).
T
ac
is assumed to be 6 system clocks (3 PCI clocks):
Medium DEVSEL# target, zero wait PCI timing.