Technical data

Configuration Transactions
4-3
4
Type 0 Configuration Cycles
Type 0 configuration cycles are issued to configure devices on the same
bus as the initiator. The processor will access configuration registers
within the 21150, issuing a Type 0 cycle on the primary PCI bus by
programming the Raven CONADD Register for Bus Number 0, and
Device Number 1_0100 (binary). The Function Code is ignored by the
21150 since it is a single-function device. The RAVEN chip will translate
this configuration address to an IDSEL# on AD20, which is connected to
the DEVSEL# on the 21150 on the PMCspan.
The 21150 limits all configuration register accesses to a single double
word data transfer and returns a target disconnect with the first data
transfer if additional data phases are requested. All bytes of the requested
double word are returned, regardless of the PCI byte enable bits. Type 0
configuration transactions do not use the 21150 data buffers so these
transactions are completed immediately regardless of the state of the data
buffers.
The 21150 will ignore all Type 0 transactions initiated on the secondary
PCI bus.
Type 1 Configuration Cycles
Type 1 configuration cycles are issued to configure PMC adapters. The
processor will access configuration registers within the PMC adapters by
issuing a Type 1 cycle on the primary PCI bus by programming the Raven
CONADD Register for Bus Number $01 (i.e., the Bus Number
programmed into the Secondary Bus Number register), and the Device
Number per Table 4-1. The Function Code is dependent on the PMC
adapters.
The 21150 will perform a Type 1 to Type 0 translation when the Type 1
transaction generated on the primary bus is intended for a PMC adapter on
the secondary bus. The PMC adapter can then respond to the Type 0
transaction.
The 21150 forwards Type 1 to Type 0 configuration transactions as
delayed transactions which are limited to a single data transfer.