Technical data

PMC Clock, Request, Grant Assignment
4-9
4
PMC Clock, Request, Grant Assignment
The 21150 bridge chip provide individual clock sources and arbitration
logic for each PMC adapter on the secondary PCI bus. The PMCspan
routes the secondary PCI bus Clock, Request and Grant signals between
the 21150 bridge chip and the PMC slots as shown in Table 4-3.
PMC Present Signal Assignment
The PMCspan hardwires the BUSMODE(4:2)# encoding signals to 001
(binary) for each PMC slot indicating that the PMCspan supports PCI
protocol. The signal BUSMODE1# returned from each PMC adapter
indicates there is a PMC adapter installed in the slot and that the PMC
adapter supports PCI protocol. The PMC Present signals from each PMC
slot may be read at any time following a reset on the 21150 GPIO pins.
Table 4-4 shows the assignment of the PMC Present signals to the GPIO
pins. Figure 4-4 shows the values in the Serial Clock Mask register
following a reset. Serial Clock Mask bit 13 is 0 in order to enable
s_clk_o(9) for the 21150 s_clk input.
Table 4-3. PMC Clock, Request, Grant Assignments
PMC
21150
Clock Source
21150
Request
21150
Grant
1 (Slot 1 on PMCspan-001/-002) s_clk_o(0) s_req_l(0) s_gnt_l(0)
2 (Slot 2 on PMCspan-001/-002) s_clk_o(1) s_req_l(1) s_gnt_l(1)
3 (Slot 1 on PMCspan-010) s_clk_o(2) s_req_l(2) s_gnt_l(2)
4 (Slot 2 on PMCspan-010) s_clk_o(3) s_req_l(3) s_gnt_l(3)