User Guide

Figure 10. Sample Clock Timing Options

Routing AI Sample Clock to an Output Terminal

You can route ai/SampleClock to any output PFI terminal.

AI Sample Clock Timebase

The AI Sample Clock Timebase (ai/SampleClockTimebase) signal is

divided down to provide a source for ai/SampleClock. ai/SampleClock

Timebase can be generated from external or internal sources.

ai/SampleClockTimebase is not available as an output from the chassis.

Convert Behavior For Analog Input Modules

Scanned

Scanned C Series analog input modules contain a single A/D converter and

a multiplexer to select between multiple input channels. When the cDAQ

Module Interface receives a Sample Clock pulse, it begins generating a

Convert Clock for each scanned module in the current task. Each Convert

Clock signals the acquisition of a single channel from that module. The

Convert Clock rate depends on the module being used, the number of

channels used on that module, and the system Sample Clock rate.

The driver chooses the fastest conversion rate possible based on the speed

of the A/D converter for each module and adds 10 µs of padding between

each channel to allow for adequate settling time. This scheme enables the

channels to approximate simultaneous sampling. If the AI Sample Clock

rate is too fast to allow for 10 µs of padding, NI-DAQmx selects a

conversion rate that spaces the AI Convert Clock pulses evenly throughout

the sample. NI-DAQmx uses the same amount of padding for all the

modules in the task. To explicitly specify the conversion rate, use the

Analog Comparison

Event

20 MHz Timebase

100 kHz Timebase

Programmable

Clock

Divider

ai/SampleClock

Timebase

PFI

Analog Comparison Event

Ctr

Internal Output

ai/SampleCloc

PFI

Sigma-Delta Module Internal Output