User's Manual

NDA-24300 CHAPTER 2
Page 19
Issue 1
SYSTEM MAINTENANCE OUTLINE
Figure 2-15 General System Block Diagram
CPU 0
To MUX
To MUX
To MUX (IMG2)
To MUX (IMG2)
To MUX (IMG3)
To MUX (IMG3)
IMG0
TSWM
LPM
MISC I/O BUS
MISC I/O BUS MISC I/O BUS
01
E1/DS1
with
Fusion Link
E1/DS1
with
Fusion Link
SERIAL BUS
PM BUS
PM BUS
PM BUS
PM BUS
PM BUS
PM BUS
PM BUS
PM BUS
T
S
W
I
/
O
B
U
S
0
RS-232C
10 BASE-T
10 BASE-T 10 BASE-T
G
T
U
S
Symbols
EMA: PH-PC40 ISAGT: PZ-GT13 LANI: PZ-PC19 GT: PH-GT09 IOC: PH-IO24
TSW: PH-SW12 DLKC: PH-PC20 MUX: PH-PC36 PLO: PH-CK16/17/16-A/17-A
LC/TRK LC/TRK
MUX
MUX
LC/TRK LC/TRK
MUX
LC/TRK LC/TRK
MUX
DTI
FCH LC/TRK
MUX
MUX
MUX
MUX
LC/TRK LC/TRK
LC/TRK LC/TRK
LC/TRK LC/TRK
DTI
FCH
LC/TRK
TSW 00
TSW 10
TSW 01
TSW 11
TSW 02
TSW 12
TSW 03
TSW 13
PLO 0
PLO 1
MISC
GT 1GT 0
DLKC 0 DLKC 1
MAT
MATAP
HUB
HUB HUB
EMA
MISC
IOC
ISAGT
LANI LANI
CPU 1
ISAGT
LANI LANI
G
T
B
U
S
B
T
S
W
I
/
O
B
U
S
0
: Circuit Card