User's Manual

CHAPTER 6 NDA-24300
Page 462
Issue 1
SYSTEM OPERATIONS
Figure 6-42 System Block Diagram (Switching Network Between CPU and GT)
IMG0 IMG1 IMG2 IMG3
TSW I/O BUS
TSW I/O BUS
CPR 0
CPR 1
MISC BUS
IOP0
Backboard
Backboard Bus
T
External Cable
TSW 00
GT 0
GT 1
CPU 1
MUX MUX MUX MUX
TSW 10
TSW 01
MUX MUX MUX MUX
TSW 11
TSW 02
MUX MUX MUX MUX
TSW 12
TSW 03
MUX MUX MUX MUX
TSW 13
DLKC 1
DLKC 0
PLO 1
PLO 0
ISAGT
LANI LANI
ISAGT
LANI LANI
IOC/
MISC
EMA
CPU 0
CPU
ISAGT0
GT 1
GT 0
Note:
The connection between ISAGT and GT is somewhat unique in this system. As shown, though an
external cable is physically connected between ISAGT #0 and GT#1, the actual control signal is
sent/received only between ISAGT 0 and GT 0. This is because GT 0 and GT 1 have a multiple con-
nection on the backboard side.
Note
ISAGT: PZ-GT13 LANI: PZ-PC19 GT: PH-GT09 TSW: PH-SW12 MUX: PH-PC36
DLKC: PH-PC20 PLO: PH-CK16/17 EMA: PH-PC40 IOC: PH-IO24