Single-Chip Microcontrollers User's Manual

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User’s Manual

Printed in Japan

PD78058F, 78058FY Subseries

8-Bit Single-Chip Microcontrollers

PD78056F

PD78058F

PD78P058F

PD78058F(A)

PD78056FY

PD78058FY

PD78P058FY

PD78058FY(A)

Document No. U12068EJ2V0UM00 (2nd edition)

Date Published April 1998 N CP (K)

1997

Summary of content (593 pages)

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User’s Manual µPD78058F, 78058FY Subseries 8-Bit Single-Chip Microcontrollers µPD78056F µPD78058F µPD78P058F µPD78058F(A) µPD78056FY µPD78058FY µPD78P058FY µPD78058FY(A) Document No.
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[MEMO] 2
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used.
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The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors.
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MAJOR REVISIONS IN THIS EDITION Page Throughout Major Revision from Previous Edition The following products have already been developed: µPD78056FGC-×××-8BT, 78058FGC-×××-8BT, 78P058FGC-8BT, 78056FYGC-×××-8BT, 78058FYGC-×××-8BT P133 to The block diagrams of the following ports were changed.
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PREFACE Readers This manual has been prepared for user engineers who want to understand the functions of the µPD78058F and 78058FY Subseries and design and develop its application systems and programs. Affected versions are each of the versions in the following Subseries. µPD78058F Subseries : µPD78056F, 78058F, 78P058F, 78058F(A) µPD78058FY Subseries : µPD78056FY, 78058FY, 78P058FY, 78058FY(A) Purpose This manual is intended for users to understand the functions described in the Organization below.
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How to Read This Manual Before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers. For persons who use this manual as the manual for the µPD78058F(A) and 78058FY(A), → The µPD78058F and 78058FY differ from the µPD78058F(A) and 78058FY(A) only in their quality grades. For products with (A), please change the readings for the product name as follows.
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Chapter Organization This manual divides the descriptions for the µPD78058F and 78058FY Subseries into different chapters as shown below. Read only the chapters related to the device you use.
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Differences between µPD78058F and µPD78058FY Subseries: The µPD78058F and µPD78058FY Subseries are different in the following functions of the serial interface channel 0.
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Related Documents for µPD78058F Subseries Document No.
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Development Tool Documents (User’s Manuals) Document No.
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Documents for Embedded Software (User’s Manual) Document No. Document Name Japanese 78K/0 Series Real-Time OS OS for 78K/0 Series MX78K0 English Basics U11537J U11537E Installation U11536J U11536E Basics U12257J U12257E Other Documents Document No.
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CONTENTS CHAPTER 1 OUTLINE (µPD78058F SUBSERIES) ............................................................................. 35 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 Features .................................................................................................................................. Applications ........................................................................................................................... Ordering Information .........................................
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3.2.14 AVSS .............................................................................................................................................. 3.3 71 3.2.15 RESET ......................................................................................................................................... 71 3.2.16 X1 and X2 .................................................................................................................................... 71 3.2.17 XT1 and XT2 .................
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5.3 5.4 5.2.1 Control registers ........................................................................................................................... 103 5.2.2 General registers .......................................................................................................................... 106 5.2.3 Special Function Register (SFR) .................................................................................................. 108 Instruction Address Addressing .....................
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7.5 7.6 7.4.2 Subsystem clock oscillator ........................................................................................................... 162 7.4.3 Scaler ........................................................................................................................................... 164 7.4.4 When no subsystem clocks are used ........................................................................................... 164 Clock Generator Operations ...............................
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CHAPTER 11 WATCHDOG TIMER ...................................................................................................... 245 11.1 11.2 11.3 11.4 Watchdog Timer Functions ................................................................................................ Watchdog Timer Configuration .......................................................................................... Watchdog Timer Control Registers ...................................................................................
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16.4.3 SBI mode operation ................................................................................................................. 305 16.4.4 2-wire serial I/O mode operation ............................................................................................. 331 16.4.5 SCK0/P27 pin output manipulation ......................................................................................... 336 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) .............................
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.2 21.3 21.4 21.5 Interrupt Sources and Configuration ................................................................................. 478 Interrupt Function Control Registers ................................................................................. 482 Interrupt Servicing Operations ........................................................................................... 491 21.4.1 Non-maskable interrupt acknowledge operation .................................................................
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26.3.3 26.4 PROM read procedure ............................................................................................................ 546 Screening of One-Time PROM Versions ........................................................................... 547 CHAPTER 27 INSTRUCTION SET ....................................................................................................... 549 27.1 Legends Used in Operation List ...........................................................................
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LIST OF FIGURES (1/8) Figure No. Title Page 3-1 List of Pin Input/Output Circuit .......................................................................................................... 75 4-1 List of Pin Input/Output Circuit .......................................................................................................... 93 5-1 Memory Map (µPD78056F, 78056FY) ..............................................................................................
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LIST OF FIGURES (2/8) Figure No. Title Page 7-4 Oscillation Mode Selection Register Format ..................................................................................... 159 7-5 Main System Clock Waveform due to Writing to OSMS ................................................................... 160 7-6 External Circuit of Main System Clock Oscillator .............................................................................. 161 7-7 External Circuit of Subsystem Clock Oscillator ....
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LIST OF FIGURES (3/8) Figure No. Title Page 8-31 Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger ................ 204 8-32 Timing of One-Shot Pulse Output Operation Using Software Trigger ............................................... 205 8-33 Control Register Settings for One-Shot Pulse Output Operation Using External Trigger ................. 206 8-34 Timing of One-Shot Pulse Output Operation Using External Trigger (with Rising Edge Specified) ..
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LIST OF FIGURES (4/8) Figure No. Title Page 14-1 A/D Converter Block Diagram ........................................................................................................... 263 14-2 A/D Converter Mode Register Format .............................................................................................. 266 14-3 A/D Converter Input Select Register Format ....................................................................................
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LIST OF FIGURES (5/8) Figure No. Title Page 16-27 Address Transmission from Master Device to Slave Device (WUP = 1) .......................................... 325 16-28 Command Transmission from Master Device to Slave Device ......................................................... 326 16-29 Data Transmission from Master Device to Slave Device .................................................................. 327 16-30 Data Transmission from Slave Device to Master Device ......................
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LIST OF FIGURES (6/8) Figure No. Title 18-5 Automatic Data Transmit/Receive Interval Specify Register Format ................................................ 395 18-6 3-Wire Serial I/O Mode Timings ........................................................................................................ 401 18-7 Circuit of Switching in Transfer Bit Order ..........................................................................................
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LIST OF FIGURES (7/8) Figure No. Title Page 20-4 Real-time Output Port Mode Register Format .................................................................................. 474 20-5 Real-time Output Port Control Register Format ................................................................................ 475 21-1 Basic Configuration of Interrupt Function .........................................................................................
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LIST OF FIGURES (8/8) Figure No. Title Page 25-1 Block Diagram of ROM Correction ................................................................................................... 527 25-2 Correction Address Registers 0 and 1 Format .................................................................................. 528 25-3 Correction Control Register Format ..................................................................................................
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LIST OF TABLES (1/3) Table No. Title Page 1-1 Differences Between the µPD78058F and µPD78058F(A) .............................................................. 45 1-2 Mask Options of Mask POM Versions .............................................................................................. 46 2-1 Differences Between the µPD78058FY and µPD78058FY(A) .......................................................... 57 2-2 Mask Options of Mask ROM Versions ..........................................
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LIST OF TABLES (2/3) Table No. 9-10 32 Title Page Square-Wave Output Ranges When 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter ................................................................ 234 10-1 Interval Timer Interval Time .............................................................................................................. 239 10-2 Watch Timer Configuration .................................................................................
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LIST OF TABLES (3/3) Table No. Title Page 20-2 Operation in Real-time Output Buffer Register Manipulation ............................................................ 473 20-3 Real-time Output Port Operating Mode and Output Trigger ............................................................. 475 21-1 Interrupt Source List .........................................................................................................................
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CHAPTER 1 OUTLINE (µPD78058F SUBSERIES) 1.1 Features Compared to the conventional µPD78054 Subseries, EMI (Electro Magnetic Interference) noise has been reduced. On-chip high-capacity ROM and RAM Item Data Memory Program Memory (ROM) Internal High-Speed RAM µPD78056F 48 Kbytes 1024 bytes µPD78058F 60 Kbytes Part Number µPD78P058F Notes 60 KbytesNote 1 Internal Buffer RAM 32 bytes Internal Expansion RAM None 1024 bytes 1024 bytesNote 1 1024 bytesNote 2 1.
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CHAPTER 1 OUTLINE (µPD78058F SUBSERIES) 1.2 Applications In the case of the µPD78056F, 78058F and 78P058F, Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPC’s, fuzzy home appliances, vending machines, etc. In the case of the µPD78058F (A), Controllers for car electronics, gas detection and shut-off devices, various safety devices, etc. 1.3 Ordering Information Part Number Package Internal ROM µPD78056FGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.
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CHAPTER 1 OUTLINE (µPD78058F SUBSERIES) 1.4 Quality Grade Part Number Package Quality Grade µPD78056FGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Standard µPD78056FGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard µPD78058FGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Standard µPD78058FGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
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CHAPTER 1 OUTLINE (µPD78058F SUBSERIES) 1.5 Pin Configuration (Top View) (1) Normal operating mode 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) µPD78056FGC-×××-3B9, 78058FGC-×××-3B9, 78058FGC(A)-×××-3B9, 78P058FGC-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
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CHAPTER 1 OUTLINE (µPD78058F SUBSERIES) Pin Identifications A8 to A15 : Address Bus P130, P131 : Port13 AD0 to AD7 : Address/Data Bus PCL : Programmable Clock ANI0 to ANI7 : Analog Input RD : Read Strobe ANO0, ANO1 : Analog Output RESET : Reset ASCK : Asynchronous Serial Clock RTP0 to RTP7 : Real-Time Output Port ASTB : Address Strobe RxD : Receive Data AVDD : Analog Power Supply SB0, SB1 : Serial Bus AVREF0, 1 : Analog Reference Voltage SCK0 to SCK2 : Serial
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CHAPTER 1 OUTLINE (µPD78058F SUBSERIES) (2) PROM programming mode 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) µPD78P058FGC-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) VDD (L) PGM (L) A9 (L) A2 A3 A4 A5 A6 A7 A8 A16 A10 A11 A12 A13 VSS A14 A15 A0 A1 Cautions 1. (L) 2.
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CHAPTER 1 OUTLINE (µPD78058F SUBSERIES) 1.6 78K/0 Series Expansion The 78K/0 Series expansion is shown below. The names in frames are subseries. Products in mass production Products under development Y subseries products are compatible with I2C bus.
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CHAPTER 1 OUTLINE (µPD78058F SUBSERIES) The differences between the major functions of each subseries are shown below. Function Subseries Control ROM Timer Capacity 8-bit 16-bit Watch WDT µPD78075B 32 K to 40 K 4 ch µPD78078 48 K to 60 K µPD78070A 1 ch 1 ch 8-bit 10-bit 8-bit 1 ch A/D A/D 8 ch — I/O 2 ch 3 ch (UART: 1 ch) 88 1.8 V 61 2.7 V — 24 K to 60 K 2 ch 3 ch (time-division UART: 1 ch) 68 1.8 V µPD78058F 48 K to 60 K 3 ch (UART: 1 ch) 69 2.
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CHAPTER 1 OUTLINE (µPD78058F SUBSERIES) 1.
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CHAPTER 1 OUTLINE (µPD78058F SUBSERIES) 1.8 Outline of Function Part Number µPD78056F Item Internal memory ROM µPD78058F Mask ROM PROM 48 Kbytes High-speed RAM 1024 bytes Buffer RAM 32 bytes Expansion RAM None Memory space µPD78P058F 60 Kbytes 60 KbytesNote 1 1024 bytesNote 1 1024 bytes 1024 bytesNote 2 64 Kbytes General register 8 bits × 8 × 4 banks Minimum With main system clock selected instruction execution With subsystem clock selected time 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.
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OUTLINE (µPD78058F SUBSERIES) CHAPTER 1 Part Number µPD78056F Item Buzzer output µPD78058F µPD78P058F 1.2 kHz, 2.4 kHz, 4.9 KHz, 9.8 kHz (main system clock at 5.0-MHz operation) Vectored Maskable Internal: 13 interrupt sources External: 7 Non-maskable Internal: 1 Software 1 Test input Internal: 1 External: 1 Supply voltage VDD = 2.7 to 6.0 V Operating ambient temperature TA = –40 to +85 °C Package • 80-pin plastic QFP (14 × 14 mm, Resin thickness : 2.
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CHAPTER 1 OUTLINE (µPD78058F SUBSERIES) 1.10 Mask Options There are mask options in the mask ROM versions (µPD78056F, 78058F). By specifying the mask option when ordering, you can have the pull-up resistors shown in Table 1-2 incorporated on-chip. If a mask option is used when pull-up resistors are required, the number of parts can be reduced and package area can be shrunk. The mask option provided for the µPD78058F Subseries is shown in Table 1-2. Table 1-2.
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CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES) 2.1 Features Compared to the conventional µPD78054Y Subseries, EMI (Electro Magnetic Interference) noise has been reduced. On-chip high-capacity ROM and RAM Item Part Number Program Memory (ROM) µPD78056FY 48 Kbytes µPD78058FY 60 Kbytes µPD78P058FY 60 KbytesNote 1 Notes Data Memory Internal High-Speed RAM 1024 bytes Internal Buffer RAM 32 bytes Internal Expansion RAM None 1024 bytes 1024 bytesNote 1 1024 byesNote 2 1.
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CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES) 2.2 Applications In the case of the µPD78056FY, 78058FY and 78P058FY, Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending machines, etc. In the case of the µPD78058FY (A), Controllers for car electronics, gas detection and shut-off devices, various safety devices, etc. 2.3 Ordering Information Part Number Package Internal ROM µPD78056FYGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.
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CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES) 2.4 Quality Grade Part Number Package Quality Grade µPD78056FYGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Standard µPD78056FYGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard µPD78058FYGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Standard µPD78058FYGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
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CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES) 2.5 Pin Configuration (Top View) (1) Normal operating mode 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) µPD78056FYGC-×××-3B9, 78058FYGC-×××-3B9, 78058FYGC(A)-×××-3B9, µPD78P058FYGC-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
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CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES) Pin Identifications A8 to A15 : Address Bus PCL : Programmable Clock AD0 to AD7 : Address/Data Bus RD ; Read Strobe ANI0 to ANI7 : Analog Input RESET : Reset ANO0, ANO1 : Analog Output RTP0 to RTP7 : Real-Time Output Port ASCK : Asynchronous Serial Clock RxD : Receive Data ASTB : Address Strobe SB0, SB1 : Serial Bus AVDD : Analog Power Supply SCK0 to SCK2 : Serial Clock AVREF0, 1 : Analog Reference Voltage SCL : Serial
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CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES) (2) PROM programming mode 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) µPD78P058FYGC-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
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CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES) 2.6 78K/0 Series Expansion The 78K/0 Series expansion is shown below. The names in frames are subseries. Products in mass production Products under development Y subseries products are compatible with I2C bus.
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CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES) The differences between the major functions of each subseries are shown below. Function Subseries Control µPD78078Y µPD78070AY ROM Capacity 48 K to 60 K — µPD780018AY 48 K to 60 K µPD780058Y 24 K to 60 K µPD78058FY 48 K to 60 K µPD78054Y 16 K to 60 K µPD780034Y 8 K to 32 K µPD780024Y µPD78018FY µPD78014Y LCD 8 K to 60 K 8 K to 32 K 54 88 1.8 V 3-wire with automatic send/receive function. : 1 ch 61 2.
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CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES) 2.
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CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES) 2.8 Outline of Function Part Number µPD78056FY Item Internal memory ROM µPD78058FY Mask ROM PROM 48 Kbytes High-speed RAM 1024 bytes Buffer RAM 32 bytes Expansion RAM None Memory space µPD78P058FY 60 Kbytes 60 KbytesNote 1 1024 bytesNote 1 1024 bytes 1024 bytesNote 2 64 Kbytes General register 8 bits × 8 × 4 banks Minimum With main system clock selected instruction execution With subsystem clock selected time 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.
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CHAPTER 2 OUTLINE (µPD78058FY SUBSERIES) Part Number µPD78056FY Item Vectored Maskable µPD78P058FY Internal: 13 interrupt sources µPD78058FY External: 7 Non-maskable Internal: 1 Software 1 Test input Internal: 1 External: 1 Supply voltage VDD = 2.7 to 6.0 V Operating ambient temperature TA = –40 to +85°C Package • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
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CHAPTER 2 2.10 OUTLINE (µPD78058FY SUBSERIES) Mask Options The mask ROM versions (µPD78056FY, 78058FY) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for the device production. Using this mask option when pull-up resistors are required reduces the number of components to add to the device, resulting in board space saving.
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CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES) 3.1 Pin Function List 3.1.1 Normal operating mode pins (1) Port pins (1/3) Pin Name Input/Output Function After Reset Alternate Function P00 Input Port 0. Input only Input INTP0/TI00 P01 Input/ 8-bit input/output port. Input/output mode can be specified Input INTP1/TI01 P02 output bit-wise. INTP2 P03 If used as an input port, an on-chip INTP3 P04 pull-up resistor can be used by INTP4 P05 software.
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CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES) (1) Port pins (2/3) Pin Name Input/Output Function After Reset Alternate Function P30 Input/ Port 3. Input TO0 P31 output 8-bit input/output port. TO1 P32 Input/output mode can be specified bit-wise. TO2 P33 If used as an input port, an on-chip pull-up resistor can be used by TI1 P34 software. TI2 P35 PCL P36 BUZ P37 — P40 to P47 Input/ Port 4. output 8-bit input/output port.
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CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES) (1) Port pins (3/3) Pin Name Input/Output P120 to P127 Function Input/ Port 12. output 8-bit input/output port. After Reset Alternate Function Input RTP0 to RTP7 Input ANO0 to ANO1 Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be used by software. P130, P131 Input/ Port 13. output 2-bit input/output port. Input/output mode can be specified bit-wise.
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CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES) (2) Non-port pins (1/2) Pin Name Input/Output INTP0 Input INTP1 Function External interrupt request inputs with specifiable valid edges (rising After Reset Alternate Function Input edge, falling edge, both rising and falling edges).
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CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES) (2) Non-port pins (2/2) Pin Name Input/Output Function AD0 to AD7 Input/Output Low-order address/data bus when expanding external memory After Reset Alternate Function Input P40 to P47 A8 to A15 Output High-order address bus when expanding external memory Input P50 to P57 RD Output Strobe signal output for read operation from external memory Input P64 WR Strobe signal output for write operation to external memory WAIT Input ASTB Output P65
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CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES) 3.1.2 PROM programming mode pins (PROM versions only) Pin Name Input/Output RESET Input Function PROM programming mode setting. When +5 V or +12.5 V is applied to the VPP pin or a low level voltage is applied to the RESET pin, the PROM programming mode is set. VPP Input High-voltage application for PROM programming mode setting and program write/verify.
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CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES) 3.2 Description of Pin Functions 3.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem oscillation. The following operating modes can be specified bit-wise.
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CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES) 3.2.2 P10 to P17 (Port 1) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with a port mode register 1 (PM1).
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CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES) (d) BUSY Serial interface automatic transmit/receive busy input pins (e) STB Serial interface automatic transmit/receive strobe output pins Caution When this port is used as a serial interface pin, the I/O and output latches must be set according to the function the user requires. For the setting, refer to Figure 16-4 “Serial Operating Mode Register 0 Format” and Figure 18-3 “Serial Operating Mode Register 1 Format.” 3.2.
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CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES) 3.2.5 P40 to P47 (Port 4) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address/data bus. The test input flag (KRIF) can be set to 1 by detecting a falling edge. The following operating mode can be specified in 8-bit units. (1) Port mode These ports function as 8-bit input/output ports. They can be specified in 8-bit units for input or output ports by using the memory expansion mode register (MM).
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CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES) (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 6 (PM6). P60 to P63 are N-ch open drain outputs. Mask ROM version can contain pull-up resistors with the mask option. When P64 to P67 are used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor option register L (PUOL).
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CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES) 3.2.9 P120 to P127 (Port 12) These are 8-bit input/output ports. Besides serving as input/output ports, they function as a real-time output port. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 12 (PM12).
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CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES) 3.2.13 AVDD This is the analog power supply pin of the A/D converter and the port’s power supply pin. Always use the same voltage as that of the VDD pin even when the A/D converter is not used. 3.2.14 AVSS This is the ground potential pin for the A/D converter and D/A converter, and the ground potential pin for the port. Even when the A/D converter and D/A converter are not used, always use the same potential as that of the VSS pin. 3.2.
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CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES) 3.2.21 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the µPD78058F Subseries at delivery. Connect it directly to the VSS with the shortest possible wire in the normal operating mode. When a voltage difference is produced between the IC pin and VSS pin because the wiring between those two pins is too long or an external noise is input to the IC pin, the user's program may not run normally.
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CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES) 3.3 Input/output Circuits and Recommended Connection of Unused Pins Table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 3-1 for the configuration of the input/output circuit of each type. Table 3-1.
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CHAPTER 3 PIN FUNCTION (µPD78058F SUBSERIES) Table 3-1. Pin Input/Output Circuit Types (2/2) Pin Name Input/Output Circuit Type Input/Output Recommended Connection of Unused Pins P60 to P63 (Mask ROM version) 13-I Input/output Connect independently via a resistor to VDD. P60 to P63 (PROM version) 13-H P64/RD 5-D Input/output Connect independently via a resistor to VDD or VSS. Input/output Connect independently via a resistor to VSS.
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PIN FUNCTION (µPD78058F SUBSERIES) CHAPTER 3 Figure 3-1.
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PIN FUNCTION (µPD78058F SUBSERIES) CHAPTER 3 Figure 3-1.
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CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) 4.1 Pin Function List 4.1.1 Normal operating mode pins (1) Port pins (1/3) Pin Name Input/Output Function After Reset Alternate Function P00 Input Port 0. Input only Input INTP0/TI00 P01 Input/ 8-bit input/output port. Input/output mode can be specified Input INTP1/TI01 P02 output bit-wise. INTP2 P03 If used as an input port, an on-chip INTP3 P04 pull-up resistor can be used by INTP4 P05 software.
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CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) (1) Port pins (2/3) Pin Name Input/Output Function After Reset Alternate Function P30 Input/ Port 3. Input TO0 P31 output 8-bit input/output port. TO1 P32 Input/output mode can be specified bit-wise. TO2 P33 If used as an input port, an on-chip pull-up resistor can be used by TI1 P34 software. TI2 P35 PCL P36 BUZ P37 — P40 to P47 Input/ Port 4. output 8-bit input/output port.
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CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) (1) Port pins (3/3) Pin Name Input/Output P120 to P127 Function Input/ Port 12. output 8-bit input/output port. After Reset Alternate Function Input RTP0 to RTP7 Input ANO0 to ANO1 Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be used by software. P130 to P131 Input/ Port 13. output 2-bit input/output port. Input/output mode can be specified bit-wise.
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CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) (2) Non-port pins (1/2) Pin Name Input/Output INTP0 Input INTP1 Function External interrupt request inputs with specifiable valid edges (rising After Reset Alternate Function Input edge, falling edge, both rising and falling edges).
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CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) (2) Non-port pins (2/2) Pin Name Input/Output Function AD0 to AD7 Input/Output Low-order address/data bus when expanding external memory After Reset Alternate Function Input P40 to P47 A8 to A15 Output High-order address bus when expanding external memory Input P50 to P57 RD Output Strobe signal output for read operation from external memory Input P64 WR Strobe signal output for write operation to external memory WAIT Input ASTB Output P65
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CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) 4.1.2 PROM programming mode pins (PROM versions only) Pin Name Input/Output RESET Input Function PROM programming mode setting. When +5 V or +12.5 V is applied to the VPP pin or a low level voltage is applied to the RESET pin, the PROM programming mode is set. VPP Input High-voltage application for PROM programming mode setting and program write/verify.
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CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) 4.2 Description of Pin Functions 4.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem oscillation. The following operating modes can be specified bit-wise.
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CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) 4.2.2 P10 to P17 (Port 1) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with a port mode register 1 (PM1).
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CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) 4.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output, and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 3 (PM3).
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CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) 4.2.5 P40 to P47 (Port 4) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address/data bus. The test input flag (KRIF) can be set to 1 by detecting a falling edge. The following operating mode can be specified in 8-bit units. (1) Port mode These ports function as 8-bit input/output ports. They can be specified in 8-bit units for input or output ports by using the memory expansion mode register (MM).
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CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) 4.2.8 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified bit-wise. (1) Port mode Port 7 functions as a 3-bit input/output port. Bit-wise specification as an input port or output port is possible by means of port mode register 7 (PM7).
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CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) 4.2.9 P120 to P127 (Port 12) These are 8-bit input/output ports. Besides serving as input/output ports, they function as a real-time output port. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 12 (PM12).
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CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) 4.2.13 AVDD This is the analog power supply pin of the A/D converter and the port’s power supply pin. Always use the same voltage as that of the V DD pin even when the A/D converter is not used. 4.2.14 AVSS This is the ground potential pin for the A/D converter and D/A converter, and the ground potential pin for the port. Even when the A/D converter and D/A converter are not used, always use the same potential as that of the VSS pin. 4.2.
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CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) 4.2.21 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the µPD78058FY Subseries at delivery. Connect it directly to the VSS with the shortest possible wire in the normal operating mode. When a voltage difference is produced between the IC pin and VSS pin because the wiring between those two pins is too long or an external noise is input to the IC pin, the user's program may not run normally.
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CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) 4.3 Input/output Circuits and Recommended Connection of Unused Pins Table 4-1 shows the input/output circuit types of pins and the recommended connection for unused pins. Refer to Figure 4-1 for the configuration of the input/output circuit of each type. Table 4-1. Pin Input/Output Circuit Types (1/2) Pin Name Input/Output Circuit Type Input/Output Recommended Connection of Unused Pins Input Connect to VSS.
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CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) Table 4-1. Pin Input/Output Circuit Types (2/2) Pin Name Input/Output Circuit Type Input/Output Recommended Connection of Unused Pins P60 to P63 (Mask ROM version) 13-I Input/output Connect independently via a resistor to VDD. P60 to P63 (PROM version) 13-H Input/output Connect independently via a resistor to VDD or VSS. P64/RD 5-D Input/output Connect independently via a resistor to VSS.
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CHAPTER 4 PIN FUNCTION (µPD78058FY SUBSERIES) Figure 4-1.
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PIN FUNCTION (µPD78058FY SUBSERIES) CHAPTER 4 Figure 4-1.
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CHAPTER 5 CPU ARCHITECTURE 5.1 Memory Spaces 64-Kbyte memory spaces can be accessed in the µPD78058F, 78058FY Subseries. Figures 5-1 to 5-3 show memory maps. Figure 5-1.
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CHAPTER 5 CPU ARCHITECTURE Figure 5-2.
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CHAPTER 5 CPU ARCHITECTURE Figure 5-3.
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CHAPTER 5 CPU ARCHITECTURE 5.1.1 Internal program memory space The µPD78056F and µPD78056FY are Mask ROM with a 49152 x 8 bit configuration, the µPD78058F and µPD78058FY are Mask ROM with a 61440 x 8 bit configuration and the µPD78P058F and µPD78P058FY are PROM with a 61440 x 8 bit configuration. They store program and table data, etc. Normally, they are addressed by the program counter (PC). The areas shown below are allocated to the internal program memory space.
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CHAPTER 5 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). 5.1.2 Internal data memory space The µPD78058F and 78058FY Subseries units incorporate the following RAMs. (1) Internal high-speed RAM This RAM has a 1024 x 8 bit configuration.
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CHAPTER 5 CPU ARCHITECTURE 5.1.5 Data memory addressing The method to specify the address of the instruction to be executed next, or the address of a register or memory to be manipulated when an instruction is executed is called addressing. The address of the instruction to be executed next is addressed by the program counter PC (for details, refer to Section 5.3 Instruction Address Addressing).
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CHAPTER 5 CPU ARCHITECTURE Figure 5-5.
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CHAPTER 5 CPU ARCHITECTURE Figure 5-6.
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CHAPTER 5 CPU ARCHITECTURE 5.2 Processor Registers The µPD78058F and 78058FY Subseries units incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
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CHAPTER 5 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When IE = 0, all interrupts except non-maskable interrupt requests are disabled (DI status). When IE = 1, interrupts are enabled (EI status). At this time, acknowledgment of interrupts is controlled with an inservice priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specify flag.
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CHAPTER 5 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area (FB00H to FEFFH) can be set as the stack area. Figure 5-9. Stack Pointer Format 15 SP 0 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory.
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CHAPTER 5 CPU ARCHITECTURE 5.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H). Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE and HL).
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CHAPTER 5 CPU ARCHITECTURE Figure 5-12.
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CHAPTER 5 CPU ARCHITECTURE 5.2.3 Special Function Register (SFR) Unlike a general register, each special-function register has special functions. It is allocated in the FF00H to FFFFH area. The special-function register can be manipulated like the general register, with the operation, transfer and bit manipulation instructions. Manipulatable bit units, 1, 8 and 16, depend on the special-function register type. Each manipulation bit unit can be specified as follows.
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CHAPTER 5 CPU ARCHITECTURE Table 5-3.
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CHAPTER 5 CPU ARCHITECTURE Table 5-3.
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CHAPTER 5 CPU ARCHITECTURE Table 5-3.
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CHAPTER 5 CPU ARCHITECTURE 5.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The contents of PC are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing.
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CHAPTER 5 CPU ARCHITECTURE 5.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. The CALL !addr16 and BR !addr16 instruction can branch in the entire memory space. The CALLF !addr11 instruction branches to an area of addresses 0800H through 0FFFH.
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CHAPTER 5 CPU ARCHITECTURE 5.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. Before the CALLT [addr5] instruction is executed, table indirect addressing is performed. This instruction references an address stored in the memory table at addresses 40H through 7FH, and can branch in the entire memory space.
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CHAPTER 5 CPU ARCHITECTURE 5.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed.
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CHAPTER 5 CPU ARCHITECTURE 5.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically (illicitly) addressed. Of the µPD78058F and 78058FY Subseries instruction words, the following instructions employ implied addressing.
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CHAPTER 5 CPU ARCHITECTURE 5.4.2 Register addressing [Function] This addressing accesses a general register as an operand. The general register accessed is specified by the register bank select flags (RBS0 and RBS1) and register specify code (Rn or RPn) in an instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
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CHAPTER 5 CPU ARCHITECTURE 5.4.3 Direct addressing [Function] This addressing directly addresses the memory indicated by the immediate data in an instruction word.
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CHAPTER 5 CPU ARCHITECTURE 5.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this address is applied is a 256-byte space of addresses FE20H through FF1FH. An internal RAM and a special-function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H through FF1FH) to which short direct addressing is applied is a part of the entire SFR area.
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CHAPTER 5 CPU ARCHITECTURE [Description example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H Operation code 0 0 0 1 0 0 0 1 OP code 0 0 1 1 0 0 0 0 30H (saddr-offset) 0 1 0 1 0 0 0 0 50H (immediate data) [Illustration] 7 0 OP code saddr-offset Short Direct Memory 15 Effective Address 1 8 7 1 1 1 1 1 1 α When 8-bit immediate data is 20H to FFH, α = 0 When 8-bit immediate data is 00H to 1FH, α = 1 120 0
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CHAPTER 5 CPU ARCHITECTURE 5.4.5 Special-Function Register (SFR) addressing [Function] The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.
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CHAPTER 5 CPU ARCHITECTURE 5.4.6 Register indirect addressing [Function] This addressing addresses the memory with the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register bank select flags (RBS0 and RBS1) and register pair specify code in an instruction code. This addressing can be carried out for all the memory spaces.
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CHAPTER 5 CPU ARCHITECTURE 5.4.7 Based addressing [Function] This addressing addresses the memory by adding 8-bit immediate data to the contents of the HL register pair which is used as a base register and by using the result of the addition. The HL register pair to be accessed is in the register bank specified by the register bank select flags (RBS0 and RBS1). The offset data is first expanded as a positive number to 16 bits and then added. A carry from the 16th bit is ignored.
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CHAPTER 5 CPU ARCHITECTURE 5.4.8 Based indexed addressing [Function] This addressing addresses the memory by adding the contents of the HL register, which is used as a base register, to the contents of the B or C register specified in the instruction word, and by using the result of the addition. The HL, B, and C registers to be accessed are registers in the register bank specified by the register bank select flags (RBS0 and RBS1).
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CHAPTER 6 PORT FUNCTIONS 6.1 Port Functions The µPD78058F and 78058FY Subseries units incorporate two input ports and sixty-seven input/output ports. Figure 6-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. Besides port functions, the ports can also serve as on-chip hardware input/ output pins. Figure 6-1.
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CHAPTER 6 PORT FUNCTIONS Table 6-1. Port Functions (µPD78058F Subseries) (1/2) Pin Name Function Alternate Function P00 Port 0. Input only INTP0/TI00 P01 8-bit input/output port. Input/output mode can be specified INTP1/TI01 P02 bit-wise. INTP2 P03 If used as an input port, an on-chip pull-up INTP3 P04 resistor can be used by software. INTP4 P05 INTP5 P06 INTP6 P07 P10 to P17 Input only Port 1. XT1 ANI0 to ANI7 8-bit input/output port.
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CHAPTER 6 PORT FUNCTIONS Table 6-1. Port Functions (µPD78058F Subseries) (2/2) Pin Name Function P60 Port 6. N-ch open-drain input/output port. P61 8-bit input/output port. On-chip pull-up resistor can be specified by P62 Input/output mode can be specified mask option. (Mask ROM version only). P63 bit-wise. LEDs can be driven directly. Alternate Function — P64 If used as an input port, an on-chip pull-up RD P65 resistor can be used by software. WR P66 WAIT P67 ASTB P70 Port 7.
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CHAPTER 6 PORT FUNCTIONS Table 6-2. Port Functions (µPD78058FY Subseries) (1/2) Pin Name Function Alternate Function P00 Port 0. Input only INTP0/TI00 P01 8-bit input/output port. Input/output mode can be specified INTP1/TI01 P02 bit-wise. INTP2 P03 If used as an input port, an on-chip pull-up INTP3 P04 resistor can be used by software. INTP4 P05 INTP5 P06 INTP6 P07 P10 to P17 Input only Port 1. XT1 ANI0 to ANI7 8-bit input/output port.
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CHAPTER 6 PORT FUNCTIONS Table 6-2. Port Functions (µPD78058FY Subseries) (2/2) Pin Name Function P60 Port 6. N-ch open drain input/output port. P61 8-bit input/output port. On-chip pull-up resistor can be specified by P62 Input/output mode can be specified mask option. (Mask ROM version only). P63 bit-wise. LEDs can be driven directly. Alternate Function — P64 If used as an input port, an on-chip pull-up RD P65 resistor can be used by software. WR P66 WAIT P67 ASTB P70 Port 7.
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CHAPTER 6 PORT FUNCTIONS 6.2 Port Configuration A port consists of the following hardware: Table 6-3.
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CHAPTER 6 PORT FUNCTIONS Figure 6-2. P00 and P07 Block Diagram Internal bus RD P00/INTP0/TI00, P07/XT1 Figure 6-3. P01 to P06 Block Diagram AVDD WRPUO PUO0 P-ch RD Internal bus Selector WRPORT Output Latch (P01 to P06) P01/INTP1/TI01.
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CHAPTER 6 PORT FUNCTIONS 6.2.2 Port 1 Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit units with a port mode register 1 (PM1). When P10 to P17 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL). Alternate function includes an A/D converter analog input. RESET input sets port 1 to input mode. Figure 6-4 shows a block diagram of port 1.
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CHAPTER 6 PORT FUNCTIONS 6.2.3 Port 2 (µPD78058F Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2). When P20 to P27 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).
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CHAPTER 6 PORT FUNCTIONS Figure 6-6.
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CHAPTER 6 PORT FUNCTIONS 6.2.4 Port 2 (µPD78058FY Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2). When P20 to P27 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).
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CHAPTER 6 PORT FUNCTIONS Figure 6-8.
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CHAPTER 6 PORT FUNCTIONS 6.2.5 Port 3 Port 3 is an 8-bit input/output port with output latch. P30 to P37 pins can specify the input mode/output mode in 1-bit units with the port mode register 3 (PM3). When P30 to P37 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL). Alternate functions include timer input/output, clock output, and buzzer output. RESET input sets port 3 to input mode.
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CHAPTER 6 PORT FUNCTIONS 6.2.6 Port 4 Port 4 is an 8-bit input/output port with output latch. P40 to P47 pins can specify the input mode/output mode in 8-bit units with the memory expansion mode register (MM). When P40 to P47 pins are used as input ports, an onchip pull-up resistor can be used to them in 8-bit units with pull-up resistor option register L (PUOL). The test input flag (KRIF) can be set to 1 by detecting falling edges.
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CHAPTER 6 PORT FUNCTIONS 6.2.7 Port 5 Port 5 is an 8-bit input/output port with output latch. P50 to P57 pins can specify the input mode/output mode in 1-bit units with the port mode register 5 (PM5). When P50 to P57 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL). Port 5 can drive LEDs directly. Alternate function includes address bus function in external memory expansion mode.
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CHAPTER 6 PORT FUNCTIONS 6.2.8 Port 6 Port 6 is an 8-bit input/output port with output latch. P60 to P67 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (PM6). This port has functions related to pull-up resistors as shown below. These functions depending on whether the higher 4 bits or lower 4 bits of a port are used, and whether the mask ROM model or PROM model is used. Table 6-4.
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CHAPTER 6 PORT FUNCTIONS Figure 6-13. P60 to P63 Block Diagram AVDD RD Internal bus Selector Mask Option Resistor Mask ROM products only. PROM versions have no pull-up resistor. WRPORT Output Latch (P60 to P63) P60 to P63 WRPM PM60 to PM63 PM : Port mode register RD : Port 6 read signal WR : Port 6 write signal Figure 6-14.
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CHAPTER 6 PORT FUNCTIONS 6.2.9 Port 7 This is a 3-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 7 (PM7). When pins P70 to P72 are used as input port pins, an on-chip pull-up resistor can be used as a 3-bit unit by means of pull-up resistor option register L (PUOL). Alternate functions include serial interface channel 2 data input/output and clock input/output. RESET input sets the input mode.
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CHAPTER 6 PORT FUNCTIONS Figure 6-16.
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CHAPTER 6 PORT FUNCTIONS 6.2.10 Port 12 This is an 8-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 12 (PM12). When pins P120 to P127 are used as input port pins, an on-chip pull-up resistor can be used as an 8-bit unit by means of pull-up resistor option register H (PUOH). Alternate function includes real-time output. RESET input sets the input mode. Figure 6-17 shows a block diagram of port 12. Figure 6-17.
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CHAPTER 6 PORT FUNCTIONS 6.2.11 Port 13 This is a 2-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 13 (PM13). When pins P130 and P131 are used as input port pins, an on-chip pull-up resistor can be used as a 2-bit unit by means of pull-up resistor option register H (PUOH). Alternate function includes D/A converter analog output. RESET input sets the input mode. Figure 6-18 shows a block diagram of port 13.
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CHAPTER 6 PORT FUNCTIONS 6.3 Port Function Control Registers The following four types of registers control the ports. • Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13) • Pull-up resistor option register (PUOH, PUOL) • Memory expansion mode register (MM) • Key return mode register (KRM) (1) Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13) These registers are used to set port input/output in 1-bit units.
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CHAPTER 6 PORT FUNCTIONS Table 6-5.
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CHAPTER 6 PORT FUNCTIONS Figure 6-19.
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CHAPTER 6 PORT FUNCTIONS (2) Pull-up resistor option register (PUOH, PUOL) This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has been specified with PUOH, PUOL. No on-chip pull-up resistors can be used to the bits set to the output mode or to the bits used as an analog input pin, irrespective of PUOH or PUOL setting.
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CHAPTER 6 PORT FUNCTIONS (3) Memory expansion mode register (MM) This register is used to set input/output of port 4. MM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 10H. Figure 6-21.
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CHAPTER 6 PORT FUNCTIONS (4) Key return mode register (KRM) This register sets enabling/disabling of standby function release by a key return signal (falling edge detection of port 4). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H. Figure 6-22.
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CHAPTER 6 PORT FUNCTIONS 6.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again.
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CHAPTER 6 PORT FUNCTIONS 6.4.3 Operations on input/output port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode The output latch contents are undefined, but since the output buffer is OFF, the pin status does not change.
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[MEMO] 154
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CHAPTER 7 CLOCK GENERATOR 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC). (2) Subsystem clock oscillator The circuit oscillates at a frequency of 32.768 kHz.
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CHAPTER 7 CLOCK GENERATOR Figure 7-1.
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CHAPTER 7 CLOCK GENERATOR 7.3 Clock Generator Control Register The clock generator is controlled by the following two registers: • Processor clock control register (PCC) • Oscillation mode selection register (OSMS) (1) Processor clock control register (PCC) The PCC sets whether to use CPU clock selection, the ratio of division, main system clock oscillator operation/ stop and subsystem clock oscillator internal feedback resistor. The PCC is set with a 1-bit or 8-bit memory manipulation instruction.
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CHAPTER 7 CLOCK GENERATOR Figure 7-3.
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CHAPTER 7 CLOCK GENERATOR The fastest instruction of the µPD78075F and 78075FY Subseries can be executed in two clocks of the CPU clock. The relationship between the CPU clock (fCPU) and the minimum instruction execution time is shown in Table 7-2. Table 7-2. Relationship Between CPU Clock and Minimum Instruction Execution Time CPU Clock (fCPU) Minimum Instruction Execution Time: 2/fCPU fX 0.4 µs fX/2 0.8 µs fX/22 1.6 µs fX/23 3.2 µs fX/24 6.4 µs fX/25 12.8 µs fXT/2 122 µs fX = 5.
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CHAPTER 7 CLOCK GENERATOR Figure 7-5. Main System Clock Waveform due to Writing to OSMS Write to OSMS (MCS 0) Max. 2/fX fXX Operating at fXX = fX/2 (MCS = 0) Caution 2. When writing “1” to MCS, VDD must be 2.7 V or higher before the write execution.
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CHAPTER 7 CLOCK GENERATOR 7.4 System Clock Oscillator 7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and an antiphase clock signal to the X2 pin. Figure 7-6 shows an external circuit of the main system clock oscillator. Figure 7-6.
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CHAPTER 7 CLOCK GENERATOR 7.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the XT1 pin and an antiphase clock signal to the XT2 pin. Figure 7-7 shows an external circuit of the subsystem clock oscillator. Figure 7-7.
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CHAPTER 7 CLOCK GENERATOR Figure 7-8. Examples of Resonator with Incorrect Connection (2/2) (c) Changing high current is too near a signal line (d) Current flows through the grounding line of the resonator (potential at points A, B, and C fluctuate) AV DD Pnm X2 X1 IC High Current X2 A X1 B IC C High Current (e) Signals are fetched X2 Remark X1 IC When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side.
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CHAPTER 7 CLOCK GENERATOR 7.4.3 Scaler The scaler divides the main system clock oscillator output (fXX) and generates various clocks. 7.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the XT1 and XT2 pins as follows. XT1 : Connect to VDD XT2 : Leave open In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops.
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CHAPTER 7 CLOCK GENERATOR 7.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock • Subsystem clock • CPU clock fXX fXT fCPU • Clock to peripheral hardware The following clock generator functions and operations are determined with the processor clock control register (PCC) and the oscillation mode selection register (OSMS).
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CHAPTER 7 CLOCK GENERATOR 7.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of the PCC.
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CHAPTER 7 CLOCK GENERATOR Figure 7-9. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation MCC CSS CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock 7.5.2 Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out.
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Table 7-3.
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CHAPTER 7 CLOCK GENERATOR 7.6.2 System clock and CPU clock switching procedure This section describes switching procedure between system clock and CPU clock. Figure 7-10. System Clock and CPU Clock Switching VDD RESET Interrupt Request Signal fXX System Clock CPU Clock fXX Minimum Maximum Speed Operation Speed Operation Wait (26.2 ms : 5.
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[MEMO] 170
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.1 Overview of the µPD78058F and 78058FY Subseries On-Chip Timers This chapter describes the 16-bit timer/event counter and begins with an overview of the on-chip timers and related devices of the µPD78058F and 78058FY Subseries.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-1.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.2 16-Bit Timer/Event Counter Functions The 16-bit timer/event counter (TM0) has the following functions. • Interval timer • PWM output • Pulse width measurement • External event counter • Square-wave output • One-shot pulse output PWM output and pulse width measurement can be used at the same time. (1) Interval timer TM0 generates interrupts request at the preset time interval. Table 8-2.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Square-wave output TM0 can output a square wave with any selected frequency. Table 8-3. 16-Bit Timer/Event Counter Square-Wave Output Ranges Minimum Pulse Width MCS = 1 Maximum Pulse Width MCS = 0 MCS = 1 2 × TI00 input cycle 216 MCS = 0 × TI00 input cycle 2 × 1/fX — 2 × 1/fX 22 (400 ns) (800 ns) 22 × 1/fX (800 ns) 23 × 1/fX (1.6 µs) 216 — (400 ns) 23 × 1/fX × 1/fX (1.6 µs) 24 × 1/fX (3.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-1.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-2.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (1) Capture/compare register 00 (CR00) CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control register 0. When CR00 is used as a compare register, the value set in CR00 is constantly compared with the 16-bit timer register (TM0) count value, and an interrupt request (INTTM00) is generated if they match.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Caution If the valid edge of the TIO0/P00 pin is input while CR01 is read, CR01 does not perform the capture operation and retains the current data. However, the interrupt request flag (PIF0) is set. (3) 16-bit timer register (TM0) TM0 is a 16-bit register which counts the count pulses. TM0 is read by a 16-bit memory manipulation instruction. When TM0 is read, capture/compare register (CR01) should first be set as a capture register. RESET input sets TM0 to 0000H.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-3. Timer Clock Selection Register 0 Format Symbol 7 6 5 4 3 2 1 0 TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 Address After Reset R/W FF40H 00H R/W PCL Output Clock Selection TCL03 TCL02 TCL01 TCL00 MCS = 1 MCS = 0 0 0 0 0 fXT (32.768 kHz) 0 1 0 1 fXX fX (5.0 MHz) fX/2 (2.5 MHz) 0 1 1 0 fXX/2 fX/2 (2.5 MHz) fX/2 (1.25 MHz) 0 1 1 1 fXX/2 2 fX/2 (1.
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CHAPTER 8 Remarks 1. fXX 16-BIT TIMER/EVENT COUNTER : Main system clock frequency (fX or fX/2) 2. fX : Main system clock oscillation frequency 3. fXT : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6. MCS : Bit 0 of oscillation mode selection register (OSMS) 7. Figures in parentheses apply to operation with fX = 5.0 MHz of fXT = 32.768 kHz.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-4.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Capture/compare control register 0 (CRC0) This register controls the operation of the capture/compare registers 00, 01 (CR00, CR01). CRC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CRC0 value to 04H. Figure 8-5.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-6.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P30/TO0 pin for timer output, set PM30 and output latch of P30 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 value to FFH. Figure 8-7.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (6) External interrupt mode register 0 (INTM0) This register is used to set INTP0 to INTP2 valid edges. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 value to 00H. Figure 8-8.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Sampling clock select register (SCS) This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote controlled reception is carried out using INTP0, digital noise is removed with sampling clock. SCS is set with an 8-bit memory manipulation instruction. RESET input sets SCS value to 00H. Figure 8-9.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5 16-Bit Timer/Event Counter Operations 8.5.1 Interval timer operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-10 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value set in 16-bit capture/compare register 00 (CR00) beforehand as the interval.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-11. Interval Timer Configuration Diagram 16-Bit Capture/Compare Register 00 (CR00) INTTM00 INTTM3 Selector 2fXX fXX fXX/2 2 fXX/2 TI00/P00/INTP0 OVF0 16-Bit Timer Register (TM0) Clear Circuit Figure 8-12.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-6. 16-Bit Timer/Event Counter Interval Times TCL06 TCL05 TCL04 0 0 0 0 0 1 Minimum Interval Time MCS = 1 MCS = 0 Maximum Interval Time MCS = 1 2 × TI00 input cycle MCS = 0 Resolution MCS = 1 216 × TI00 input cycle MCS = 0 TI00 input edge cycle Setting 2 × 1/fX Setting 216 × 1/fX Setting 1/fX prohibited (400 ns) prohibited (13.1 ms) prohibited (200 ns) 216 217 0 1 0 2 × 1/fX (400 ns) 22 × 1/fX (800 ns) × 1/fX (13.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-13. Control Register Settings for PWM Output Operation (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 0 0 1 0 PWM mode (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0/1 0/1 0 CR00 set as compare register (c) 16-bit timer output control register (TOC0) OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 TOC0 0 × × × × × 0/1 1 TO0 Output Enabled Specifies Active Level Remarks 1.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and D/A converter applications, etc. The analog output voltage (VAN) used for D/A conversion with the configuration shown in Figure 8-14 is as follows. VAN = VREF × capture/compare register 00 (CR00) value 216 VREF: External switching circuit reference voltage Figure 8-14.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.3 PPG output operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-16 allows operation as PPG (Programmable Pulse Generator) output.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.4 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00/P00 pin and TI01/P01 pin using the 16-bit timer register (TM0). There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00/P00 pin.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-18. Configuration Diagram for Pulse Width Measurement by Free-Running Counter INTTM3 Selector 2fXX fXX fXX/2 fXX/2 16-Bit Timer Register (TM0) OVF0 2 16-Bit Capture/Compare Register 01 (CR01) TI00/P00/INTP00 INTP0 Internal Bus Figure 8-19.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) Measurement of two pulse widths with free-running counter When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-20), it is possible to simultaneously measure the pulse widths of the two signals input to the TI00/P00 pin and the TI01/P01 pin.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-21.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Pulse width measurement with free-running counter and two capture registers When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-22), it is possible to measure the pulse width of the signal input to the TI00/P00 pin.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-23.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Pulse width measurement by means of restart When input of a valid edge to the TI00/P00 pin is detected, the count value of the 16-bit timer register (TM0) is taken into 16-bit capture/compare register 01 (CR01), and then the pulse width of the signal input to the TI00/P00 pin is measured by clearing TM0 and restarting the count (see register settings in Figure 8-24).
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.5 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI00/P00 pin with the 16-bit timer register (TM0). TM0 is incremented each time the valid edge specified with the external interrupt mode register 0 (INTM0) is input. When the TM0 counted value matches the 16-bit capture/compare register 00 (CR00) value, TM0 is cleared to 0 and the interrupt request signal (INTTM00) is generated.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-27. External Event Counter Configuration Diagram 16-Bit Capture/Compare Register 00 (CR00) INTTM00 Clear OVF0 16-Bit Timer Register (TM0) TI00 Valid Edge INTP0 16-Bit Capture/Compare Register 01 (CR01) Internal Bus Figure 8-28.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.6 Square-wave output operation Operates as a square wave output at the desired frequency with the count value set previously in the 16 bit capture/ conveyor register 00 (CR00) as the interval. The TO0/P30 pin output status is reversed at intervals of the count value preset to CR00 by setting bit 0 (TOE0) and bit 1 (TOC01) of the 16-bit timer output control register (TOC0) to 1. This enables a square wave with any selected frequency to be output. Figure 8-29.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-30. Square-Wave Output Operation Timing Count Clock TM0 Count Value 0000 0001 CR00 0002 N-1 N 0000 0001 0002 N-1 N 0000 N INTTM00 TO0 Pin Output Table 8-7. 16-Bit Timer/Event Count Square-Wave Output Ranges Minimum Pulse Width MCS = 1 MCS = 0 Maximum Pulse Width MCS = 1 2 × TI00 input cycle 216 2 × 1/fX — 2 × 1/fX (400 ns) (800 ns) 22 × 1/fX 23 × 1/fX (1.6 µs) (800 ns) 23 × 1/fX × 1/fX 24 (1.6 µs) × 1/fX (3.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.7 One-shot pulse output operation It is possible to output one-shot pulses synchronized with a software trigger or an external trigger (TI00/P00 pin input).
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-32. Timing of One-Shot Pulse Output Operation Using Software Trigger Set 0CH to TMC0 (TM0 count start) Count Clock TM0 Count Value 0000 0001 N N+1 0000 N-1 N M-1 M 0000 0001 0002 CR01 Set Value N N N N CR00 Set Value M M M M OSPT INTTM01 INTTM00 TO0 Pin Output Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation stop mode) is set to TMC01 to TMC03, respectively.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) One-shot pulse output using external trigger If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit timer output control register (TOC0) are set as shown in Figure 8-33, a one-shot pulse is output from the TO0/ P30 pin with a TI00/P00 valid edge as an external trigger.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-34.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.6 16-Bit Timer/Event Counter Operating Precautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because the 16-bit timer register (TM0) is started asynchronously with the count pulse. Figure 8-35.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Capture register data retention timings If the valid edge of the TI00/P00 pin is input during 16-bit capture/compare register 01 (CR01) read, CR01 holds data without carrying out capture operation. However, the interrupt request flag (PIF0) is set upon detection of the valid edge. Figure 8-37.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Operation of OVF0 flag OFV0 flag is set to 1 in the following case. The clear & start mode on match between TM0 and CR00 is selected. ↓ CR00 is set to FFFFH. ↓ When TM0 is counted up from FFFFH to 0000H. Figure 8-38.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.1 8-Bit Timer/Event Counter Function The on-chip 8-bit timer/event counters of the µPD78058F, 78058FY Subseries have two modes: a mode in which the two 8-bit timer/event counter channels are separately used (8-bit timer/event counter mode), and a mode in which the two 8-bit timer/event counter channels are used combined as a 16-bit timer/event counter (16-bit timer/event counter mode). 9.1.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 9-1. 8-Bit Timer/Event Counter Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 2 × 1/fX 22 × 1/fX 29 × 1/fX 210 × 1/fX 2 × 1/fX 22 × 1/fX (400 ns) (800 ns) (102.4 µs) (204.8 µs) (400 ns) (800 ns) 22 × 1/fX 23 × 1/fX 210 × 1/fX 211 × 1/fX 22 × 1/fX 23 × 1/fX (800 ns) (1.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-2. 8-Bit Timer/Event Counter Square-Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 2 × 1/fX 22 × 1/fX 29 × 1/fX 210 × 1/fX 2 × 1/fX 22 × 1/fX (400 ns) (800 ns) (102.4 µs) (204.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.1.2 16-bit timer/event counter mode (1) 16-bit interval timer Interrupt requests can be generated at the preset time intervals. Table 9-3. Interval Times When 8-Bit Timer/Event Counters are Used as 16-Bit Timer/Event Counter Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 2 × 1/fX 22 × 1/fX 217 × 1/fX 218 × 1/fX 2 × 1/fX 22 × 1/fX (400 ns) (800 ns) (26.2 ms) (52.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-4.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.2 8-Bit Timer/Event Counter Configuration The 8-bit timer/event counters 1 and 2 consist of the following hardware. Table 9-5.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-1.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-2. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 Level F/F (LV1) LVR1 R LVS1 S Q TOC11 TO1/P31 P31 Output Latch INV PM31 INTTM1 TOE1 Remark The section in the broken line is an output control circuit. Figure 9-3. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 Level F/F (LV2) fSCK LVR2 R Q LVS2 TOC15 TO2/P32 S P32 Output Latch INV INTTM2 TOE2 Remarks 1.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (1) Compare registers 10 and 20 (CR10, CR20) These are 8-bit registers to compare the value set to CR10 to the 8-bit timer register 1 (TM1) count value, and the value set to CR20 to the 8-bit timer register 2 (TM2) count value, and, if they match, generate an interrupt request (INTTM1 and INTTM2, respectively). CR10 and CR20 are set with an 8-bit memory manipulation instruction. They cannot be set with a 16-bit memory manipulation instruction.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.3 8-Bit Timer/Event Counter Control Registers The following four types of registers are used to control the 8-bit timer/event counter. • Timer clock select register 1 (TCL1) • 8-bit timer mode control register 1 (TMC1) • 8-bit timer output control register (TOC1) • Port mode register 3 (PM3) (1) Timer clock select register 1 (TCL1) This register sets count clocks of 8-bit timer registers 1 and 2. TCL1 is set with an 8-bit memory manipulation instruction.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-4.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (2) 8-bit timer mode control register (TMC1) This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer register 1 and 2. TMC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC1 to 00H. Figure 9-5.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (3) 8-bit timer output control register (TOC1) This register controls operation of 8-bit timer/event counter output control circuits 1 and 2. It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of 8-bit timer registers 1 and 2. TOC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TOC1 to 00H. Figure 9-6.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (4) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P31/TO1 and P32/TO2 pins for timer output, set PM31, PM32, and output latches of P31 and P32 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 9-7.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.4 8-Bit Timer/Event Counter Operation 9.4.1 8-bit timer/event counter mode (1) Interval timer operations Operates as an interval timer which generates interrupt requests repeatedly with the count values set previously in the 8 bit conveyor registers 10 and 20 (CR10, CR20) as the interval.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Table 9-6.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Table 9-7.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (2) External event counter operation The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/ P34 pins with 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and TM2 are incremented each time the valid edge specified with the timer clock select register (TCL1) is input. Either the rising or falling edge can be selected.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (3) Operation as a Square Wave Output Operates as a square wave output at the desired frequency with the values set previously in the 8 bit conveyor registers 10 and 20 (CR10, CR20) as the interval. The TO1/P31 or TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 or CR20 by setting bit 0 (TOE1) or bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1. This enables a square wave with any selected frequency to be output.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-10. Square-Wave Output Operation Timing Count Clock TM1 Count Value 00 01 02 N–1 N 00 01 02 N–1 N 00 Count Start CR10 N TO1Note Note The initial value of TO1 output can be set with bits 2 and 3 (LVR1 and LVS1) of the 8-bit timer output control register (TOC1). 9.4.2 16-bit timer/event counter mode When bit 2 (TMC12) of the 8-bit timer mode control register (TMC1) is set to 1, the 16-bit timer/event counter mode is entered.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-11.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Table 9-9.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (2) External event counter operations The external event counter counts the number of external clock pulses to be input to the TI1/P33 pin with 2channel 8-bit timer registers 1 and 2 (TM1 and TM2). Each time TM1 overflows, the overflow signal is used as a counter clock and TM2 is incremented.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (3) Operation as a Square Wave Output Operates as a square wave output at the desired frequency with the values set previously in the 8 bit conveyor registers 10 and 20 (CR10, CR20) as the interval. When setting the count value, the value of the upper 8 bits is set in CR20 and the value of the lower 8 bits is set in CR10.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-13.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.5 Cautions on 8-Bit Timer/Event Counters (1) Timer start errors An error of one clock maximum may occur concerning the time required for a match signal to be generated after timer start. This is because the 8-bit timer registers 1 and 2 (TM1 and TM2) are started asynchronously with the count pulse. Figure 9-14.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers 10 and 20 (CR10 and CR20) are changed are smaller than those of 8-bit timer registers (TM1 and TM2), TM1 and TM2 continue counting, overflow and then restart counting from 0. Thus, if the value (M) after CR10 and CR20 change is smaller than value (N) before the change, it is necessary to restart the timer after changing CR10 and CR20. Figure 9-16.
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[MEMO] 238
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CHAPTER 10 WATCH TIMER 10.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. (1) Watch timer When the 32.768 kHz subsystem clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals. When the 4.19 MHz (standard: 4.194304 MHz) main system clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals. Caution 0.5-second intervals cannot be generated with the 5.
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CHAPTER 10 WATCH TIMER 10.2 Watch Timer Configuration The watch timer consists of the following hardware. Table 10-2. Watch Timer Configuration Item Counter Control register Configuration 5 bits × 1 Timer clock select register 2 (TCL2) Watch timer mode control register (TMC2) 10.3 Watch Timer Control Registers The following two types of registers are used to control the watch timer.
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CHAPTER 10 WATCH TIMER Figure 10-1.
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CHAPTER 10 WATCH TIMER Figure 10-2. Timer Clock Select Register 2 Format Symbol 7 6 5 4 3 TCL2 TCL27 TCL26 TCL25 TCL24 0 2 1 0 Address TCL22 TCL21 TCL20 FF42H After Reset 00H R/W R/W Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 MCS = 1 MCS = 0 0 0 0 f XX /2 3 f X /23 (625 kHz) f X /24 (313 kHz) 0 0 1 f XX /24 f X /24 (313 kHz) f X /25 (156 kHz) 0 1 0 f XX /25 f X /25 (156 kHz) f X /26 (78.1 kHz) 0 1 1 f XX /26 f X /26 (78.1 kHz) f X /27 (39.
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CHAPTER 10 WATCH TIMER (2) Watch timer mode control register (TMC2) This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/ disables prescaler and 5-bit counter operations. TMC2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC2 to 00H. Figure 10-3.
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CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation When the 32.768-kHz subsystem clock or 4.19-MHz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. The watch timer sets the test input flag (WTIF) to 1 at the constant time interval. The standby state (STOP mode/ HALT mode) can be cleared by setting WTIF to 1.
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CHAPTER 11 WATCHDOG TIMER 11.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM) (The watchdog timer and interval timer cannot be used at the same time). (1) Watchdog timer mode An inadvertent program loop (runaway) is detected. Upon detection of the runaway, a non-maskable interrupt request or RESET can be generated. Table 11-1.
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CHAPTER 11 WATCHDOG TIMER (2) Interval timer mode Interrupt requests are generated at the preset time intervals. Table 11-2. Interval Times Interval Time MCS = 1 CS = 0 211 × 1/fXX 211 × 1/fX (410 µs) 212 × 1/fX (819 µs) 212 × 1/fXX 212 × 1/fX (819 µs) 213 × 1/fX (1.64 ms) 213 × 1/fXX 213 × 1/fX (1.64 ms) 214 × 1/fX (3.28 ms) 214 × 1/fXX 214 × 1/fX (3.28 ms) 215 × 1/fX (6.55 ms) 215 × 1/fXX 215 × 1/fX (6.55 ms) 216 × 1/fX (13.1 ms) 216 × 1/fXX 216 × 1/fX (13.1 ms) 217 × 1/fX (26.
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CHAPTER 11 WATCHDOG TIMER 11.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 11-3. Watchdog Timer Configuration Item Configuration Timer clock select register 2 (TCL2) Control register Watchdog timer mode control register (WDTM) Figure 11-1.
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CHAPTER 11 WATCHDOG TIMER 11.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set with 8-bit memory manipulation instruction. RESET input sets TCL2 to 00H.
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CHAPTER 11 WATCHDOG TIMER Figure 11-2. Timer Clock Select Register 2 Format Symbol 7 5 6 4 3 TCL2 TCL27 TCL26 TCL25 TCL24 0 2 1 0 Address TCL22 TCL21 TCL20 FF42H After Reset 00H R/W R/W Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 MCS = 1 0 0 0 3 f XX /2 4 MCS = 0 3 f X /2 (625 kHz) 4 f X /2 4 (313 kHz) 5 (156 kHz) 0 0 1 f XX /2 f X /2 (313 kHz) f X /2 0 1 0 f XX /25 f X /25 (156 kHz) f X /26 (78.1 kHz) 0 1 1 f XX /26 f X /26 (78.1 kHz) f X /27 (39.
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CHAPTER 11 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 11-3.
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CHAPTER 11 WATCHDOG TIMER 11.4 Watchdog Timer Operations 11.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any runaway. The watchdog timer count clock (runaway detection time interval) can be selected with bits 0 to 2 (TCL20 to TCL22) of the timer clock select register 2 (TCL2). Watchdog timer starts by setting bit 7 (RUN) of WDTM to 1.
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CHAPTER 11 WATCHDOG TIMER 11.4.2 Interval timer operation The watchdog timer operates as an interval timer which generate interrupt request repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0. A count clock (interval time) can be selected by the bits 0 through 2 (TCL20 through TCL22) of the timer clock select register 2 (TCL2). By setting the bit 7 (RUN) of WDTM to 1, the watchdog timer starts operating as an interval timer.
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CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the timer clock select register 0 (TCL0) are output from the PCL/ P35 pin. Follow the procedure below to output clock pulses. (1) Select the clock pulse output frequency (with clock pulse output disabled) with bits 0 to 3 (TCL00 to TCL03) of TCL0.
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CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware. Table 12-1. Clock Output Control Circuit Configuration Item Configuration Timer clock select register 0 (TCL0) Control register Port mode register 3 (PM3) Figure 12-2.
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CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Figure 12-3. Timer Clock Select Register 0 Format Symbol 7 6 5 4 3 2 1 0 Address TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 FF40H After Reset 00H R/W R/W PCL Output Clock Selection TCL03 TCL02 TCL01 TCL00 MCS = 1 MCS = 0 0 0 0 0 f XT (32.768 kHz) 0 1 0 1 f XX fX 0 1 1 0 f XX /2 f X /2 (2.5 MHz) f X /22 (1.25 MHz) 0 1 1 1 f XX /22 f X /22 (1.
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CHAPTER 12 Remarks 1. fXX CLOCK OUTPUT CONTROL CIRCUIT : Main system clock frequency (fX or fX/2) 2. fX : Main system clock oscillation frequency 3. fXT : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6. MCS : Bit 0 of oscillation mode selection register (OSMS) 7. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz. (2) Port mode register 3 (PM3) This register set port 3 input/output in 1-bit units.
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CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.1 Buzzer Output Control Circuit Functions The buzzer output control circuit outputs 1.2 kHz, 2.4 kHz, 4.9 kHz, or 9.8 kHz frequency square waves. The buzzer frequency selected with timer clock select register 2 (TCL2) is output from the BUZ/P36 pin. Follow the procedure below to output the buzzer frequency. (1) Select the buzzer output frequency with bits 5 to 7 (TCL25 to TCL27) of TCL2. (2) Set the P36 output latch to 0.
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CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function. • Timer clock select register 2 (TCL2) • Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register sets the buzzer output frequency. TCL2 is set with an 8-bit memory manipulation instruction. RESET input sets TCL2 to 00H.
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CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT Figure 13-2. Timer Clock Select Register 2 Format Symbol 7 5 6 4 3 TCL2 TCL27 TCL26 TCL25 TCL24 0 2 1 0 Address TCL22 TCL21 TCL20 FF42H After Reset 00H R/W R/W Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 MCS = 1 MCS = 0 0 0 0 f XX /23 f X /23 (625 kHz) f X /24 (313 kHz) 0 0 1 f XX /24 f X /24 (313 kHz) f X /25 (156 kHz) 0 1 0 f XX /25 f X /25 (156 kHz) f X /26 (78.1 kHz) 0 1 1 f XX /26 f X /26 (78.
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CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT (2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P36/BUZ pin for buzzer output function, set PM36 and output latch of P36 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 13-3.
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CHAPTER 14 A/D CONVERTER 14.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D conversion result register (ADCR). The following two methods are used for starting an A/D conversion operation. (1) Hardware start Conversion is started by trigger input (INTP3).
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CHAPTER 14 A/D CONVERTER 14.2 A/D Converter Configuration The A/D converter consists of the following hardware. Table 14-1.
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CHAPTER 14 A/D CONVERTER Figure 14-1.
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CHAPTER 14 A/D CONVERTER (1) Successive approximation register (SAR) The analog input voltage value and the voltage tap (comparative voltage) value from the serial resistance string are compared and the results are stored in this register from the most significant bit (MSB). If values are stored to the least significant bit (LSB) (after A/D conversion), the contents of the SAR are transferred to the A/D conversion results register (ADCR).
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CHAPTER 14 A/D CONVERTER (7) AVREF0 pin This pin inputs the A/D converter reference voltage. It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AVREF0 and AVSS. The current flowing in the series resistor string can be reduced by setting the voltage to be input to the AVREF0 pin to AVSS level in standby mode. Caution A series resistor string of approximately 10 kΩ is connect between the AVREF0 pin and the AVSS pin.
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CHAPTER 14 A/D CONVERTER Figure 14-2. A/D Converter Mode Register Format Symbol 7 6 5 ADM CS TRG FR1 4 3 2 1 0 After Reset 01H Address FR0 ADM3 ADM2 ADM1 HSC FF80H R/W R/W Analog Input Channel Selection ADM3 ADM2 ADM1 0 0 0 ANI0 0 0 1 ANI1 0 1 0 ANI2 0 1 1 ANI3 1 0 0 ANI4 1 0 1 ANI5 1 1 0 ANI6 1 1 1 ANI7 A/D Conversion Time SelectionNote 1 FR1 FR0 HSC fX = 5.
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CHAPTER 14 A/D CONVERTER (2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. Pins other than those selected as analog input can be used as input/output ports. ADIS is set with an 8-bit memory manipulation instruction. RESET input sets ADIS to 00H. Cautions 1. Set the analog input channel in the following order. (1) Set the number of analog input channels with ADIS.
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CHAPTER 14 A/D CONVERTER (3) External interrupt mode register 1 (INTM1) This register sets the valid edge for INTP3 to INTP6. INTM1 is set with an 8-bit memory manipulation instruction. RESET input sets INTM1 to 00H. Figure 14-4.
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CHAPTER 14 A/D CONVERTER 14.4 A/D Converter Operations 14.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with A/D converter input select register (ADIS). (2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter mode register (ADM). (3) The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
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CHAPTER 14 A/D CONVERTER Figure 14-5. A/D Converter Basic Operation Conversion Time Sampling Time A/D Converter Operation Sampling SAR Undefined A/D Conversion 80H C0H or 40H ADCR Conversion Result Conversion Result INTAD A/D conversion operations are performed continuously until bit 7 (CS) of ADM is reset (0) by software.
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CHAPTER 14 A/D CONVERTER 14.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (the value stored in A/D conversion result register (ADCR)) is shown by the following expression. VIN ADCR = INT ( × 256 + 0.5) AVREF0 or (ADCR – 0.5) × Where, AVREF0 ≤ VIN < (ADCR + 0.5) × AVREF0 256 256 INT( ) : Function which returns integer parts of value in parentheses.
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CHAPTER 14 A/D CONVERTER 14.4.3 A/D converter operating mode Select 1 analog input channel from ANI0-ANI7 by the A/D converter input select register (ADIS) and the A/D converter mode register (ADM) and begin A/D conversion. The following two methods are used for starting an A/D conversion operation. • Hardware start: Conversion is started by trigger input (INTP3). • Software start: Conversion is started by setting ADM.
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CHAPTER 14 A/D CONVERTER (2) A/D conversion operation in software start When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 0 and 1, respectively, the A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM. Upon termination of the A/D conversion, the conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal (INTAD) is generated.
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CHAPTER 14 A/D CONVERTER 14.5 A/D Converter Cautions (1) Power consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in HALT mode with the subsystem clock. As a current still flows in the AVREF0 pin at this time, this current must be cut in order to minimize the overall system power dissipation. In Figure 14-9, the power dissipation can be reduced by outputting a low-level signal to the output port in standby mode.
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CHAPTER 14 A/D CONVERTER (3) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on pins AVREF0 and ANI0 to ANI7. Since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 14-10 in order to reduce noise. Figure 14-10.
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CHAPTER 14 A/D CONVERTER (6) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed. Caution is therefore required since, if a change of analog input pin is performed during A/D conversion, the A/D conversion result and ADIF for the analog input before the change may be set just before the ADM rewrite.
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CHAPTER 14 A/D CONVERTER (7) AVDD pin The AVDD pin is the analog circuit power supply pin, and supplies power to the input circuits of ANI0/P10 to ANI7/P17. Therefore, be sure to apply the same voltage as VDD to this pin even when the application circuit is designed so as to switch to a backup battery. Figure 14-12.
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[MEMO] 278
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CHAPTER 15 D/A CONVERTER 15.1 D/A Converter Functions The D/A converter converts a digital input into an analog value. It consists of two 8-bit resolution channels of voltage output type D/A converter. The conversion method used is the R-2R resistor ladder method. D/A conversion is started by setting the DACE0 and DACE1 of the D/A converter mode register (DAM). There are two types of modes for the D/A converter, as follows.
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CHAPTER 15 D/A CONVERTER 15.2 D/A Converter Configuration The D/A converter consists of the following hardware. Table 15-1. D/A Converter Configuration Item Configuration D/A conversion value set register 0 (DACS0) Register D/A conversion value set register 1 (DACS1) Control register D/A converter mode register (DAM) Figure 15-1.
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CHAPTER 15 D/A CONVERTER (1) D/A conversion value set register 0, 1 (DACS0, DACS1) DACS0 and DACS1 are registers where values are set for determining the analog voltage output respectively to pins ANO0 and ANO1. DACS0 and DACS1 are set with 8-bit memory manipulation instructions. RESET input sets these registers to 00H. Analog voltage output to the ANO0 and ANO1 pins is determined by the following expression. ANOn output voltage = AVREF1 × where, DACSn 256 n = 0, 1 Cautions 1.
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CHAPTER 15 D/A CONVERTER 15.3 D/A Converter Control Registers The D/A converter mode register (DAM) controls the D/A converter. This register sets D/A converter operation enable/stop. The DAM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 15-2.
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CHAPTER 15 D/A CONVERTER 15.4 Operations of D/A Converter (1) Select the operation mode for channel 0 using bit 4 (DAM4) of the D/A converter mode register (DAM), and select the operation mode for channel 1 using bit 5 (DAM5). (2) Set data corresponding to the analog voltage values output respectively to pins ANO0/P130 and ANO1/P131 in D/A conversion setting registers 0 and 1 (DACS0 and DACS1).
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CHAPTER 15 15.5 D/A CONVERTER Cautions Related to D/A Converter (1) Output impedance of D/A converter Because the output impedance of the D/A converter is high, use of current flowing from the ANOn pins (n = 0,1) is prohibited. If the input impedance of the load for the converter is low, insert a buffer amplifier between the load and the ANOn pins. In addition, wiring from the ANOn pins to the buffer amplifier or the load should be as short as possible (because of high output impedance).
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) The µPD78058F Subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1. Refer to CHAPTER 19 SERIAL INTERFACE CHANNEL 2 for details of the serial interface channel 2). Table 16-1.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) 16.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes. • Operation stop mode • 3-wire serial I/O mode • SBI (serial bus interface) mode • 2-wire serial I/O mode Caution Do not switch the operating mode (3-wire serial I/O/ 2-wire serial I/O/SBI) while operation of serial interface channel 0 is enabled. If switching the operation mode, first terminate the serial operation, then carry out switching.
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SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) CHAPTER 16 (4) 2-wire serial I/O mode (MSB-first) This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) 16.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 16-2.
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SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) CHAPTER 16 Figure 16-2.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction. When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial operation.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (3) SO0 latch This latch holds the SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled by software. In the SBI mode, this latch is set upon termination of the 8th serial clock. (4) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) 16.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) • Serial bus interface control register (SBIC) • Interrupt timing specify register (SINT) (1) Timer clock select register 3 (TCL3) This register sets the serial clock of serial interface channel 0.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) Figure 16-3. Timer Clock Select Register 3 Format Symbol 7 6 5 4 3 2 1 0 TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 Address After Reset FF43H R/W 88H R/W Serial Interface Channel 0 Serial Clock Selection TCL33 TCL32 TCL31 TCL30 MCS = 1 MCS = 0 0 1 1 0 fXX/2 Setting prohibited fX/22 (1.25 MHz) 0 1 1 1 fXX/22 fX/22 (1.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. Caution Do not switch the operating mode (3-wire serial I/O/ 2-wire serial I/O/SBI) while operation of serial interface channel 0 is enabled.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) Figure 16-4.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Figure 16-5. Serial Bus Interface Control Register Format (1/2) Symbol 7 6 5 4 3 2 1 0 SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W After Reset FF61H R/W 00H R/WNote RELT Used for bus release signal output.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) Figure 16-5. Serial Bus Interface Control Register Format (2/2) R/W ACKE 0 Acknowledge Signal Automatic Output Control Acknowledge signal automatic output disable (output with ACKT enable) Before completion of transfer Acknowledge signal is output in synchronization with the 9th clock falling edge of SCK0 (automatically output when ACKE = 1).
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/P27 pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Figure 16-6.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) 16.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • SBI mode • 2-wire serial I/O mode 16.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) 16.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series. Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).
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CHAPTER 16 Symbol 7 6 5 CSIM0 CSIE0 COI R/W R/W SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) 4 WUP 3 2 1 CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 R/W Address FF60H After Reset 00H 0 × Input Clock to SCK0 pin from off-chip 1 0 8-bit timer register 2 (TM2) output 1 1 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) CSIM CSIM CSIM 04 03 0 × Operation Mode 02 0 R/W R/W Note 1 Serial Interface Channel 0 Clock Selection CSIM01 CSIM00 PM25 P25 PM26 P26 PM2
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol 7 6 5 4 3 2 1 0 SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W R/W Address FF61H 00H R/W R/W RELT When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. CMDT When CMDT = 1, SO0 Iatch is cleared to 0.
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SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) CHAPTER 16 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0). The transmitted data is held in the SO0 latch and is output from the SO0 pin.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 16-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form. MSB/LSB switching as the start bit can be specified with bit 2 (CSIM02) of the serial operating mode register 0 (CSIM0). Figure 16-9.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) 16.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format. SBI uses a single master device and employs the clocked serial I/O format with the addition of a bus configuration function. This function enables devices to communicate using only two lines.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (1) SBI functions In the conventional serial I/O format, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary, to provide chip select signal to identify command and data, and to judge the busy state, because only the data transfer function is available. If these operations are to be controlled by software, the software must be heavily loaded.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (2) SBI definition The SBI serial data format and the signals to be used are defined as follows. Serial data to be transferred with SBI consists of three kinds of data: “address”, “command”, and “data”. Figure 16-11 shows the address, command, and data transfer timings. Figure 16-11.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (a) Bus release signal (REL) The bus release signal is a signal with the SB0 (SB1) line which has changed from the low level to the high level when the SCK0 line is at the high level (without serial clock output). This signal is output by the master device. Figure 16-12. Bus Release Signal SCK0 "H" SB0 (SB1) The bus release signal indicates that the master device is going to transmit an address to the slave device.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (c) Address An address is 8-bit data which the master device outputs to the slave device connected to the bus line in order to select a particular slave device. Figure 16-14. Addresses 1 SCK0 A7 SB0 (SB1) 2 A6 3 A5 4 5 A4 A3 6 A2 7 A1 8 A0 Address Bus Release Signal Command Signal 8-bit data following bus release and command signals is defined as an “address”.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (d) Command and data The master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. Figure 16-16. Commands SCK0 1 SB0 (SB1) 2 C7 3 C6 4 C5 5 C4 6 C3 7 C2 8 C1 C0 Command Command Signal Figure 16-17. Data SCK0 SB0 (SB1) 1 D7 2 D6 3 D5 4 5 D4 D3 6 D2 7 D1 8 D0 Data 8-bit data following a command signal is defined as “command” data.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (e) Acknowledge signal (ACK) The acknowledge signal is used to check serial data reception between transmitter and receiver. Figure 16-18. Acknowledge Signal [When output in synchronization with 11th clock SCK0] SCK0 8 9 10 11 SB0 (SB1) ACK [When output in synchronization with 9th clock SCK0] SCK0 SB0 (SB1) Remark 8 9 ACK The dotted line indicates READY status.
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SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) CHAPTER 16 (f) Busy signal (BUSY) and ready signal (READY) The BUSY signal is intended to report to the master device that the slave device is preparing for data transmission/reception. The READY signal is intended to report to the master device that the slave device is ready for data transmission/reception. Figure 16-19.
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CHAPTER 16 Symbol 7 6 5 CSIM0 CSIE0 COI R/W R/W SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) 4 WUP 3 2 1 0 Address After Reset FF60H CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 00H R/W Note 1 Serial Interface Channel 0 Clock Selection CSIM01 CSIM00 0 × Input Clock to SCK0 pin from off-chip 1 0 8-bit timer register 2 (TM2) output 1 1 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 Operation Mode Start Bit SI0/SB0
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. The shaded area is used in the SBI mode. Symbol 7 6 5 4 3 2 1 0 SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W FF61H 00H R/W R/WNote Used for bus release signal output. When RELT = 1, SO0 Iatch is set to (1). After SO0 latch setting, automatically cleared to (0).
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CHAPTER 16 R SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) ACKD Acknowledge Detection Set Conditions (ACKD = 1) Clear Conditions (ACKD = 0) • SCK0 fall immediately after the busy mode is released during the transfer start instruction execution.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (4) Various signals Figures 16-20 to 16-25 show various signals and flag operations in SBI. Table 16-3 lists various signals in SBI. Figure 16-20. RELT, CMDT, RELD, and CMDD Operations (Master) Slave address write to SIO0 (Transfer Start Instruction) SIO0 SCK0 SB0 (SB1) RELT CMDT RELD CMDD Figure 16-21.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) Figure 16-22. ACKT Operation SCK0 SB0 (SB1) 6 7 D2 8 D1 9 D0 ACK ACKT When set during this period Caution Do not set ACKT before termination of transfer.
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SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) CHAPTER 16 Figure 16-23.
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SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) CHAPTER 16 Figure 16-24.
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Table 16-3. Various Signals in SBI Mode (1/2) Signal Name Acknowledge signal (ACK) Busy signal (BUSY) SB0 (SB1) rising edge when SCK0 = 1 SCK0 Condition Effects on Flag CMD signal is output to indicate that transmit data is an address. • CMDT set • CMDD set i) Transmit data is an address after REL signal output. ii) REL signal is not output and transmit data is an command.
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Table 16-3. Various Signals in SBI Mode (2/2) Signal Name Master Synchronous clock to output address/command/ data, ACK signal, synchroSCK0 nous BUSY signal, etc. Address/command/data are SB0 (SB1) transferred with the first eight synchronous clocks.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (5) Pin configuration The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations. (a) SCK0 ............ Serial clock input/output pin <1> Master .. CMOS and push-pull output <2> Slave .... Schmitt input (b) SB0 (SB1) .... Serial data input/output dual-function pin Both master and slave devices have an N-ch open drain output and a Schmitt input.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (6) Address match detection method In the SBI mode, the master transmits a slave address to select a specific slave device. Coincidence of the addresses can be automatically detected by hardware. CSIIF0 is set only when the slave address transmitted by the master coincides with the address set to SVA when the wake-up function specify bit (WUP) = 1.
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Figure 16-27.
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Figure 16-28.
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Figure 16-29.
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Figure 16-30.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (9) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 • Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer. Cautions 1. If CSIE0 is set to “1” after data write to SIO0, transfer does not start. 2.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (10) How to determine the slave busy state When a device is in the master mode, use the following procedure to determine if the slave is in the busy state or not. <1> Detect the generation of an acknowledge signal (ACK) or interrupt request signal. <2> Set the port mode register PM25 (or PM26) of pin SB0/P25 (or SB1/P26) in the input mode. <3> Read the terminal’s status (the pin is in the ready state if it is in the high level).
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) 16.4.4 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1). Figure 16-31.
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CHAPTER 16 Symbol 7 6 5 CSIM0 CSIE0 COI R/W R/W SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) 4 WUP 3 2 1 0 CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 Address FF60H After Reset 00H 0 × Input Clock to SCK0 pin from off-chip 1 0 8-bit timer register 2 (TM2) output 1 1 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) CSIM CSIM CSIM Operation Mode 02 Start Bit SIO/SB0/P25 SO0/SB1/P26 SCK0/P27 Pin Function Pin Function Pin Function 04 03 0 × 3-wire Seri
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol 7 6 5 4 3 2 1 0 Address SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W R/W FF61H After Reset 00H R/W R/W RELT When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the serial clock (SCK0).
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) (3) Other signals Figure 16-33 shows RELT and CMDT operations. Figure 16-33. RELT and CMDT Operations SO0 Latch RELT CMDT (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 • Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer. Cautions 1.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78058F SUBSERIES) 16.4.5 SCK0/P27 pin output manipulation Because the SCK0/P27 pin incorporates an output latch, static output is also possible by software in addition to normal serial clock output. P27 output latch manipulation enables any value of SCK0 to be set by software. (SI0/SB0 and SO0/SB1 pin to be controlled with the RELT and CMDT bits of serial bus interface control register (SBIC).) SCK0/P27 pin output manipulating procedure is described below.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) The µPD78058FY Subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1. Refer to CHAPTER 19 SERIAL INTERFACE CHANNEL 2 for details of the serial interface channel 2). Table 17-1.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) 17.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode • I2C (Inter IC) bus mode Caution Do not switch the operating mode (3-wire serial I/O/ 2-wire serial I/O/I2C bus) while operation of serial interface channel 0 is enabled. The operation mode should be switched after stopping the serial operation.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (4) I2C (Inter IC) bus mode (MSB-first) This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCL) and serial data bus (SDA0 or SDA1). This mode is in compliance with the I2C bus format. In this mode, the transmitter outputs three kinds of data onto the serial data bus: “start condition”, “data”, and “stop condition”, to be actually sent or received.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) 17.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 17-2.
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SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) CHAPTER 17 Figure 17-2.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel-serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction. When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial operation.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (3) SO0 latch This latch holds SI0/SB0/SDA0/P25 and SO0/SB1/SDA1/P26 pin levels. It can be directly controlled by software. (4) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received. (5) Serial clock control circuit This circuit controls serial clock supply to the serial I/O shift register 0 (SIO0).
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) Table 17-3. Serial Interface Channel 0 Interrupt Request Signal Generation Serial Transfer mode 3-wire or 2-wire serial I/O BSYE WUP WAT1 WAT0 ACKE 0 0 0 0 0 mode An interrupt request signal is generated each time 8 serial clocks are counted. Other than above I2C bus mode (transmit) Description 0 0 1 Setting prohibited 0 0 An interrupt request signal is generated each time 8 serial clocks are counted (8-clock wait).
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) 17.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) • Serial bus interface control register (SBIC) • Interrupt timing specify register (SINT) (1) Timer clock select register 3 (TCL3) This register sets the serial clock of serial interface channel 0.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) Figure 17-3. Timer Clock Select Register 3 Format Symbol 7 6 5 4 3 2 1 0 Address TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 After Reset FF43H R/W 88H R/W Serial Interface Channel 0 Serial Clock Selection TCL33 TCL32 TCL31 TCL30 Serial Clock in I2C Bus Mode MCS = 1 MCS = 0 5 Serial Clock in 2-Wire or 3-Wire Serial I/O Mode MCS = 1 MCS = 0 0 1 1 0 f XX/2 Setting prohibited f X/2 (78.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) Figure 17-4.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Figure 17-5. Serial Bus Interface Control Register Format (1/2) Symbol 7 6 5 4 3 2 1 0 SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W After Reset FF61H 00H R/W R/WNote RELT Used for stop condition signal output.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) Figure 17-5. Serial Bus Interface Control Register Format (2/2) R/W Acknowledge Signal Output ControlNote 1 ACKE Disables acknowledge signal automatic output. (However, output with ACKT is enabled) Used for reception when 8-clock wait mode is selected or for transmission. Note 2 0 1 R Enables acknowledge signal automatic output.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/SCL pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Figure 17-6.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) Figure 17-6. Interrupt Timing Specify Register Format (2/2) R/W R/W R SVA Bit to be Used as Slave Address SVAM 0 Bits 0 to 7 1 Bits 1 to 7 INTCSI0 Interrupt Source SelectionNote1 SIC 0 CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer 1 CSIIF0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer SCK0/SCL Pin LevelNote 2 CLD 0 Low level 1 High level Notes 1.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) 17.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode • I2C (Inter IC) bus mode 17.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) 17.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series. Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol 7 6 5 4 3 2 1 0 SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W R/W Address FF61H After Reset 00H R/W R/W RELT When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
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SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) CHAPTER 17 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0). The transmitted data is held in the SO0 latch and is output from the SO0 pin.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 17-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form. MSB/LSB switching as the start bit can be specified with bit 2 (CSIM02) of the serial operating mode register 0 (CSIM0). Figure 17-9.
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CHAPTER 17 17.4.3 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1). Figure 17-10.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol 7 6 5 4 3 2 1 0 SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W R/W Address After Reset FF61H 00H R/W R/W RELT When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the serial clock (SCK0).
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (3) Other signals Figure 17-12 shows RELT and CMDT operations. Figure 17-12. RELT and CMDT Operations SO0 Latch RELT CMDT (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 • Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer.
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CHAPTER 17 17.4.4 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) I2C bus mode operation The I2C bus mode is provided for when communication operations are performed between a single master device and multiple slave devices.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (1) I2C bus mode functions In the I2C bus mode, the following functions are available. (a) Automatic identification of serial data Slave devices automatically detect and identifies start condition, data, and stop condition signals sent in series through the serial data bus.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (a) Start condition When the SDA0 (SDA1) pin level is changed from high to low while the SCL pin is high, this transition is recognized as the start condition signal. This start condition signal, which is created using the SCL and SDA0 (or SDA1) pins, is output from the master device to slave devices to initiate a serial transfer. See section 17.4.5 Cautions on use of I2C bus mode for details of the start condition output.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (d) Acknowledge signal (ACK) The acknowledge signal indicates that the transferred serial data has definitely been received. This signal is used between the sending side and receiving side devices for confirmation of correct data transfer. In principle, the receiving side device returns an acknowledge signal to the sending device each time it receives 8-bit data.
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SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) CHAPTER 17 (f) Wait signal (WAIT) The wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data. During the wait state, the slave device continues to output the wait signal by keeping the SCL pin low to delay subsequent transfers. When the wait state is released, the master device can start the next transfer.
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SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) CHAPTER 17 (3) Register setting The I2C bus mode is set by the serial operating mode register 0 (CSIM0), serial bus interface control register (SBIC), and interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets 00H.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol 7 6 5 4 3 2 1 0 SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT Address After Reset FF61H 00H R/W R/W Note 1 R/W RELT Use for stop condition output. When RELT = 1, SO0 latch is set to 1. After SO0 latch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (c) Interrupt timing specification register (SINT) SINT is set by the 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (4) Various signals A list of signals in the I2C bus mode is given in Table 17-4. Table 17-4. Signals in I2C Bus Mode Signal Name Start condition Definition : Description SDA0 (SDA1) falling edge when SCL is high Note 1 Function : Indicates that serial communication starts and subsequent data are address data. Signaled by : Master Signaled when : CMDT is set. Affected flag(s) : CMDD (is set.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (5) Pin configurations The configurations of the serial clock pin SCL and the serial data bus pins SDA0 (SDA1) are shown below. (a) SCL Pin for serial clock input/output dual-function pin. <1> Master ..... N-ch open-drain output <2> Slave ....... Schmitt input (b) SDA0 (SDA1) Serial data input/output dual-function pin. Uses N-ch open-drain output and Schmitt-input buffers for both master and slave devices.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (7) Error detection In the I2C bus mode, transmission error detection can be performed by the following methods because the serial bus SDA0 (SDA1) status during transmission is also taken into the serial I/O shift register 0 (SIO0) register of the transmitting device. (a) Comparison of SIO0 data before and after transmission In this case, a transmission error is judged to have occurred if the two data values are different.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) Figure 17-22.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) Figure 17-22.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) Figure 17-22.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) Figure 17-23.
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SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) CHAPTER 17 Figure 17-23.
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SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) CHAPTER 17 Figure 17-23.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) 17.4.5 Cautions on use of I2C bus mode (1) Start condition output (master) The SCL pin normally outputs a low-level signal when no serial clock is output. It is necessary to change the SCL pin to high in order to output a start condition signal. To set pin SCL to high level, set bit 3 (CLC) of the interrupt timing specification register (SINT) to 1. After setting CLC, clear CLC to 0 and return the SCL pin to low.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (2) Slave wait release (slave transmission) Slave wait status is released by WREL flag (bit 2 of interrupt timing specify register (SINT)) setting or execution of an serial I/O shift register 0 (SIO0) write instruction. If the slave sends data, the wait is immediately released by execution of an SIO0 write instruction and the clock rises without the start transmission bit being output in the data line.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (3) Slave wait release (slave reception) The slave is released from the wait status when the WREL flag (bit 2 of the interrupt timing specify register (SINT)) is set or when an instruction that writes data to the serial I/O shift register 0 (SIO0) is executed.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) (4) Reception completion of salve In the reception completion processing of the slave, check the bit 3 (CMDD) of the serial bus interface control register (SBIC) and bit 6 (COI) of the serial operation mode register 0 (CSIM0) (when CMDD = 1).
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) • Example of program releasing serial transfer status SET1 P2.5; <1> SET1 PM2.5; <2> SET1 PM2.7; <3> CLR1 CSIE0; <4> SET1 CSIE0; <5> SET1 RELT; <6> CLR1 PM2.7; <7> CLR1 P2.5; <8> CLR1 PM2.5; <9> <1> This instruction prevents the SDA0 pin from outputting a low level when the I2C bus mode is restored by instruction <5>. The output of the SDA0 pin goes into a high-impedance state.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) 17.4.7 SCK0/SCL/P27 pin output manipulation The SCK0/SCL/P27 pin can execute static output via software, in addition to outputting the normal serial clock. The value of serial clocks can also be arbitrarily set by software (the SI0/SB0/SDA0 and SO0/SB1/SDA1 pins are controlled with the RELT and CMDT bits of serial bus interface control register (SBIC)). The SCK0/SCL/P27 pin output should be manipulated as described below.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78058FY SUBSERIES) Figure 17-29. Logic Circuit of SCL Signal CLC (manipulated by bit manipulation instruction) SCL Wait request signal Serial clock (low while transfer is stopped) Remarks 1. This figure indicates the relation of the signals and does not indicate the internal circuit. 2.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.1 Serial Interface Channel 1 Functions Serial interface channel 1 employs the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.2 Serial Interface Channel 1 Configuration Serial interface channel 1 consists of the following hardware. Table 18-1.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-1.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (1) Serial I/O shift register 1 (SIO1) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO1 is set with an 8-bit memory manipulation instruction. When the value in bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is 1, writing data to SIO1 starts serial operation.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.3 Serial Interface Channel 1 Control Registers The following four types of registers are used to control serial interface channel 1. • Timer clock select register 3 (TCL3) • Serial operating mode register 1 (CSIM1) • Automatic data transmit/receive control register (ADTC) • Automatic data transmit/receive interval specify register (ADTI) (1) Timer clock select register 3 (TCL3) This register sets the serial clock of serial interface channel 1.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-2. Timer Clock Select Register 3 Format Symbol 7 6 5 4 3 2 1 0 TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 Address FF43H After Reset 88H R/W R/W Serial Interface Channel 1 Serial Clock Selection TCL37 TCL36 TCL35 TCL34 MCS = 1 MCS = 0 0 1 1 0 fXX/2 Setting prohibited fX/22 (1.25 MHz) 0 1 1 1 fXX/22 fX/22 (1.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Serial operating mode register 1 (CSIM1) This register sets serial interface channel 1 serial clock, operating mode, operation enable/stop and automatic transmit/receive operation enable/stop. CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM1 to 00H. Figure 18-3.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) Automatic data transmit/receive control register (ADTC) This register sets automatic receive enable/disable, the operating mode, strobe output enable/disable, busy input enable/disable, error check enable/disable and displays automatic transmit/receive execution and error detection. ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H. Figure 18-4.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (4) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Figure 18-5.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (2/4) Symbol 7 ADTI ADTI7 6 5 0 0 4 3 2 1 0 Address ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 After Reset FF6BH 00H R/W R/W Data Transfer Interval Specification (fXX = 5.0 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 MinimumNote MaximumNote 1 0 0 0 0 223.2 µ s + 0.5/fSCK 224.8 µ s + 1.5/fSCK 1 0 0 0 1 236.0 µ s + 0.5/fSCK 237.6 µ s + 1.5/fSCK 1 0 0 1 0 248.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (3/4) Symbol 7 ADTI ADTI7 6 5 0 0 4 3 2 1 0 Address ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI7 After Reset FF6BH 00H R/W R/W Data Transfer Interval Control 0 No control of interval by ADTI 1 Control of interval by ADTI (ADTI0 to ADTI4) Note 1 Data Transfer Interval Specification (fXX = 2.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (4/4) Symbol 7 ADTI ADTI7 6 5 0 0 4 3 2 1 0 Address ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 After Reset FF6BH 00H R/W R/W Data Transfer Interval Specification (fXX = 2.5 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 MinimumNote MaximumNote 1 0 0 0 0 446.4 µ s + 0.5/fSCK 449.6 µ s + 1.5/fSCK 1 0 0 0 1 472.0 µ s + 0.5/fSCK 475.2 µ s + 1.5/fSCK 1 0 0 1 0 497.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4 Serial Interface Channel 1 Operations The following three operating modes are available to the serial interface channel 1. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 18.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers that incorporate a conventional synchronous serial interface such as the 75X/XL, 78K and 17K Series. Communication is carried out with three lines of serial clock (SCK1), serial output (SO1) and serial input (SI1). (1) Register setting The 3-wire serial I/O mode is set with the serial operating mode register 1 (CSIM1).
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 1 (SIO1) is carried out at the falling edge of the serial clock SCK1. The transmit data is held in the SO1 latch and is output from the SO1 pin.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-7. Circuit of Switching in Transfer Bit Order 7 6 Internal Bus 1 0 LSB-first MSB-first Read/Write Gate Read/Write Gate SO1 Latch SI1 Serial I/O Shift Register 1 (SIO1) D Q SO1 SCK1 Start bit switching is realized by switching the bit order write to SIO1. The SIO1 shift order remains unchanged. Thus, switching between MSB-first and LSB-first must be performed before writing data to SIO1.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4.3 3-wire serial I/O mode operation with automatic transmit/receive function This 3-wire serial I/O mode is used for transmission/reception of a maximum of 32-byte data without the use of software. Once transfer is started, the data prestored in the RAM can be transmitted by the set number of bytes, and data can be received and stored in the RAM by the set number of bytes.
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CHAPTER 18 Symbol 7 6 CSIM1 CSIE1 DIR 5 4 3 2 ATE 0 0 0 SERIAL INTERFACE CHANNEL 1 1 0 CSIM11 CSIM10 Address After Reset FF68H 00H R/W R/W Serial Interface Channel 1 Clock Selection CSIM11 CSIM10 0 × Clock externally input to SCK1 pinNote 1 1 0 8-bit timer register 2 (TM2) output 1 1 Clock specified with bits 4 to 7 of timer clock select register 3 (TCL3) ATE Serial Interface Channel 1 Operating Mode Selection 0 3-wired serial I/O mode 1 3-wired serial I/O mode with aut
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) Automatic data transmit/receive control register (ADTC) ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H.
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CHAPTER 18 Symbol 7 ADTI ADTI7 6 5 0 0 4 3 2 SERIAL INTERFACE CHANNEL 1 1 0 Address ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 After Reset FF6BH 00H R/W R/W Data Transfer Interval Specification (fXX = 5.0 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 MinimumNote MaximumNote 1 0 0 0 0 223.2 µ s + 0.5/fSCK 224.8 µ s + 1.5/fSCK 1 0 0 0 1 236.0 µ s + 0.5/fSCK 237.6 µ s + 1.5/fSCK 1 0 0 1 0 248.8 µ s + 0.5/fSCK 250.4 µ s + 1.5/fSCK 1 0 0 1 1 261.6 µ s + 0.5/fSCK 263.2 µ s + 1.
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CHAPTER 18 Symbol 7 ADTI ADTI7 6 5 0 0 4 3 2 SERIAL INTERFACE CHANNEL 1 1 0 Address ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI7 After Reset FF6BH 00H R/W R/W Data Transfer Interval Control ADTINote 1 0 No control of interval by 1 Control of interval by ADTI (ADTI0 to ADTI4) Data Transfer Interval Specification (fXX = 2.5 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 MinimumNote 2 MaximumNote 2 0 0 0 0 0 36.8 µ s + 0.5/fSCK 40.0 µ s + 1.5/fSCK 0 0 0 0 1 62.4 µ s + 0.
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CHAPTER 18 Symbol 7 ADTI ADTI7 6 5 0 0 4 3 2 SERIAL INTERFACE CHANNEL 1 1 0 Address ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 After Reset FF6BH 00H R/W R/W Data Transfer Interval Specification (fXX = 2.5 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 MinimumNote MaximumNote 1 0 0 0 0 446.4 µ s + 0.5/fSCK 449.6 µ s + 1.5/fSCK 1 0 0 0 1 472.0 µ s + 0.5/fSCK 475.2 µ s + 1.5/fSCK 1 0 0 1 0 497.6 µ s + 0.5/fSCK 500.8 µ s + 1.5/fSCK 1 0 0 1 1 523.2 µ s + 0.5/fSCK 526.4 µ s + 1.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FAC0H of internal buffer RAM (up to FADFH at maximum). The transmit data should be in the order from high-order address to low-order address. <2> Set to the automatic data transmit/receive address pointer (ADTP) the value obtained by subtracting 1 from the number of transmit data bytes.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) Communication operation (a) Basic transmission/reception mode This transmission/reception mode is the same as the 3-wire serial I/O mode in which specified number of data are transmitted/received in 8-bit units. Serial transmission is started by writing the desired data to serial I/O shift register 1 (SIO1) when bit 7 (CSIE1) of serial operation mode register 1 (CSIM1) is set at 1. When the final byte has been sent, an interrupt request flag (CSIIF1) is set.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-9.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission/reception (ARLD = 0, RE = 1) in basic transmit/receive mode, internal buffer RAM operates as follows. (i) Before transmission/reception (See Figure 18-10 (a).) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the internal buffer RAM to SIO1.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-10.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) Basic transmission mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transmission is started by writing the desired data to serial I/O shift register 1 (SIO1) when bit 7 (CSIE1) of serial operation mode register 1 (CSIM1) is set at 1. When the final byte has been sent, an interrupt request flag (CSIIF1) is set.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-12.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD=0, RE=0) in basic transmit mode, internal buffer RAM operates as follows. (i) Before transmission (See Figure 18-13 (a).) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the internal buffer RAM to SIO1. When transmission of the first byte is completed, automatic data transmit/receive address pointer (ADTP) is decremented.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-13.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Repeat transmission mode In this mode, data stored in the internal buffer RAM is transmitted repeatedly. Serial transmission is started by writing the desired data to serial I/O shift register 1 (SIO1) when bit 7 (CSIE1) of serial operation mode register 1 (CSIM1) is set at 1.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-15.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD = 1, RE = 0) in repeat transmit mode, internal buffer RAM operates as follows. (i) Before transmission (See Figure 18-16 (a).) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the internal buffer RAM to SIO1. When transmission of the first byte is completed, automatic data transmit/receive address pointer (ADTP) is decremented.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-16.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (d) Automatic transmission/reception suspending and restart Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) to 0. If during 8-bit data transfer, the transmission/reception is not suspended if bit 7 (CSIE1) is set to 0. It is suspended upon completion of 8-bit data transfer.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (4) Synchronization control Busy control and strobe control are functions for synchronizing sending and receiving between the master device and slave device. By using these functions, it is possible to detect bit slippage during sending and receiving.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Furthermore, in the case that the busy control option is used, select the internal clock for the serial clock. The busy signal cannot be controlled with an external clock. The operation timing when the busy control option is used is shown in Figure 18-19. Caution Busy control cannot be used at the same time as interval timing control using the auto data send and receive interval instruction register (ADIT).
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-20 Busy Signal and Wait Cancel (When BUSY0 = 0) SCK1 SO1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY (Active High) 1.5 clocks (min.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-21. Operation Timings When Using Busy & Strobe Control Option (BUSY0 = 0) SCK1 SO1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 STB BUSY CSIIF1 Busy Input Release Busy Input Valid TRF Caution When TRF is cleared, the SO1 pin becomes low level.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Bit Slippage Detection Function Through the Busy Signal During an auto send and receive operation, noise occur in the serial clock signal output by the master device and bit slippage may occur in the slave device side serial clock. At this time, if the strobe control option is not used, this bit slippage will have an effect on sending of the next byte.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (5) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the internal buffer RAM are performed after transmitting/receiving one byte. Therefore, an interval is inserted before the next transmit/ receive.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (a) When the automatic transmit/receive function is used by the internal clock If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is set at (1), the internal clock operates. If the auto send and receive function is operated by the internal clock, interval timing by CPU processing is as follows. When bit 7 (ADTI7) of automatic data transmit/receive interval specify register (ADTI) is set to 0, the interval depends on the CPU processing.
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CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) When the automatic transmit/receive function is used by the external clock If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is cleared to 0, external clock operation is set. When the automatic transmit/receive function is used by the external clock, it must be selected so that the interval may be longer than the values shown as follows. Table 18-3.
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[MEMO] 432
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.1 Serial Interface Channel 2 Functions Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption. (2) Asynchronous serial interface (UART) mode In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.2 Serial Interface Channel 2 Configuration Serial interface channel 2 consists of the following hardware. Table 19-1.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-1.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-2.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (1) Transmit shift register (TXS) This register is used to set the transmit data. The data written in TXS is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data. Writing data to TXS starts the transmit operation. TXS is written to with an 8-bit memory manipulation instruction. It cannot be read. TXS value is FFH after RESET input.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.3 Serial Interface Channel 2 Control Registers Serial interface channel 2 is controlled by the following four registers. • Serial operating mode register 2 (CSIM2) • Asynchronous serial interface mode register (ASIM) • Asynchronous serial interface status register (ASIS) • Baud rate generator control register (BRGC) (1) Serial operating mode register 2 (CSIM2) This register is set when serial interface channel 2 is used in the 3-wire serial I/O mode.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Asynchronous serial interface mode register (ASIM) This register is set when serial interface channel 2 is used in the asynchronous serial interface mode. ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. Figure 19-4.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Table 19-2.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) Asynchronous serial interface status register (ASIS) This is a register which displays the type of error when a reception error is generated in the asynchronous serial interface mode. ASIS is read with 8-bit memory manipulation instruction. In 3-wire serial I/O mode, the contents of the ASIS are undefined. RESET input sets ASIS to 00H. Figure 19-5.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (4) Baud rate generator control register (BRGC) This register sets the serial clock for serial interface channel 2. BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Figure 19-6.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-6. Baud Rate Generator Control Register Format (2/2) 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS = 1 MCS = 0 0 0 0 0 fXX/210 fXX/210 (4.9 kHz) fX/211 (2.4 kHz) 11 0 1 0 1 fXX fX (5.0 MHz) fX/2 (2.5 MHz) 1 0 1 1 0 fXX/2 fX/2 (2.5 MHz) fX/22 (1.25 MHz) 2 fX/22 (1.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (a) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clocks generated by scaling the main system clock. The baud rate generated from the main system clock is found from the following expression.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. fASCK [Baud rate] = 2 × (k+16) [Hz] fASCK : Frequency of clock input to ASCK pin k : Value set in MDL0 to MDL3 (0 ≤ k ≤ 14) Table 19-4.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4 Serial Interface Channel 2 Operation Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 19.4.1 Operation stop mode In the operation stop mode, serial transfer is not performed, and therefore power consumption can be reduced. In the operation stop mode, the P70/SI2/RxD, P71/SO2/TxD and P72/SCK2/ASCK pins can be used as normal input/output ports.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.2 Asynchronous serial interface (UART) mode In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates. In addition, the baud rate can be defined by scaling the input clock to the ASCK pin. The MIDI standard baud rate (31.25 kbps) can be used by employing the dedicated UART baud rate generator.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Asynchronous serial interface status register (ASIS) ASIS is set with 8-bit memory manipulation instruction. RESET input sets ASIS to 00H.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (d) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS = 1 0 0 0 0 fXX/210 0 1 0 1 fXX fX/210 fX MCS = 0 (4.9 kHz) fX/211 (2.4 kHz) 11 (5.0 MHz) fX/2 (2.5 MHz) 1 (1.25 MHz) 2 0 1 1 0 fXX/2 fX/2 (2.5 MHz) fX/22 0 1 1 1 fXX/22 fX/22 (1.25 MHz) fX/23 (625 kHz) 3 fX/23 (625 kHz) fX/24 (313 kHz) 4 (313 kHz) fX/25 (156 kHz) 5 (78.1 kHz) 6 1 0 0 0 fXX/23 1 0 0 1 fXX/24 fX/24 fX/25 (156 kHz) fX/26 (78.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (i) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clock is generated by scaling the main system clock. The baud rate generated from the main system clock is obtained with the following expression.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. [Baud rate] = fASCK 2 × (k+16) [Hz] fASCK : Frequency of clock input to ASCK pin k : Value set in MDL0 to MDL3 (0 ≤ k ≤ 14) Table 19-6.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 19-7. Figure 19-7. Asynchronous Serial Interface Transmit/Receive Data Format One Data Frame Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Character Bits 1 data frame is composed of each of the bits shown below. • Start bits .................. 1 bit • Character bits ......... 7 bits/8 bits • Parity bits ................
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected. With 0 parity and no parity, an error cannot be detected.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Transmission A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit, parity bit and stop bit(s) are added automatically. When the transmit operation starts, the data in the transmit shift register (TXS) is shifted out, and when the transmit shift register (TXS) is empty, a transmission completion interrupt request (INTST) is generated. Figure 19-8.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (d) Reception When bit 6 (RXE) of the asynchronous serial interface mode register (ASIM) is set (1), a receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is performed using the serial clock specified by ASIM.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (e) Receive errors Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error. The data reception result error flag is set in the asynchronous serial interface status register (ASIS) and at the same time a receive error interrupt request (INTSER) is generated. Receive error causes are shown in Table 19-7.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) UART mode cautions (a) If bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) is cleared to (0) during transmission and sending operation is halt, be sure to set the transmit shift register (TXS) to FFH, then set TXE to 1 before executing the next transmission.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75X/XL Series, 78K Series, 17K Series, etc. Communication is performed using three lines: the serial clock (SCK2), serial output (SO2), and serial input (SI2).
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. When the 3-wire serial I/O mode is selected, 00H should be set in ASIM.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS = 1 0 0 0 0 fXX/210 0 1 0 1 fXX fX/210 fX MCS = 0 (4.9 kHz) fX/211 (2.4 kHz) 11 (5.0 MHz) fX/2 (2.5 MHz) 1 (1.25 MHz) 2 0 1 1 0 fXX/2 fX/2 (2.5 MHz) fX/22 0 1 1 1 fXX/22 fX/22 (1.25 MHz) fX/23 (625 kHz) 3 fX/23 (625 kHz) fX/24 (313 kHz) 4 (313 kHz) fX/25 (156 kHz) 5 (78.1 kHz) 6 1 0 0 0 fXX/23 1 0 0 1 fXX/24 fX/24 fX/25 (156 kHz) fX/26 (78.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 When the internal clock is used as the serial clock in the 3-wire serial I/O mode, set BRGC as described below. BRGC setting is not required if an external serial clock is used. (i) When the baud rate generator is not used: Select a serial clock frequency with TPS0 to TPS3. Be sure then to set MDL0 to MDL3 to 1,1,1,1. The serial clock frequency is 1/2 the source clock frequency of the 5-bit counter.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit by bit in synchronization with the serial clock. Transmit shift register (TXS/SIO2) and receive shift register (RXS) shift operations are performed in synchronization with the fall of the serial clock SCK2. Then transmit data is held in the SO2 latch and output from the SO2 pin.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 19-13 shows the configuration of the transmit shift register (TXS/SIO2) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form. MSB/LSB switching as the start bit can be specified with bit 2 (CSIM22) of the serial operating mode register 2 (CSIM2). Figure 19-13.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.4 Restrictions on using UART mode In the UART mode, a receive completion interrupt request (INTSR) is generated after a certain period of time following the generation and clearing of the receive error interrupt request (INTSER). Thereby, the phenomenon shown below may occur.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-15.
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2 [Example] Main Processing EI UART Receive Error Interrupt (INTSER) Servicing INTSER is Generated 7 Clocks (MIN.) of CPU Clock (Time from Interrupt Request to Servicing) Instructions for 2205 clocks (MIN.) of CPU clock are required.
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CHAPTER 20 REAL-TIME OUTPUT PORT 20.1 Real-Time Output Port Functions Data set previously in the real-time output buffer register can be transferred to the output latch by hardware concurrently with timer interrupt request or external interrupt request generation, then output externally. This is called the real-time output function. The pins that output data externally are called real-time output ports. By using a real-time output, a signal that has no jitter can be output.
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CHAPTER 20 REAL-TIME OUTPUT PORT 20.2 Real-Time Output Port Configuration The real-time output port consists of the following hardware. Table 20-1. Real-time Output Port Configuration Item Configuration Register Real-time output buffer register (RTBL, RTBH) Control register Port mode register 12 (PM12) Real-time output port mode register (RTPM) Real-time output port control register (RTPC) Figure 20-1.
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CHAPTER 20 REAL-TIME OUTPUT PORT (1) Real-time output buffer register (RTBL, RTBH) Addresses of RTBL and RTBH are mapped individually in the Special function register (SFR) area as shown in Figure 20-2. When specifying 4 bits × 2 channels as the operating mode, data are set individually in RTBL and RTBH. When specifying 8 bits × 1 channel as the operating mode, data are set to both RTBL and RTBH by writing 8-bit data to either RTBL or RTBH. Table 20-2 shows operations during manipulation of RTBL and RTBH.
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CHAPTER 20 REAL-TIME OUTPUT PORT 20.3 Real-Time Output Port Control Registers The following three registers control the real-time output port. • Port mode register 12 (PM12) • Real-time output port mode register (RTPM) • Real-time output port control register (RTPC) (1) Port mode register 12 (PM12) This register sets the input or output mode of port 12 pins (P120 to P127) which are multiplexed with realtime output pins (RTP0 to RTP7).
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CHAPTER 20 REAL-TIME OUTPUT PORT (3) Real-time output port control register (RTPC) This register sets the real-time output port operating mode and output trigger. Table 20-3 shows the relation between the operating mode of the real-time output port and output trigger. RTPC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 20-5.
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[MEMO] 476
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled status. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. It generates a standby release signal. A non-maskable interrupt contains one source of the watchdog timer interrupt request.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.2 Interrupt Sources and Configuration Combining all the factors in interrupts, non-maskable interrupts, maskable interrupts and software interrupts, there are a total of 22 source (see Table 21-1). Table 21-1.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Table 21-1.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-1.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-1.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input. IF0L, IF0H, and IF1L are set with a 1-bit or 8-bit memory manipulation instruction.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. If MK0L and MK0H are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting. RESET input sets these registers to FFH. Figure 21-3.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (3) Priority specify flag registers (PR0L, PR0H, and PR1L) The priority specify flag is used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting. RESET input sets these registers to FFH. Figure 21-4.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (4) External interrupt mode register (INTM0, INTM1) These registers set the valid edge for INTP0 to INTP6. INTM0 and INTM1 are set by 8-bit memory manipulation instructions. RESET input sets these registers to 00H. Figure 21-5.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-6.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (5) Sampling clock select register (SCS) This register is used to set the valid edge clock sampling clock to be input to INTP0. When remote controlled data reception is carried out using INTP0, digital noise is removed with sampling clocks. SCS is set with an 8-bit memory manipulation instruction. RESET input sets SCS to 00H. Figure 21-7.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS The noise elimination circuit sets the interrupt request flag (PIF0) at (1) when the sampled INTP0 input level is active twice in succession. Figure 21-8 shows the input/output timing of the noise elimination circuit. Figure 21-8.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (6) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt processing are mapped. In addition to being able to perform read and write operations in 8 bit units, operations using bit operation commands and special commands (EI, DI) can be performed.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4 Interrupt Servicing Operations 21.4.1 Non-maskable interrupt acknowledge operation A non-maskable interrupt request is received without condition even when in the interrupt request reception prohibited state. It does not undergo interrupt priority control and has highest priority over all other interrupts.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-10.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-12. Non-Maskable Interrupt Request Acknowledge Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main Routine NMI Request <1> NMI Request <2> NMI Request <1> executed. NMI Request <2> held. 1 Instruction Execution Held NMI Request <2> processed.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.2 Maskable Interrupt request reception For a maskable interrupt request, the interrupt request flag is set at (1) and if the mask (MK) flag of that interrupt is cleared (0), it is possible for it to be received. A vector interrupt request is received if an interrupt enable state exists (when the IE flag is set at (1)).
PAGE 495
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-13.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-14. Interrupt Request Acknowledge Timing (Minimum Time) 6 Clocks Instruction CPU Processing Instruction PSW and PC Save, Jump to Interrupt Servicing Interrupt Servicing Program × × IF (× × PR=1) 8 Clocks × × IF (× × PR=0) 7 Clocks Remark 1 clock : 1 (fCPU: CPU clock) fCPU Figure 21-15.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.3 Software interrupt request acknowledge operation A software interrupt request is received by the execution of a BRK command. A software interrupt cannot be prohibited. If a software interrupt request is received, the contents of the program status word (PSW) and the program counter (PC) are saved to the stack in that order, the IE flag is reset (0) and the contents of the vector table (003EH, 003FH) are loaded in the PC and branched.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Table 21-4. Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing Multiple Interrupt Non-maskable Request Interrupt Interrupt Currently Being Processed PR = 0 PR = 1 Request IE = 1 IE = 0 IE = 1 IE = 0 D D D D D ISP=0 E E D D D ISP=1 E E D E D E E D E D Non-maskable interrupt Maskable interrupt Maskable Interrupt Request Software interrupt Remarks 1. E : Multiple interrupt enable 2.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-16. Multiple Interrupt Example (1/2) Example 1 Example of multiple interrupt requests being generated twice. Main Processing INTxx Servicing IE=0 INTyy Servicing IE=0 EI IE=0 EI INTxx (PR=1) INTzz Servicing EI INTyy (PR=0) INTzz (PR=0) RETI RETI RETI During processing of interrupt INTxx, 2 interrupt requests, INTyy and INTzz, are received and multiple interrupts are generated.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Example 3 Example of a multiple interrupt not being generated because an interrupt was not permitted. Main Processing EI INTxx Servicing INTyy Servicing IE=0 INTxx (PR=0) 1 Instruction Execution INTyy (PR=0) RETI IE=0 RETI In processing of interrupt INTxx, interrupt reception was not permitted (the IE command was not issued), so interrupt request INTyy was not received and multiple interrupts were not generated.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.5 Interrupt request reserve Among the commands, there are some for which, even if an interrupt request is generated while they are being executed, reception of the interrupt request is held until execution of the next command is completed. The commands of this type (interrupt request hold commands) are shown below. • MOV PSW, #byte • MOV A, PSW • MOV PSW, A • MOV1 PSW.bit, CY • MOV1 CY, PSW.bit • AND1 CY, PSW.bit • OR1 CY, PSW.bit • XOR1 CY, PSW.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.5 Test Functions When a clock timer overflow occurs and when the port 4 falling edge is detected, a corresponding test input flag is set (1) and a standby release signal is generated. Unlike the interrupt function, vector processing is not executed. There are two test input factors as shown in Table 21-5. The basic configuration is shown in Figure 21-18. Table 21-5.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (1) Interrupt request flag register 1L (IF1L) It indicates whether a watch timer overflow is detected or not. It is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction. It is set to 00H by the RESET signal input. Figure 21-19.
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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (3) Key return mode register (KRM) This register is used to set enable/disable of standby function clear by key return signal (port 4 falling edge detection). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H. Figure 21-21.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.1 External Device Expansion Functions The external device expansion functions connect external devices to areas other than the internal ROM, RAM, and SFR. Connection of external devices uses ports 4 to 6. Ports 4 to 6 control address/data, read/write strobe, wait, address strobe etc. Table 22-1.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Memory maps when using the external device expansion function are as follows. Figure 22-1. Memory Map When Using External Device Expansion Function (1/2) (a) Memory Map of the µPD78056F and 78056FY, and of the µPD78P058F and 78P058FY when the internal PROM is 48 Kbytes.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-1.
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CHAPTER 22 22.2 EXTERNAL DEVICE EXPANSION FUNCTION External Device Expansion Function Control Register The external device expansion function is controlled by the memory expansion mode register (MM) and memory size switching register (IMS). (1) Memory expansion mode register (MM) MM sets the wait count and external expansion area, and also sets the input/output of port 4. MM is set with an 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 10H. Figure 22-2.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION (2) Memory size switching register (IMS) This register specifies the internal memory size. In principle, use IMS in a default status. However, when using the external device expansion function with the µPD78058F, 78P058F, 78058FY and 78P058FY, set IMS so that the internal ROM capacity is 56 Kbytes or lower. IMS is set with an 8-bit memory manipulation instruction. RESET input sets this register to the value indicated in Table 22-3. Figure 22-3.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.3 External Device Expansion Function Timing Timing control signal output pins in the external memory expansion mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin. The read strobe signal is output in data accesses and instruction fetches from external memory. During internal memory access, the read strobe signal is not output (maintains high level). (2) WR pin (Alternate function: P65) Write strobe signal output pin.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-4.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-5.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-6.
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CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-7.
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CHAPTER 23 STANDBY FUNCTION 23.1 Standby Function and Configuration 23.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. System clock oscillator continues oscillation. In this mode, current consumption cannot be decreased as in the STOP mode.
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CHAPTER 23 STANDBY FUNCTION 23.1.2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H. However, it takes 217/fX, not 218/fX, until the STOP mode is cleared by RESET input. Figure 23-1.
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CHAPTER 23 STANDBY FUNCTION 23.2 Standby Function Operations 23.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating status in the HALT mode is described below. Table 23-1.
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CHAPTER 23 STANDBY FUNCTION (2) HALT mode clear The HALT mode can be cleared with the following four types of sources. (a) Clear upon unmasked interrupt request The HALT mode is cleared when an unmasked interrupt request is generated. If interrupt acknowledge is enabled, vectored interrupt servicing is performed. If disabled, the next address instruction is executed. Figure 23-2.
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CHAPTER 23 STANDBY FUNCTION (d) Clear upon RESET input The HALT mode is cleared upon RESET signal input. As is the case with normal reset operation, a program is executed after branching to the reset vector address. Figure 23-3. HALT Mode Release by RESET Input Wait (217/f x : 26.2 ms) HALT Instruction RESET Signal Operating Mode HALT Mode Oscillation Clock Oscillation Stabilization Wait Status Reset Period Oscillation Stop Operating Mode Oscillation Remarks 1.
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CHAPTER 23 STANDBY FUNCTION 23.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to VDD via a pull-up resistor to minimize the leakage current at the crystal oscillator. Thus, do not use the STOP mode in a system where an external clock is used for the main system clock. 2.
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CHAPTER 23 STANDBY FUNCTION (2) STOP mode release The STOP mode can be cleared with the following three types of sources. (a) Release by unmasked interrupt request The STOP mode is cleared upon generation of an unmasked interrupt request. If interrupt acknowledge is enabled, vectored interrupt servicing is performed after the lapse of the oscillation stabilization time. If interrupt acknowledge is disabled, the next address instruction is executed. Figure 23-4.
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CHAPTER 23 STANDBY FUNCTION (c) Release by RESET input The STOP mode is cleared upon RESET input, and after the lapse of the oscillation stabilization time, reset operation is performed. Figure 23-5. Release by STOP Mode RESET Input Wait (217/f x : 26.2 ms) STOP Instruction RESET Signal Operating Mode Reset Period STOP Mode Oscillation Stabilization Wait Status Oscillation Stop Oscillation Operating Mode Oscillation Clock Remarks 1. fX: main system clock oscillation frequency 2. ( ): fX: 5.
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CHAPTER 24 RESET FUNCTION 24.1 Reset Function The following two operations are available to generate the reset signal. (1) External reset input with RESET pin (2) Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.
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CHAPTER 24 RESET FUNCTION Figure 24-2. Timing of Reset Input by RESET Input X1 Oscillation Stabilization Time Wait Reset Period (Oscillation Stop) Normal Operation Normal Operation (Reset Processing) RESET Internal Reset Signal Delay Delay Hi-Z Port Pin Figure 24-3.
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CHAPTER 24 RESET FUNCTION Table 24-1. Hardware Status After Reset (1/2) Hardware Program counter (PC) Note 1 Status after Reset The contents of reset vector tables (0000H and 0001H) are set.
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CHAPTER 24 RESET FUNCTION Table 24-1.
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CHAPTER 25 ROM CORRECTION 25.1 ROM Correction Functions The µPD78058F, 78058FY Subseries can replace part of a program in the mask ROM with a program in the internal expansion RAM. Instruction bugs found in the mask ROM can be avoided, and program flow can be changed by using the ROM correction. The ROM correction can correct two places (max.) of the internal ROM (program). Caution The ROM correction cannot be emulated by the in-circuit emulator (IE-78000-R, IE-78000-R-A, IE-78K0-NS and IE-78001-R-A).
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CHAPTER 25 ROM CORRECTION (1) Correction address registers 0 and 1 (CORAD0, CORAD1) These registers set the start address (correction address) of the instruction(s) to be corrected in the mask ROM. The ROM correction corrects two places (max.) of the program. Addresses are set to two registers, CORAD0 and CORAD1. If only one place needs to be corrected, set the address to either of the registers. CORAD0 and CORAD1 are set with a 16-bit memory manipulation instruction.
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CHAPTER 25 ROM CORRECTION 25.3 ROM Correction Control Registers The ROM correction is controlled with the correction control register (CORCN). (1) Correction control register (CORCN) This register controls whether or not the correction branch request signal is generated when the fetch address matches the correction address set in correction address registers 0 and 1. The correction control register consists of correction enable flags (COREN0, COREN1) and correction status flags (CORST0, CORST1).
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CHAPTER 25 25.4 ROM CORRECTION ROM Correction Application (1) Store the correction address and instruction after correction (patch program) to nonvolatile memory (such as EEPROMTM) outside the microcontroller. When two places should be corrected, store the branch destination judgment program as well. The branch destination judgment program checks which one of the addresses set to correction address register 0, 1 (CORAD0 or CORAD1) generates the correction branch. Figure 25-4.
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CHAPTER 25 ROM CORRECTION (2) Assemble in advance the initialization routine as shown in Figure 25-6 to correct the program. Figure 25-6. Initialization Routine Initialization ROM correction Is ROM correction used ? Note No Yes Load the contents of external nonvolatile memory into internal expansion RAM Correction address register setting ROM correction enabled Main program Note Whether the ROM correction is used or not should be judged by the port input level.
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CHAPTER 25 ROM CORRECTION Figure 25-7.
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CHAPTER 25 25.5 ROM CORRECTION ROM Correction Example The example of ROM correction when the instruction at address 1000H “ADD A, #1” is changed to “ADD A, #2” is as follows. Figure 25-8.
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CHAPTER 25 25.6 ROM CORRECTION Program Execution Flow Figures 25-9 and 25-10 show the program transition diagrams when the ROM correction is used. Figure 25-9.
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CHAPTER 25 ROM CORRECTION Figure 25-10.
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CHAPTER 25 25.7 ROM CORRECTION Cautions on ROM Correction (1) Address values set in correction address registers 0 and 1 (CORAD0 and CORAD1) must be addresses where instruction codes are stored. (2) Correction address registers 0 and 1 (CORAD0 and CORAD1) should be set when the correction enable flags (COREN0, COREN1) are “0” (when correction branch processing is disabled).
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CHAPTER 26 µPD78P058F, 78P058FY The µPD78P058F and 78P058FY are products which have one time PROM incorporated into them, which it is only possible to write to once. The differences between PROM products (µPD78P058F and 78P058FY) and ROM products (µPD78056F, 78056FY, 78058F and 78058FY) are shown in Table 26-1. Table 26-1.
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CHAPTER 26 µPD78P058F, 78P058FY 26.1 Memory Size Switching Register In the µPD78P058F and 78P058FY, internal memory can be selected through the memory size select register (IMS). The same memory mapping as that of mask ROM versions that have a different internal memory can be done by setting IMS. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Figure 26-1.
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CHAPTER 26 µPD78P058F, 78P058FY 26.2 Internal Expansion RAM Size Switching Register The internal expansion RAM size of the µPD78P058F and 78P058FY can be defined using the internal expansion RAM size switching register (IXS), thus enabling memory mapping that is the same as that of mask ROM products with different internal expansion RAM. The IXS is set by an 8-bit memory manipulation instruction. RESET signal input sets IXS to 0AH. Figure 26-2.
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CHAPTER 26 µPD78P058F, 78P058FY 26.3 PROM Programming The µPD78P058F and 78P058FY include on-chip PROM in a 60 Kbyte configuration as program memory. To write a program into the µ PD78P058F or 78P058FY PROM, make the device enter the PROM programming mode by setting the levels of the V PP and RESET pins as specified. For the connection of unused pins, see paragraph (2) PROM programming mode in section 1.5 or 2.5 Pin Configuration (Top View).
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CHAPTER 26 µPD78P058F, 78P058FY (3) Standby mode Setting CE to H sets the standby mode. In this mode, data output becomes high impedance irrespective of the status of OE. (4) Page data latch mode Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode. In this mode, 1-page 4-byte data is latched in the internal address/data latch circuit.
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CHAPTER 26 µPD78P058F, 78P058FY 26.3.2 PROM write procedure Figure 26-3. Page Program Mode Flowchart Start Address = G VDD = 6.5 V, VPP = 12.5 V Remark: G = Start address X=0 N = Last address of program Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Address = Address + 1 Latch X=X+1 No X = 10? 0.1-ms program pulse Yes Fail Verify 4 Bytes Pass No Address = N? Yes VDD = 4.5 to 5.
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CHAPTER 26 µPD78P058F, 78P058FY Figure 26-4. Page Program Mode Timing Page Data Latch Page Program Program Verify A2 to A16 A0, A1 Hi-Z D0 to D7 Data Input Data Output VPP VPP VDD VDD+1.
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CHAPTER 26 µPD78P058F, 78P058FY Figure 26-5. Byte Program Mode Flowchart Start Remark: Address = G G = Start address N = Last address of program VDD = 6.5 V, VPP = 12.5 V X=0 X=X+1 No X = 10? 0.1-ms program pulse Address = Address + 1 Verify Yes Fail Pass No Address = N? Yes VDD = 4.5 to 5.
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CHAPTER 26 µPD78P058F, 78P058FY Figure 26-6. Byte Program Mode Timing Program Program Verify A0 to A16 D0 to D7 Data Input Data Output VPP VPP VDD VDD+1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL Cautions 1. Be sure to apply VDD before applying VPP, and remove it after removing VPP. 2. VPP must not exceed +13.5 V including overshoot voltage. 3. Disconnecting/inserting the device from/to the on-board socket while +12.
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CHAPTER 26 µPD78P058F, 78P058FY 26.3.3 PROM read procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the VPP pin. Unused pins are handled as shown in paragraph, (2) PROM programming mode in section 1.5 or 2.5 Pin Configuration (Top View). (2) Supply +5 V to the VDD and VPP pins. (3) Input the address of data to be read to pins A0 through A16. (4) Read mode is entered.
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CHAPTER 26 µPD78P058F, 78P058FY 26.4 Screening of One-Time PROM Versions One-time PROM versions cannot be fully tested by NEC before shipment due to the structure of one-time PROM. Therefore, after users have written data into the PROM, screening should be implemented by user: that is, store devices at high temperature for one day as specified below, and verify their contents after the devices have returned to room temperature.
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[MEMO] 548
PAGE 549
CHAPTER 27 INSTRUCTION SET This chapter describes each instruction set of the µPD78058F and 78058FY Subseries as list table. For details of its operation and operation code, refer to the separate document 78K/0 Series USER’S MANUAL—Instructions (U12326E).
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CHAPTER 27 INSTRUCTION SET 27.1 Legends Used in Operation List 27.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and must be described as they are.
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CHAPTER 27 INSTRUCTION SET 27.1.
PAGE 552
CHAPTER 27 INSTRUCTION SET 27.
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CHAPTER 27 Clock Instruction Mnemonic Group 16-bit data transfer MOVW Operands Byte Flag Operation Z AC CY 6 – rp ← word saddrp, #word 4 8 10 (saddrp) ← word sfrp, #word 4 – 10 sfrp ← word AX, saddrp 2 6 8 AX ← (saddrp) saddrp, AX 2 6 8 (saddrp) ← AX AX, sfrp 2 – 8 AX ← sfrp 2 – 8 sfrp ← AX AX, rp Note 3 1 4 – AX ← rp rp, AX Note 3 1 4 – rp ← AX 3 10 12 + 2n AX ← (addr16) 3 10 12 + 2m (addr16) ← AX 1 4 – AX ↔ rp 2 4 – A, CY ← A + byte × × ×
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CHAPTER 27 Clock Instruction Mnemonic Group Operands Byte A, #byte saddr, #byte 4 – A, CY ← A – byte × × × 3 6 8 (saddr), CY ← (saddr) – byte × × × 4 – A, CY ← A – r × × × 4 – r, CY ← r – A × × × A, saddr 2 4 5 A, CY ← A – (saddr) × × × A, !addr16 3 8 9+n A, CY ← A – (addr16) × × × A, [HL] 1 4 5+n A, CY ← A – (HL) × × × A, [HL + byte] 2 8 9+n A, CY ← A – (HL + byte) × × × A, [HL + B] 2 8 9+n A, CY ← A – (HL + B) × × × A, [HL + C] 2 8
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CHAPTER 27 Clock Instruction Mnemonic Group Operands Byte A, #byte saddr, #byte 4 – A ← A byte × 3 6 8 (saddr) ← (saddr) byte × 4 – A←A r × 4 – r←r A × A, saddr 2 4 5 A ← A (saddr) × A, !addr16 3 8 9+n A ← A (addr16) × A, [HL] 1 4 5+n A ← A (HL) × A, [HL + byte] 2 8 9+n A ← A (HL + byte) × A, [HL + B] 2 8 9+n A ← A (HL + B) × A, [HL + C] 2 8 9+n A ← A (HL + C) × A, #byte 2 4 – A←A saddr, #byte 3 6 8 (saddr) ← (saddr) 2 4 – A←A 2 4 –
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CHAPTER 27 Clock Instruction Mnemonic Group 16-bit operation Multiply/ divide Bit manipulate Byte Note 1 Note 2 Flag Operation Z AC CY AX, #word 3 6 – AX, CY ← AX + word × × × SUBW AX, #word 3 6 – AX, CY ← AX – word × × × CMPW AX, #word 3 6 – AX – word × × × MULU X 2 16 – AX ← A × X DIVUW C 2 25 – AX (Quotient), C (Remainder) ← AX ÷ C r 1 2 – r←r+1 × × saddr 2 4 6 (saddr) ← (saddr) + 1 × × r 1 2 – r←r–1 × × saddr 2 4 6 (saddr) ← (saddr)
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CHAPTER 27 Clock Instruction Mnemonic Group AND1 OR1 Bit manipulate XOR1 SET1 CLR1 SET1 INSTRUCTION SET Operands Byte Note 1 Note 2 Flag Operation Z AC CY CY, saddr.bit 3 6 7 CY ← CY (saddr.bit) × CY, sfr.bit 3 – 7 CY ← CY sfr.bit × CY, A.bit 2 4 – CY ← CY A.bit × CY, PSW.bit 3 – 7 CY ← CY PSW.bit × CY, [HL].bit 2 6 7+n CY ← CY (HL).bit × CY, saddr.bit 3 6 7 CY ← CY (saddr.bit) × CY, sfr.bit 3 – 7 CY ← CY sfr.bit × CY, A.bit 2 4 – CY ← CY A.
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CHAPTER 27 INSTRUCTION SET Clock Instruction Mnemonic Group Operands Byte Note 1 Note 2 !addr16 3 7 – (SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L, PC ← addr16, SP ← SP – 2 CALLF !addr11 2 5 – (SP – 1) ← (PC + 2)H, (SP – 2) ← (PC + 2)L, PC15 – 11 ← 00001, PC10 – 0 ← addr11, SP ← SP – 2 1 6 – (SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L, PCH ← (00000000, addr5 + 1), PCL ← (00000000, addr5), SP ← SP – 2 BRK 1 6 – (SP – 1) ← PSW, (SP – 2) ← (PC + 1)H, (SP – 3) ← (PC + 1)L, PCH ← (003FH),
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CHAPTER 27 Clock Instruction Mnemonic Group BT Operands Byte Note 1 Note 2 Flag Operation Z AC CY saddr.bit, $addr16 3 8 9 PC ← PC + 3 + jdisp8 if(saddr.bit) = 1 sfr.bit, $addr16 4 – 11 PC ← PC + 4 + jdisp8 if sfr.bit = 1 A.bit, $addr16 3 8 – PC ← PC + 3 + jdisp8 if A.bit = 1 PSW.bit, $addr16 3 – 9 PC ← PC + 3 + jdisp8 if PSW.bit = 1 [HL].bit, $addr16 3 10 11 + n PC ← PC + 3 + jdisp8 if (HL).bit = 1 saddr.bit, $addr16 4 10 11 PC ← PC + 4 + jdisp8 if(saddr.bit) = 0 sfr.
PAGE 560
CHAPTER 27 INSTRUCTION SET 27.
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CHAPTER 27 INSTRUCTION SET Second Operand [HL + byte] rNote sfr ADD MOV MOV MOV MOV ADDC SUB XCH ADD XCH XCH ADD XCH ADD SUBC AND ADDC SUB ADDC ADDC SUB SUB ADDC ADDC SUB SUB OR XOR SUBC AND SUBC SUBC AND AND SUBC SUBC AND AND CMP OR XOR OR XOR OR XOR OR XOR OR XOR CMP CMP CMP CMP CMP #byte A saddr !addr16 PSW [DE] [HL] MOV MOV MOV ROR XCH XCH ADD XCH ADD ROL RORC First Operand A r MOV MOV [HL + B] $addr16 [HL + C] 1 None ROLC MOV ADD INC DEC ADDC SU
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CHAPTER 27 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand #word AX rpNote sfrp saddrp !addr16 SP None First Operand AX ADDW MOVW SUBW XCHW MOVW MOVW MOVW MOVW CMPW rp MOVW MOVWNote INCW DECW PUSH POP sfrp MOVW MOVW saddrp MOVW MOVW !addr16 MOVW SP MOVW Note MOVW Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand A.bit sfr.bit saddr.
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CHAPTER 27 INSTRUCTION SET (4) Call/instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand AX !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP 563
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[MEMO] 564
PAGE 565
APPENDIX A. DIFFERENCES AMONG µPD78054, 78058F, AND 780058 SUBSERIES The major differences among the µPD78054, 78058F, and 780058 Subseries are shown in Table A-1. Table A-1. Major Differences Among µPD78054, 78058F, and 780058 Subseries (1/2) µPD78054 Subseries Product Name µPD78058F Subseries µPD780058 Subseries Item EMI noise countermeasure No Yes Yes Power-supply voltage VDD = 2.0 to 6.0 V VDD = 2.7 to 6.0 V VDD = 1.8 to 5.
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APPENDIX A. DIFFERENCES AMONG µPD78054, 78058F, AND 780058 SUBSERIES Table A-1. Major Differences Among µPD78054, 78058F, and 780058 Subseries (2/2) Product Name µPD78054 Subseries µPD78058F Subseries µPD780058 Subseries Item Emulation probe EP-78230GC-R, EP-780058GC-R, EP-78054GK-R EP-780058GK-R Device file DF78054 DF780058 Package • 80-pin plastic QFP (14 × 14 mm, Resin • 80-pin plastic QFP (14 × 14 mm, Resin • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.
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APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the µPD78058F and 78058FY Subseries. Figure B-1 shows the configuration of the development tools.
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APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tool Configuration (1/2) (1) When using in-circuit emulator IE-78K0-NS Debugging tools Language processing software • Assembler package • C compiler package • C library source file • Device file • System simulator • Integrated debugger • Device file Tool for PROM writing Embeded software • PG-1500 controller • Real-time OS • OS Host machine (PC) Interface adapter, PC card interface, etc.
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APPENDIX B DEVELOPMENT TOOLS Figure B-1.
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APPENDIX B DEVELOPMENT TOOLS B.1 Language Processing Software RA78K/0 Assembler package Program that converts program written in mnemonic into object codes that can be executed by microcontroller. In addition, automatic functions to generate symbol table and optimize branch instructions are also provided. Used in combination with optional device file (DF78054). This assembler package is a DOS-based application.
PAGE 571
APPENDIX B DEVELOPMENT TOOLS B.2 PROM Programming Tool B.2.1 Hardware PG-1500 This is a PROM programmer capable of programming the single-chip microcontroller with on-chip PROM programmer PROM by manipulating from the stand-alone or host machine through connection of the separately available programmer adapter and the attached board. It can also program separate PROM ICs with a capacity from 256 Kbits to 4 Mbits.
PAGE 572
APPENDIX B DEVELOPMENT TOOLS B.3 Debugging Tool B.3.1 Hardware (1/2) (1) When using in-circuit emulator IE-78K0-NS IE-78K0-NSNote The in-circuit emulator serves to debug hardware and software when In-circuit emulator developing application systems using a 78K/0 Series product. It corresponds to integrated debugger (ID78K0-NS). This emulator should be used in combination with power supply unit, emulation probe, and interface adapter which is required to connect this emulator to the host machine.
PAGE 573
APPENDIX B DEVELOPMENT TOOLS B.3.1 Hardware (2/2) (2) When using in-circuit emulator IE-78001-R-A IE-78001-R-ANote 1 The in-circuit emulator serves to debug hardware and software when In-circuit emulator developing application systems using a 78K/0 Series product. It corresponds to integrated debugger (ID78K0). This emulator should be used in combination with emulation probe, and interface adapter which is required to connect this emulator to the host machine.
PAGE 574
APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (1/2) SM78K0 This simulator can debug target system at C source level or assembler level while System simulator simulating operation of target system on host machine. SM78K0 runs on Windows. By using SM78K0, logic and performance of application can be verified without in-circuit emulator independently of hardware development, so that development efficiency and software quality can be improved. This simulator is used with optional device file (DF78054).
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APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (2/2) ID78K0-NSNote This is a control program that is used to debug the 78K/0 Series. Integrated debugger It uses Windows on a personal computer and OSF/MotifTM on EWS as a (Supports the in-circuit graphical user interface, and has the appearance and operability conforming emulator IE-78K0-NS) to these interfaces.
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APPENDIX B DEVELOPMENT TOOLS B.4 OS for IBM PC The following OSs for the IBM PC are supported. Table B-1. OS for IBM PC OS PC DOS Version Ver. 5.02 to Ver. 6.3 J6.1/VNote to J6.3/VNote IBM DOSTM J5.02/VNote MS-DOS Ver. 5.0 to Ver. 6.22 5.0/VNote to 6.2/VNote Note Only English mode is supported. Caution Although Ver. 5.0 or later have a task swap function, this function cannot be used with this software. B.
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APPENDIX B DEVELOPMENT TOOLS Drawing and Footprint for Conversion Socket (EV-9200GC-80) Figure B-2. EV-9200GC-80 Drawings (For Reference Only) Based on EV-9200GC-80 (1) Package drawing (in mm) A E M B N O L K S J C D R F EV-9200GC-80 Q 1 No.1 pin index P G H I EV-9200GC-80-G1E ITEM MILLIMETERS INCHES A 18.0 0.709 B 14.4 0.567 C 14.4 0.567 D 18.0 0.709 E 4-C 2.0 4-C 0.079 F 0.8 0.031 G 6.0 0.236 H 16.0 0.63 I 18.7 0.736 J 6.0 0.236 K 16.0 0.63 L 18.
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APPENDIX B DEVELOPMENT TOOLS Figure B-3. EV-9200GC-80 Footprints (For Reference Only) Based on EV-9200GC-80 (2) Pad drawing (in mm) G J H D E F K I L C B A EV-9200GC-80-P1 ITEM INCHES A 19.7 0.776 B 15.0 0.591 C +0.003 0.65±0.02 × 19=12.35±0.05 0.026+0.002 –0.001 × 0.748=0.486 –0.002 D +0.003 0.65±0.02 × 19=12.35±0.05 0.026+0.002 –0.001 × 0.748=0.486 –0.002 E 15.0 0.591 F 19.7 0.776 G 6.0 ± 0.05 0.236 +0.004 –0.003 H 6.0 ± 0.05 0.236 +0.004 –0.003 I 0.35 ± 0.02 0.
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APPENDIX B DEVELOPMENT TOOLS Drawing of Conversion Adapter (TGK-080SDW) Figure B-4. TGK-080SDW Drawings (For Reference) (unit: mm) Reference diagram: TGK-080SDW Package dimension (unit: mm) A B C T U V D R Q Q Q M2 screw G F E c e b H P a S O O O N K I JJJ d Z W X Y L L LM g v f k u r t j s i q h p l Protrusion : 4 places n o m ITEM A B C D MILLIMETERS 18.0 11.77 0.5x19=9.5 INCHES ITEM MILLIMETERS a 0.5x19=9.5±0.10 0.25 0.020x0.748=0.374±0.004 0.010 g φ 5.3 φ 5.3 φ 1.
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APPENDIX C EMBEDDED SOFTWARE This chapter describes the embedded software that is available for the µPD78058F and 78058FY Subseries to allow users to develop and maintain application programs for these subseries.
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APPENDIX C EMBEDDED SOFTWARE C.1 Real-time OS (1/2) RX78K/0 RX78K/0 is real-time OS conforming to µITRON specifications. Real-time OS Tool (configurator) that generates nucleus of RX78K/0 and plural information tables is supplied. Used in combination with an optional assembler package (RA78K/0) and device file (DF78054). RX78K/0 is a DOS-based application. Therefore run the RX78K/0 from the DOS prompt under Windows.
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APPENDIX C EMBEDDED SOFTWARE Real-time OS (2/2) MX78K0 µITRON-specification subset OS. Nucleus of MX78K0 is supplied. OS This OS performs task management, event management, and time management. It controls the task execution sequence for task management and selects the task to be executed next. MX78K0 is a DOS-based application. Therefore run the MX78K0 from the DOS prompt under Windows.
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APPENDIX D REGISTER INDEX D.1 Register Index (Register Name) [A] A/D conversion result register (ADCR) ............................................................................................................. 264 A/D converter input select register (ADIS) ....................................................................................................... 267 A/D converter mode register (ADM) ............................................................................................................
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APPENDIX D REGISTER INDEX Interrupt request flag register 1L (IF1L) ................................................................................................... 483, 503 Interrupt timing specify register (SINT) ........................................................................... 298, 316, 351, 360, 370 [K] Key return mode register (KRM) ..............................................................................................................
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APPENDIX D REGISTER INDEX [S] Sampling clock select register (SCS) ......................................................................................................... 186, 488 Serial bus interface control register (SBIC) ............................................ 296, 302, 314, 333, 349, 355, 360, 369 Serial I/O shift register 0 (SIO0) .................................................................................................................290, 342 Serial I/O shift register 1 (SIO1) .......
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APPENDIX D REGISTER INDEX CR00: Capture/compare register 00 .......................................................................................................... 177 CR01: Capture/compare register 01 .......................................................................................................... 177 CR10: Compare registers 10 ..................................................................................................................... 219 CR20: Compare registers 20 ...........
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APPENDIX D REGISTER INDEX PCC: Processor clock control register ..................................................................................................... 157 PM0: Port mode register 0 .............................................................................................................. 130, 146 PM12: Port mode register 12 .................................................................................................... 130, 146, 474 PM13: Port mode register 13 ................
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APPENDIX D REGISTER INDEX TOC1: 8-bit timer output control register ................................................................................................... 223 TXS: Transmit shift register ..................................................................................................................... 437 [W] WDTM: 590 Watchdog timer mode register .......................................................................................................
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APPENDIX E REVISION HISTORY Major revisions by edition and revised chapters are shown below. Edition 2nd Major Revisions from Previous Edition Revised Chapters The following products have already been developed: µPD78056GC-×××-8BT, 78058FGC-×××-8BT, 78P058FGC-8BT, 78056FYGC-×××-8BT, 78058FYGC-×××-88BT Throughout The block diagrams of the following ports were changed.
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