Single-Chip Microcontrollers User's Manual

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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES)
SCL
CLC
CMDT
CLD
SDA0(SDA1)
17.4.5 Cautions on use of I
2
C bus mode
(1) Start condition output (master)
The SCL pin normally outputs a low-level signal when no serial clock is output. It is necessary to change
the SCL pin to high in order to output a start condition signal. To set pin SCL to high level, set bit 3 (CLC)
of the interrupt timing specification register (SINT) to 1.
After setting CLC, clear CLC to 0 and return the SCL pin to low. If CLC remains 1, no serial clock is
output.
To output the start condition or stop condition from the master, set CLC to “1”, then make sure that bit 6
(CLD) of SINT is “1”. This procedure must be followed because there is a possibility that the slave has set
SCL to low level (wait status).
Figure 17-24. Start Condition Output