Electronics America 8-Bit Single-Chip Microcontrollers User's Manual

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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (

PD78054 Subseries)

Note Busy mode can be cleared by start of serial interface transfer. However, BSYE flag is not cleared

to 0.

Remark CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)

ACKD Acknowledge Detection

Clear Conditions (ACKD = 0)

• SCK0 fall immediately after the busy mode is

released during the transfer start instruction execution.

• When CSIE0 = 0

• When RESET input is applied

Set Conditions (ACKD = 1)

• When acknowledge signal (ACK) is detected at the

rising edge of SCK0 clock after completion of

transfer

BSYE Synchronizing Busy Signal Output Control

Disables busy signal which is output in synchronization with the falling edge of SCK0 clock just after

execution of the instruction to be cleared to (0) (sets READY status).

R/W

Note

1 Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal.