Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate OR gate 74AHC TSSOP 8

1. General description

The 74AHC2G32; 74AHCT2G32 is a high-speed Si-gate CMOS device.

The 74AHC2G32; 74AHCT2G32 provides two 2-input OR gates.

2. Features and benefits

 Symmetrical output impedance

 High noise immunity

 ESD protection:

 HBM JESD22-A114E exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 CDM JESD22-C101C exceeds 1000 V

 Low power dissipation

 Balanced propagation delays

 Multiple package options

 Specified from 40 Cto+85C and from 40 Cto+125C

3. Ordering information

74AHC2G32; 74AHCT2G32

Dual 2-input OR gate

Rev. 3 — 14 May 2013 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74AHC2G32DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; body

width 3 mm; lead length 0.5 mm

SOT505-2

74AHCT2G32DP

74AHC2G32DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads;

body width 2.3 mm

SOT765-1

74AHCT2G32DC

74AHC2G32GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads;

8 terminals; body 3  2  0.5 mm

SOT996-2

74AHCT2G32GD

Summary of content (14 pages)

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74AHC2G32; 74AHCT2G32 Dual 2-input OR gate Rev. 3 — 14 May 2013 Product data sheet 1. General description The 74AHC2G32; 74AHCT2G32 is a high-speed Si-gate CMOS device. The 74AHC2G32; 74AHCT2G32 provides two 2-input OR gates. 2.
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74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate 4. Marking Table 2. Marking Type number Marking code[1] 74AHC2G32DP A32 74AHCT2G32DP C32 74AHC2G32DC A32 74AHCT2G32DC C32 74AHC2G32GD A32 74AHCT2G32GD C32 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1 1A 2 1B 5 2A ≥1 7 ≥1 3 2 1Y 7 2Y 3 B 6 2B 5 Y 6 A Fig 1. mna166 mna734 mna733 Logic symbol Fig 2. IEC logic symbol Fig 3.
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74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate 6.2 Pin description Table 3. Pin description Symbol Pin Description 1A, 2A 1, 5 data input 1B, 2B 2, 6 data input GND 4 ground (0 V) 1Y, 2Y 7, 3 data output VCC 8 supply voltage 7. Functional description Table 4. Function table[1] Input Output nA nB nY L L L L H H H L H H H H [1] H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 5.
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74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74AHC2G32 Min Typ 74AHCT2G32 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V VI input voltage 0 - 5.5 0 - 5.
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74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min Typ 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max 74AHCT2G32 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V VOH HIGH-level VI = VIH or VIL; VCC = 4.
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74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate Table 8. Dynamic characteristics …continued GND = 0 V; for test circuit see Figure 7. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 3.3 6.9 1.0 8.0 1.0 9.0 ns - 4.8 7.9 1.0 9.0 1.0 10.0 ns - 17 - - - - - pF 74AHCT2G32 propagation delay tpd nA, nB to nY; see Figure 6 [1] [3] VCC = 4.5 V to 5.
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4AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT CL RT 001aad983 Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 7.
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74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.
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74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.
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74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm B D SOT996-2 A E A A1 detail X terminal 1 index area e1 1 4 8 5 C C A B C v w b e L1 y y1 C L2 L X 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit(1) mm max nom min A A1 b 0.05 0.35 D E 2.1 3.1 0.5 0.00 0.15 1.9 e e1 0.5 1.5 2.9 L L1 L2 0.5 0.15 0.6 0.3 0.05 0.4 v 0.1 w y 0.
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74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate 14. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT2G32 v.
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74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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74AHC2G32; 74AHCT2G32 NXP Semiconductors Dual 2-input OR gate Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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NXP Semiconductors 74AHC2G32; 74AHCT2G32 Dual 2-input OR gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . .