Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Buffer, driver TSSOP 14

1. General description

The 74AHC125; 74AHCT125 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). They are speciﬁed in compliance with JEDEC

standard JESD7-A.

The 74AHC125; 74AHCT125 provides four non-inverting buffer/line drivers with 3-state

outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH

at nOE causes the outputs to assume a high-impedance OFF-state.

The 74AHC125; 74AHCT125 is identical to the 74AHC126; 74AHCT126 but has active

LOW enable inputs.

2. Features

■ Balanced propagation delays

■ All inputs have a Schmitt-trigger action

■ Inputs accepts voltages higher than V

■ For 74AHC125 only: operates with CMOS input levels

■ For 74AHCT125 only: operates with TTL input levels

■ ESD protection:

◆ HBM JESD22-A114E exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V

◆ CDM JESD22-C101C exceeds 1000 V

■ Multiple package options

■ Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

3. Ordering information

74AHC125; 74AHCT125

Quad buffer/line driver; 3-state

Rev. 04 — 11 January 2008 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74AHC125D −40 °C to +125 °C SO14 plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74AHCT125D

74AHC125PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74AHCT125PW

74AHC125BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

SOT762-1

74AHCT125BQ

Summary of content (15 pages)

PAGE 1
74AHC125; 74AHCT125 Quad buffer/line driver; 3-state Rev. 04 — 11 January 2008 Product data sheet 1. General description The 74AHC125; 74AHCT125 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74AHC125; 74AHCT125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE).
PAGE 2
74AHC125; 74AHCT125 NXP Semiconductors Quad buffer/line driver; 3-state 4. Functional diagram 1Y 2 1A 1 1OE 2 2Y 5 2A 4 2OE 3 1 6 1 3 EN1 5 6 4 9 3A 3Y 8 9 10 3OE 12 4A 8 10 4Y 11 nY nA 12 11 13 4OE 13 nOE mna229 mna228 Fig 1. Logic symbol mna227 Fig 2. IEC logic symbol Fig 3. Logic diagram (one buffer) 5. Pinning information 5.
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74AHC125; 74AHCT125 NXP Semiconductors Quad buffer/line driver; 3-state 5.2 Pin description Table 2.
PAGE 4
74AHC125; 74AHCT125 NXP Semiconductors Quad buffer/line driver; 3-state Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
PAGE 5
74AHC125; 74AHCT125 NXP Semiconductors Quad buffer/line driver; 3-state Table 6. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH VOL 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = −50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = −50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = −4.
PAGE 6
74AHC125; 74AHCT125 NXP Semiconductors Quad buffer/line driver; 3-state Table 6. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max ∆ICC additional per input pin; supply current VI = VCC − 2.1 V; IO = 0 A; other pins at VCC or GND; VCC = 4.5 V to 5.5 V - - 1.35 - 1.5 - 1.5 mA CI input capacitance - 3.
PAGE 7
4AHC125; 74AHCT125 NXP Semiconductors Quad buffer/line driver; 3-state Table 7. Dynamic characteristics …continued GND = 0 V; For test circuit see Figure 8. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max CL = 15 pF - 3.0 5.5 1.0 6.5 1.0 7.0 ns CL = 50 pF - 4.3 7.5 1.0 8.5 1.0 9.5 ns - 3.4 5.1 1.0 6.0 1.0 6.5 ns - 4.9 7.3 1.0 8.3 1.0 9.5 ns - 4.5 6.8 1.0 8.0 1.0 8.5 ns - 6.5 8.8 1.0 10.0 1.
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74AHC125; 74AHCT125 NXP Semiconductors Quad buffer/line driver; 3-state VI nOE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs disabled outputs enabled mna362 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Enable and disable times Table 8. Measurement points Type Input Output VM VM VX VY 74AHC125 0.5VCC 0.
PAGE 9
74AHC125; 74AHCT125 NXP Semiconductors Quad buffer/line driver; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC PULSE GENERATOR VI VO RL S1 open DUT RT CL 001aad983 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch.
PAGE 10
74AHC125; 74AHCT125 NXP Semiconductors Quad buffer/line driver; 3-state 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.
PAGE 11
74AHC125; 74AHCT125 NXP Semiconductors Quad buffer/line driver; 3-state TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.
PAGE 12
74AHC125; 74AHCT125 NXP Semiconductors Quad buffer/line driver; 3-state DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b 1 0.05 0.00 0.30 0.
PAGE 13
74AHC125; 74AHCT125 NXP Semiconductors Quad buffer/line driver; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor LSTTL Low-power Schottky Transistor-Transistor Logic ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model CDM Charge-Device Model TTL Transistor-Transistor Logic 14. Revision history Table 11.
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74AHC125; 74AHCT125 NXP Semiconductors Quad buffer/line driver; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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NXP Semiconductors 74AHC125; 74AHCT125 Quad buffer/line driver; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . .