Datasheet

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1. General description

The 74AVCH8T245 is an 8-bit, dual supply transceiver that enables bidirectional level

translation. It features two 8-bit input-output ports (An and Bn), a direction control input

(DIR), a output enable input (OE

) and dual supply pins (V

CC(A)

and V

CC(B)

). Both V

CC(A)

and V

CC(B)

can be supplied at any voltage between 0.8 V and 3.6 V making the device

suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V,

2.5 V and 3.3 V). Pins An, OE

and DIR are referenced to V

CC(A)

and pins Bn are

referenced to V

CC(B)

. A HIGH on DIR allows transmission from An to Bn and a LOW on

DIR allows transmission from Bn to An. The output enable input (OE

) can be used to

disable the outputs so the buses are effectively isolated.

The device is fully specified for partial power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing any damaging backflow current through the

device when it is powered down. In suspend mode when either V

CC(A)

or V

CC(B)

are at

GND level, both An and Bn outputs are in the high-impedance OFF-state. The bus-hold

circuitry on the powered-up side always stays active.

The 74AVCH8T245 has active bus hold circuitry which is provided to hold unused or

floating data inputs at a valid logic level. This feature eliminates the need for external

pull-up or pull-down resistors.

2. Features and benefits

 Wide supply voltage range:

 V

CC(A)

: 0.8 V to 3.6 V

 V

CC(B)

: 0.8 V to 3.6 V

 Complies with JEDEC standards:

 JESD8-12 (0.8 V to 1.3 V)

 JESD8-11 (0.9 V to 1.65 V)

 JESD8-7 (1.2 V to 1.95 V)

 JESD8-5 (1.8 V to 2.7 V)

 JESD8-B (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114E Class 3B exceeds 8000 V

 MM JESD22-A115-A exceeds 200 V

 CDM JESD22-C101C exceeds 1000 V

 Maximum data rates:

 380 Mbit/s ( 1.8 V to 3.3 V translation)

 260 Mbit/s ( 1.1 V to 3.3 V translation)

74AVCH8T245

8-bit dual supply translating transceiver with configurable

voltage translation; 3-state

Rev. 5 — 27 December 2012 Product data sheet

Summary of content (25 pages)

PAGE 1
74AVCH8T245 8-bit dual supply translating transceiver with configurable voltage translation; 3-state Rev. 5 — 27 December 2012 Product data sheet 1. General description The 74AVCH8T245 is an 8-bit, dual supply transceiver that enables bidirectional level translation. It features two 8-bit input-output ports (An and Bn), a direction control input (DIR), a output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.
PAGE 2
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state         260 Mbit/s ( 1.1 V to 2.5 V translation)  210 Mbit/s ( 1.1 V to 1.8 V translation)  150 Mbit/s ( 1.1 V to 1.5 V translation)  100 Mbit/s ( 1.1 V to 1.2 V translation) Suspend mode Bus hold on data inputs Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.
PAGE 3
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state DIR OE A1 B1 VCC(A) VCC(B) to other seven channels Fig 2. 001aai473 Logic diagram (one channel) 5. Pinning information 5.
PAGE 4
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state 5.2 Pin description Table 2.
PAGE 5
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
PAGE 6
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state Table 6. Typical static characteristics at Tamb = 25 C[1][2] …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter IOZ Conditions OFF-state output current IOFF power-off leakage current Min Typ Max Unit A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 3.6 V [7] - 0.5 2.5 A suspend mode A port; VO = 0 V or VCCO; VCC(A) = 3.
PAGE 7
4AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state Table 7. Static characteristics …continued[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIL 40 C to +85 C Conditions LOW-level data input input voltage VCCI = 0.8 V 40 C to +125 C Min Max Min Max Unit - 0.30VCCI - 0.30VCCI V VCCI = 1.1 V to 1.95 V - 0.35VCCI - 0.35VCCI V VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V VCCI = 3.0 V to 3.
PAGE 8
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state Table 7. Static characteristics …continued[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter IBHH 40 C to +85 C Conditions bus hold A or B port HIGH current VI = 0.91 V; VCC(A) = VCC(B) = 1.
PAGE 9
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state Table 7. Static characteristics …continued[1][2] At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter ICC supply current 40 C to +85 C Conditions 40 C to +125 C Unit Min Max Min Max VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V - 10 - 55 A VCC(A) = 1.1 V to 3.6 V; VCC(B) = 1.1 V to 3.6 V - 8 - 50 A VCC(A) = 3.
PAGE 10
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state 10. Dynamic characteristics Table 9. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6 Symbol Parameter Conditions VCC(B) 0.8 V tpd [1] 1.8 V 2.5 V 3.3 V 14.4 7.0 6.2 6.0 5.9 6.0 ns Bn to An 14.4 12.4 12.1 11.9 11.8 11.8 ns OE to An 16.2 16.2 16.2 16.2 16.
PAGE 11
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C [1][2] Voltages are referenced to GND (ground = 0 V). Symbol Parameter power dissipation capacitance CPD [1] Conditions VCC(A) = VCC(B) Unit 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V A port: (direction An to Bn); output enabled 0.2 0.2 0.2 0.3 0.4 0.5 pF A port: (direction An to Bn); output disabled 0.2 0.2 0.2 0.3 0.4 0.
PAGE 12
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state Table 12. Dynamic characteristics for temperature range 40 C to +85 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6. Symbol Parameter Conditions VCC(B) Unit 1.2 V  0.1 V 1.5 V  0.1 V 1.8 V  0.15 V 2.5 V  0.2 V 3.3 V  0.3 V Min Max Min Max Min Max Min Max Min Max 0.5 9.0 0.5 6.7 0.5 5.8 0.5 4.9 0.5 4.8 VCC(A) = 1.
PAGE 13
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state Table 13. Dynamic characteristics for temperature range 40 C to +125 C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6 Symbol Parameter Conditions VCC(B) Unit 1.2 V  0.1 V 1.5 V  0.1 V 1.8 V  0.15 V 2.5 V  0.2 V 3.3 V  0.3 V Min Max Min Max Min Max Min Max Min Max 0.5 9.9 0.5 7.4 0.5 6.4 0.5 5.4 0.5 5.3 VCC(A) = 1.
PAGE 14
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state 11. Waveforms VI VM An, Bn input GND tPHL tPLH VOH VM Bn, An output VOL 001aai475 Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig 5.
PAGE 15
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0V tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 15. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Fig 7. Table 15.
PAGE 16
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state 12. Typical propagation delay characteristics 001aai476 24 tpd (ns) (1) (2) (3) (4) (5) (6) tpd (ns) (1) 20 001aai477 21 17 16 12 13 (2) (3) (4) (5) (6) 8 4 9 0 20 40 60 0 20 CL (pF) 40 60 CL (pF) a. Propagation delay (An to Bn); VCC(A) = 0.8 V b. Propagation delay (An to Bn); VCC(B) = 0.8 V (1) VCC(B) = 0.8 V. (1) VCC(A) = 0.8 V. (2) VCC(B) = 1.2 V. (2) VCC(A) = 1.2 V. (3) VCC(B) = 1.5 V.
PAGE 17
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state 001aai478 7 001aai491 7 (1) tPLH (ns) tPHL (ns) (2) 5 (1) 5 (3) (2) (3) (4) (4) (5) (5) 3 3 1 1 0 20 40 60 0 20 40 CL (pF) a. LOW to HIGH propagation delay (An to Bn); VCC(A) = 1.2 V b. HIGH to LOW propagation delay (An to Bn); VCC(A) = 1.
PAGE 18
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state 001aai481 7 (1) tPLH (ns) 001aai482 7 tPHL (ns) 5 (1) 5 (2) (3) (2) (3) (4) 3 (4) (5) 3 (5) 1 1 0 20 40 60 0 20 40 CL (pF) a. LOW to HIGH propagation delay (An to Bn); VCC(A) = 1.8 V b. HIGH to LOW propagation delay (An to Bn); VCC(A) = 1.
PAGE 19
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state 001aai485 7 tPLH (ns) 001aai484 7 tPHL (ns) (1) 5 (1) 5 (2) (2) (3) (3) 3 3 (4) (4) (5) (5) 1 1 0 20 40 60 0 CL (pF) 20 40 60 CL (pF) a. LOW to HIGH propagation delay (An to Bn); VCC(A) = 3.3 V b. HIGH to LOW propagation delay (An to Bn); VCC(A) = 3.3 V (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. Fig 11.
PAGE 20
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state 13. Package outline TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm D SOT355-1 E A X c HE y v M A Z 13 24 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 7.
PAGE 21
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm B D SOT815-1 A A E A1 c detail X terminal 1 index area C e1 terminal 1 index area e y1 C v M C A B w M C b 2 y 11 L 12 1 e2 Eh 24 13 23 14 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max.
PAGE 22
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state 14. Abbreviations Table 16. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 17. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AVCH8T245 v.5 20121227 Product data sheet - 74AVCH8T245 v.
PAGE 23
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
PAGE 24
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
PAGE 25
74AVCH8T245 NXP Semiconductors 8-bit dual supply translating transceiver; 3-state 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . .