Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate AND gate 74HC SO 14

1. General description

The 74HC08-Q100; 7 4HCT08-Q100 is a quad 2-input AND gate. Inputs include clamp

diodes. This enables the use of current limiting resistors to interface inputs to voltages in

excess of V

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Complies with JEDEC standard JESD7A

 Complies with JEDEC standard JESD8-1A

 Input levels:

 For 74HC08-Q100: CMOS level

 For 74HCT08-Q100: TTL level

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 Multiple package options

3. Ordering information

74HC08-Q100; 74HCT08-Q100

Quad 2-input AND gate

Rev. 1 — 16 July 2012 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC08D-Q100 40 C to +125 C SO14 plastic small outline package; 14 leads; body width

3.9 mm

SOT108-1

74HCT08D-Q100

74HC08PW-Q100 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74HCT08PW-Q100

74HC08BQ-Q100 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads; 14 terminals;

body 2.5  3  0.85 mm

SOT762-1

74HCT08BQ-Q100

Summary of content (14 pages)

PAGE 1
74HC08-Q100; 74HCT08-Q100 Quad 2-input AND gate Rev. 1 — 16 July 2012 Product data sheet 1. General description The 74HC08-Q100; 7 4HCT08-Q100 is a quad 2-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2.
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74HC08-Q100; 74HCT08-Q100 NXP Semiconductors Quad 2-input AND gate 4. Functional diagram 1 & 3 & 6 & 8 2 4 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 3 5 2Y 6 9 10 3Y 8 4Y 11 A 12 & Y 11 13 B mna222 Fig 1. mna221 mna223 Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.
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74HC08-Q100; 74HCT08-Q100 NXP Semiconductors Quad 2-input AND gate 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10,13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 6. Functional description Table 3. Function table[1] Input Output nA nB L L L L H L H L L H H H [1] nY H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values Table 4.
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74HC08-Q100; 74HCT08-Q100 NXP Semiconductors Quad 2-input AND gate 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC08-Q100 Min Typ 74HCT08-Q100 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.
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74HC08-Q100; 74HCT08-Q100 NXP Semiconductors Quad 2-input AND gate Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min CI input capacitance Typ 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max - 3.5 - - - - - pF 74HCT08-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.
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74HC08-Q100; 74HCT08-Q100 NXP Semiconductors Quad 2-input AND gate Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for load circuit see Figure 7. Symbol Parameter CPD 25 C Conditions power dissipation capacitance 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) - 10 - - - VCC = 4.5 V - 14 24 30 36 ns VCC = 5.
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4HC08-Q100; 74HCT08-Q100 NXP Semiconductors Quad 2-input AND gate VI negative pulse tW 90 % VM VM 10 % GND tr tf tr tf VI 90 % positive pulse GND VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 7. Load circuitry for measuring switching times Table 9.
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74HC08-Q100; 74HCT08-Q100 NXP Semiconductors Quad 2-input AND gate 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.
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74HC08-Q100; 74HCT08-Q100 NXP Semiconductors Quad 2-input AND gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.
PAGE 10
74HC08-Q100; 74HCT08-Q100 NXP Semiconductors Quad 2-input AND gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b 1 0.05 0.00 0.30 0.
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74HC08-Q100; 74HCT08-Q100 NXP Semiconductors Quad 2-input AND gate 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic MIL Military 14. Revision history Table 11. Revision history Document ID Release date 74HC_HCT08_Q100 v.
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74HC08-Q100; 74HCT08-Q100 NXP Semiconductors Quad 2-input AND gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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NXP Semiconductors 74HC08-Q100; 74HCT08-Q100 Quad 2-input AND gate No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only.
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NXP Semiconductors 74HC08-Q100; 74HCT08-Q100 Quad 2-input AND gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . .