Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Counter Binary counter 74HC Negative slope 90 MHz SSOP 14

1. General description

The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding

asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to

Q6). The counter advances on the HIGH-to-LOW transition of CP

. A HIGH on MR clears

all counter stages and forces all outputs LOW, independent of the state of CP

. Each

counter stage is a static toggle flip-flop. Schmitt-trigger action in the clock input makes the

circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This

enables the use of current limiting resistors to interface inputs to voltages in excess of

2. Features and benefits

 Low-power dissipation

 Complies with JEDEC standard no. 7A

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V.

 Multiple package options

 Specified from 40 Cto+80C and from 40 Cto+125C.

3. Applications

 Frequency dividing circuits

 Time delay circuits.

74HC4024

7-stage binary ripple counter

Rev. 7 — 31 October 2013 Product data sheet

Summary of content (19 pages)

PAGE 1
74HC4024 7-stage binary ripple counter Rev. 7 — 31 October 2013 Product data sheet 1. General description The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop.
PAGE 2
74HC4024 NXP Semiconductors 7-stage binary ripple counter 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4024N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 74HC4024D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74HC4024DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.
PAGE 3
74HC4024 NXP Semiconductors 7-stage binary ripple counter 6. Pinning information 6.1 Pinning 74HC4024 CP 1 14 VCC MR 2 13 n.c. Q6 3 12 Q0 Q5 4 11 Q1 Q4 5 10 n.c. Q3 6 9 Q2 GND 7 8 n.c. 001aab905 Fig 5. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description CP 1 clock input (HIGH-to-LOW, edge-triggered) MR 2 master reset input (active HIGH) Q6, Q5, Q4, Q3, Q2, Q2, Q1, Q0 3, 4, 5, 6, 9, 11, 12 parallel output GND 7 ground (0 V) n.c.
PAGE 4
74HC4024 NXP Semiconductors 7-stage binary ripple counter 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA IO output current VO = 0.5 V to VCC + 0.
PAGE 5
74HC4024 NXP Semiconductors 7-stage binary ripple counter 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - V VCC = 4.5 V 3.15 2.4 - V VCC = 6.0 V 4.2 3.2 - V VCC = 2.0 V - 0.8 0.5 V VCC = 4.5 V - 2.1 1.35 V VCC = 6.0 V - 2.8 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.
PAGE 6
74HC4024 NXP Semiconductors 7-stage binary ripple counter Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V - - 0.1 V IO = 20 A; VCC = 4.5 V - - 0.1 V IO = 20 A; VCC = 6.0 V - - 0.1 V IO = 4 mA; VCC = 4.5 V - - 0.33 V IO = 5.2 mA; VCC = 6.0 V - - 0.
PAGE 7
4HC4024 NXP Semiconductors 7-stage binary ripple counter 11. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7. Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V - 47 175 ns VCC = 4.5 V - 17 35 ns VCC = 6.0 V - 14 30 ns - 14 - ns VCC = 2.0 V - 25 80 ns VCC = 4.5 V - 9 16 ns VCC = 6.0 V - 7 14 ns VCC = 2.0 V - 63 200 ns VCC = 4.5 V - 23 40 ns - 18 34 ns VCC = 2.
PAGE 8
74HC4024 NXP Semiconductors 7-stage binary ripple counter Table 7. Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7. Symbol Parameter Conditions Min Typ Max Unit Tamb = 40 C to +85 C tpd propagation delay CP to Q0; see Figure 6 [1] VCC = 2.0 V - - 220 ns VCC = 4.5 V - - 44 ns - - 37 ns VCC = 6.0 V Qn to Qn+1; see Figure 6 tPHL HIGH to LOW propagation delay [1] VCC = 2.0 V - - 100 ns VCC = 4.5 V - - 20 ns VCC = 6.
PAGE 9
74HC4024 NXP Semiconductors 7-stage binary ripple counter Table 7. Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7. Symbol Parameter Conditions Min Typ Max Unit Tamb = 40 C to +125 C tpd propagation delay CP to Q0; see Figure 6 [1] VCC = 2.0 V - - 265 ns VCC = 4.5 V - - 53 ns - - 45 ns VCC = 6.0 V Qn to Qn+1; see Figure 6 tPHL HIGH to LOW propagation delay [1] VCC = 2.0 V - - 120 ns VCC = 4.5 V - - 24 ns VCC = 6.
PAGE 10
74HC4024 NXP Semiconductors 7-stage binary ripple counter Table 7. Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7. Symbol Parameter Conditions fmax maximum frequency CP; see Figure 6 [1] Min Typ Max Unit VCC = 2.0 V 4.0 - - MHz VCC = 4.5 V 20 - - MHz VCC = 6.0 V 24 - - MHz tpd is the same as tPLH and tPHL. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W).
PAGE 11
74HC4024 NXP Semiconductors 7-stage binary ripple counter VCC PULSE GENERATOR VI VO DUT RT CL mna101 Test data is given in Table 8. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig 7. Table 8. Test circuit for measuring switching times Test data Supply Input Load VCC VI tr, tf CL 2.0 V VCC 6 ns 50 pF 4.5 V VCC 6 ns 50 pF 6.0 V VCC 6 ns 50 pF 5.
PAGE 12
74HC4024 NXP Semiconductors 7-stage binary ripple counter 13. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.
PAGE 13
74HC4024 NXP Semiconductors 7-stage binary ripple counter SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.
PAGE 14
74HC4024 NXP Semiconductors 7-stage binary ripple counter SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.
PAGE 15
74HC4024 NXP Semiconductors 7-stage binary ripple counter TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.
PAGE 16
74HC4024 NXP Semiconductors 7-stage binary ripple counter 14. Abbreviations Table 9. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC4024 v.7 20131031 Product data sheet - 74HC4024 v.6 Modifications: • General description updated.
PAGE 17
74HC4024 NXP Semiconductors 7-stage binary ripple counter 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 18
74HC4024 NXP Semiconductors 7-stage binary ripple counter Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
PAGE 19
74HC4024 NXP Semiconductors 7-stage binary ripple counter 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . .