Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate and inverter XOR gate 74HC SO 14

1. General description

The 74HC86; 74HCT86 are high-speed Si-gate CMOS devices that comply with JEDEC

standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).

The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function.

2. Features and benefits

 Input levels:

 For 74HC86: CMOS level

 For 74HCT86: TTL level

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 Multiple package options

 Specified from 40 C to +85 C and from 40 C to +125 C

3. Ordering information

74HC86; 74HCT86

Quad 2-input EXCLUSIVE-OR gate

Rev. 3 — 27 August 2012 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC86N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

74HCT86N

74HC86D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width

3.9 mm

SOT108-1

74HCT86D

74HC86DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body

width 5.3 mm

SOT337-1

74HCT86DB

74HC86PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74HCT86PW

Summary of content (16 pages)

PAGE 1
74HC86; 74HCT86 Quad 2-input EXCLUSIVE-OR gate Rev. 3 — 27 August 2012 Product data sheet 1. General description The 74HC86; 74HCT86 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function. 2.
PAGE 2
74HC86; 74HCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 4. Functional diagram 1 2 1A 1B 1Y 3 4 2A 2B 2Y 6 10 3A 3B 3Y 8 12 13 4A 4B 4Y 11 5 9 mna787 Fig 1. Logic symbol 1 =1 3 =1 6 =1 8 =1 11 2 4 5 9 10 A 12 Y 13 B Fig 2. mna788 Logic diagram (one gate) 74HC_HCT86 Product data sheet mna786 Fig 3. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 3 — 27 August 2012 © NXP B.V. 2012. All rights reserved.
PAGE 3
74HC86; 74HCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 5. Pinning information 5.1 Pinning 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 2A 4 2B 5 2Y 6 GND 7 86 11 4Y 10 3B 9 3A 8 3Y 001aad103 Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10, 13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 6.
PAGE 4
74HC86; 74HCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7 V - 20 mA - 20 mA - 25 mA 50 mA IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current 0.
PAGE 5
74HC86; 74HCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min Typ VCC = 2.0 V 1.5 VCC = 4.5 V 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max 1.2 - 1.5 - 1.5 - V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.
PAGE 6
74HC86; 74HCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min 40 C to +85 C 40 C to +125 C Unit Typ Max Min Max Min Max ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 A ICC additional supply current per input pin; VI = VCC  2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.
PAGE 7
4HC86; 74HCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate Table 7. Dynamic characteristics …continued GND = 0 V; CL = 50 pF; for load circuit see Figure 6. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) - 17 32 40 48 ns - 14 - - - ns 74HCT86 [1] propagation delay nA, nB to nY; see Figure 5 tpd VCC = 4.5 V VCC = 5.0 V; CL = 15 pF tt transition time VCC = 4.
PAGE 8
74HC86; 74HCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate VI negative pulse tW 90 % VM VM 10 % GND tr tf tr tf VI 90 % positive pulse GND VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 6. Table 9.
PAGE 9
74HC86; 74HCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.
PAGE 10
74HC86; 74HCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.
PAGE 11
74HC86; 74HCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.
PAGE 12
74HC86; 74HCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.
PAGE 13
74HC86; 74HCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT86 v.
PAGE 14
74HC86; 74HCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 15
74HC86; 74HCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
PAGE 16
74HC86; 74HCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . .