Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate AND gate 74HCT TSSOP 8

1. General description

The 74HC2G08; 74HCT2G08 is a dual 2-input AND gate. Inputs include clamp diodes.

This enables the use of current limiting resistors to interface inputs to voltages in excess

of V

2. Features and benefits

 Wide supply voltage range from 2.0 V to 6.0 V

 Input levels:

 For 74HC2G08: CMOS level

 For 74HCT2G08: TTL level

 Symmetrical output impedance

 High noise immunity

 Low power dissipation

 Balanced propagation delays

 Multiple package options

 ESD protection:

 HBM JESD22-A114E exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 Specified from 40 C to +85 C and 40 C to +125 C

3. Ordering information

74HC2G08; 74HCT2G08

Dual 2-input AND gate

Rev. 5 — 8 October 2013 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC2G08DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads;

body width 3 mm; lead length 0.5 mm

SOT505-2

74HCT2G08DP

74HC2G08DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads;

body width 2.3 mm

SOT765-1

74HCT2G08DC

74HC2G08GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads;

8 terminals; body 3  2  0.5 mm

SOT996-2

74HCT2G08GD

Summary of content (15 pages)

PAGE 1
74HC2G08; 74HCT2G08 Dual 2-input AND gate Rev. 5 — 8 October 2013 Product data sheet 1. General description The 74HC2G08; 74HCT2G08 is a dual 2-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits  Wide supply voltage range from 2.0 V to 6.
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74HC2G08; 74HCT2G08 NXP Semiconductors Dual 2-input AND gate 4. Marking Table 2. Marking code Type number Marking code[1] 74HC2G08DP H08 74HCT2G08DP T08 74HC2G08DC H08 74HCT2G08DC T08 74HC2G08GD H08 74HCT2G08GD T08 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram & 1A 1B 2A 2B 1Y & 2Y 001aah789 001aah788 Fig 1. Logic symbol Fig 2. IEC logic symbol A Y B mna221 Fig 3.
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74HC2G08; 74HCT2G08 NXP Semiconductors Dual 2-input AND gate 6. Pinning information 6.1 Pinning 74HC2G08 74HCT2G08 74HC2G08 74HCT2G08 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 001aak019 Transparent top view 001aak018 Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 5. Pin configuration SOT996-2 (XSON8) 6.2 Pin description Table 3.
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74HC2G08; 74HCT2G08 NXP Semiconductors Dual 2-input AND gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7.0 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] - 20 mA output current VO = 0.5 V to (VCC + 0.
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74HC2G08; 74HCT2G08 NXP Semiconductors Dual 2-input AND gate 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.
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74HC2G08; 74HCT2G08 NXP Semiconductors Dual 2-input AND gate Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions 40 C to +125 C Min Typ[1] Max Min Max Unit 74HCT2G08 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.
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4HC2G08; 74HCT2G08 NXP Semiconductors Dual 2-input AND gate Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max - 14 30 - 36 ns 74HCT2G08 [2] propagation delay nA and nB to nY; see Figure 6 tpd VCC = 4.5 V VCC = 5.0 V; CL = 15 pF tt transition time VCC = 4.5 V; see Figure 6 CPD power dissipation VI = GND to VCC  1.
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74HC2G08; 74HCT2G08 NXP Semiconductors Dual 2-input AND gate VI tW 90 % negative pulse VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC VI G VO RL S1 open DUT CL RT 001aad983 Test data is given in Table 10. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 7.
PAGE 9
74HC2G08; 74HCT2G08 NXP Semiconductors Dual 2-input AND gate 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.
PAGE 10
74HC2G08; 74HCT2G08 NXP Semiconductors Dual 2-input AND gate VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.
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74HC2G08; 74HCT2G08 NXP Semiconductors Dual 2-input AND gate XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm B D SOT996-2 A E A A1 detail X terminal 1 index area e1 1 4 8 5 C C A B C v w b e L1 y y1 C L2 L X 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit(1) max nom min mm A A1 b 0.05 0.35 D E 2.1 3.1 0.5 0.00 0.15 1.9 e e1 0.5 1.5 2.9 L L1 L2 0.5 0.15 0.6 0.3 0.05 0.4 v 0.1 w y 0.05 0.
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74HC2G08; 74HCT2G08 NXP Semiconductors Dual 2-input AND gate 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT2G08 v.5 20131008 Product data sheet - 74HC_HCT2G32 v.
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74HC2G08; 74HCT2G08 NXP Semiconductors Dual 2-input AND gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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74HC2G08; 74HCT2G08 NXP Semiconductors Dual 2-input AND gate Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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NXP Semiconductors 74HC2G08; 74HCT2G08 Dual 2-input AND gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . .