Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74LV SO 14

1. General description

The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible

with 74HC132 and 74HCT132.

The 74LV132 contains four 2-input NAND gates which accept standard input signals.

They are capable of transforming slowly changing input signals into sharply deﬁned,

jitter-free output signals.

The gate switches at different points for positive and negative-going signals. The

difference between the positive voltage V

T+

and the negative voltage V

T−

is deﬁned as the

input hysteresis voltage V

2. Features

n Wide operating voltage: 1.0 V to 5.5 V

n Optimized for low voltage applications: 1.0 V to 3.6 V

n Accepts TTL input levels between V

= 2.7 V and V

= 3.6 V

n Typical output ground bounce < 0.8 V at V

= 3.3 V and T

amb

= 25 °C

n Typical HIGH-level output voltage (V

) undershoot: > 2 V at V

= 3.3 V and

amb

=25°C

n ESD protection:

u HBM JESD22-A114E exceeds 2000 V

u MM JESD22-A115-A exceeds 200 V

n Multiple package options

n Speciﬁed from −40 °Cto+85°C and from −40 °C to +125 °C

3. Applications

n Wave and pulse shapers for highly noisy environments

n Astable multivibrators

n Monostable multivibrators

74LV132

Quad 2-input NAND Schmitt trigger

Rev. 05 — 2 July 2009 Product data sheet

Summary of content (17 pages)

PAGE 1
74LV132 Quad 2-input NAND Schmitt trigger Rev. 05 — 2 July 2009 Product data sheet 1. General description The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC132 and 74HCT132. The 74LV132 contains four 2-input NAND gates which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The gate switches at different points for positive and negative-going signals.
PAGE 2
74LV132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV132N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 74LV132D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LV132DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; body width 5.
PAGE 3
74LV132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 6. Pinning information 6.1 Pinning 1 1A terminal 1 index area 2 13 4B 12 4A 1Y 3 2A 4 2B 5 2Y 6 9 3A GND 7 8 3Y 132 11 4Y 10 3B 12 4A 2A 4 2B 5 2Y 6 11 4Y VCC (1) 10 3B 9 8 1B 13 4B 3 3Y 14 VCC 2 1Y 7 1 1B GND 1A 14 VCC 74LV132 3A 001aah099 Transparent top view (1) The die substrate is attached to the exposed die pad using conductive die attach material.
PAGE 4
74LV132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 7. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level. Input Output nA nB nY L L H L H H H L H H H L 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit −0.5 +7.
PAGE 5
74LV132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 9. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply Conditions voltage[1] Min Typ Max Unit 1.0 3.3 5.5 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C [1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.
PAGE 6
74LV132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 11. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure 7. Symbol Parameter propagation delay tpd −40 °C to +85 °C Conditions power dissipation capacitance Unit Min Max Min Max VCC = 1.2 V - 65 - - - ns VCC = 2.0 V - 18 34 - 43 ns 24 - 30 ns [2] nA, nB to nY; see Figure 6 VCC = 2.7 V CPD −40 °C to +125 °C Typ[1] - 15 VCC = 3.0 V to 3.
PAGE 7
4LV132 NXP Semiconductors Quad 2-input NAND Schmitt trigger Table 8. Measurement points Supply voltage Input Output VCC VM VM < 2.7 V 0.5VCC 0.5VCC 2.7 V to 3.6 V 1.5 V 1.5 V ≥ 4.5 V 0.5VCC 0.5VCC VCC PULSE GENERATOR VI VO DUT CL 50 pF RT RL 1 kΩ 001aaa663 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. RL = Load resistance. CL = Load capacitance including jig and probe capacitance.
PAGE 8
74LV132 NXP Semiconductors Quad 2-input NAND Schmitt trigger Table 10. Transfer characteristics …continued GND = 0 V; For test circuit see Figure 7. Symbol Parameter VT− negative-going threshold voltage hysteresis voltage VH [1] −40 °C to +85 °C Conditions Min Typ[1] Max −40 °C to +125 °C Min Unit Max see Figure 6 VCC = 1.2 V - 0.34 - - - V VCC = 2.0 V 0.3 0.65 0.9 0.3 0.9 V VCC = 2.7 V 0.4 0.90 1.4 0.4 1.4 V VCC = 3.0 V 0.6 1.05 1.5 0.6 1.5 V VCC = 3.6 V 0.8 1.
PAGE 9
74LV132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 001aaa659 12 001aaa660 100 ICC (µA) ICC (µA) 80 8 60 40 4 20 0 0 0 0.3 0.6 0.9 1.2 0 0.4 VI (V) 0.8 1.2 1.6 2 VI (V) VCC = 1.2 V. VCC = 2.0 V. Fig 10. Typical 74LV132 transfer characteristics Fig 11. Typical 74LV132 transfer characteristics 001aaa661 300 ICC (µA) 200 100 0 0 0.6 1.2 1.8 2.4 3 VI (V) VCC = 3.0 V. Fig 12. Typical 74LV132 transfer characteristics 74LV132_5 Product data sheet © NXP B.V. 2009.
PAGE 10
74LV132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 15. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.
PAGE 11
74LV132 NXP Semiconductors Quad 2-input NAND Schmitt trigger SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.
PAGE 12
74LV132 NXP Semiconductors Quad 2-input NAND Schmitt trigger SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.
PAGE 13
74LV132 NXP Semiconductors Quad 2-input NAND Schmitt trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.
PAGE 14
74LV132 NXP Semiconductors Quad 2-input NAND Schmitt trigger DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.
PAGE 15
74LV132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 16. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 17. Revision history Table 12.
PAGE 16
74LV132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 17
74LV132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 20. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . .