74LVC1G384 Bilateral switch Rev. 5 — 15 January 2015 Product data sheet 1. General description The 74LVC1G384 provides one single pole, single throw analog switch function. It has two input/output terminals (Y and Z) and an active LOW enable input pin (E). When pin E is HIGH, the analog switch is turned off. Schmitt trigger action at the enable input makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 1.65 V to 5.5 V. 2.
74LVC1G384 NXP Semiconductors Bilateral switch Table 1. Ordering information …continued Type number Package Temperature range Name Description Version 74LVC1G384GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 SOT891 terminals; body 1 1 0.5 mm 74LVC1G384GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9 1.0 0.
74LVC1G384 NXP Semiconductors Bilateral switch 6. Pinning information 6.1 Pinning /9& * < 9&& = Q F /9& * /9& * < = *1' 9&& *1' ( Pin configuration SOT353-1 and SOT753 ( 9&& = Q F *1' ( DDJ DDJ 7UDQVSDUHQW WRS YLHZ 7UDQVSDUHQW WRS YLHZ DDD Fig 4. < Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891, SOT1115 and SOT1202 6.2 Pin description Table 3.
74LVC1G384 NXP Semiconductors Bilateral switch 7. Functional description Table 4. Function table[1] Input E Switch L ON-state H OFF-state [1] H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Min Max Unit 0.5 +6.5 V VI input voltage 0.5 +6.
74LVC1G384 NXP Semiconductors Bilateral switch 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter HIGH-level input voltage VIH LOW-level input voltage VIL 40 C to +85 C Conditions VCC = 1.65 V to 1.95 V 40 C to +125 C Min Typ[1] Max Min Unit Max 0.65VCC - - 0.65 VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.
74LVC1G384 NXP Semiconductors Bilateral switch 10.1 Test circuits 9&& 9&& ( 9,+ = 9, ( 9,/ < ,6 ,6 *1' 92 = < *1' 9, DDJ DDJ VI = VCC or GND and VO = GND or VCC. Fig 7. 92 VI = VCC or GND and VO = open circuit. Test circuit for measuring OFF-state leakage current Fig 8. Test circuit for measuring ON-state leakage current 10.2 ON resistance Table 8.
4LVC1G384 NXP Semiconductors Bilateral switch Table 8. ON resistance …continued At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15. Symbol RON(flat) Parameter 40 C to +85 C Conditions ON resistance (flatness) 40 C to +125 C Unit Min Typ[1] Max Min Max ISW = 4 mA; VCC = 1.65 V to 1.95 V - 26.0 - - - ISW = 8 mA; VCC = 2.3 V to 2.7 V - 5.0 - - - ISW = 12 mA; VCC = 2.7 V - 3.
74LVC1G384 NXP Semiconductors Bilateral switch DDD 521 ȍ DDD 521 ȍ 9, 9 (1) Tamb = 125 C. (1) Tamb = 125 C. (2) Tamb = 85 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (3) Tamb = 25 C. (4) Tamb = 40 C. (4) Tamb = 40 C. Fig 11. ON resistance as a function of input voltage; VCC = 1.8 V DDD 9, 9 521 ȍ Fig 12.
74LVC1G384 NXP Semiconductors Bilateral switch DDD 521 ȍ 9, 9 (1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = 40 C. Fig 15. ON resistance as a function of input voltage; VCC = 5.0 V 11. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 18.
74LVC1G384 NXP Semiconductors Bilateral switch Table 9. Dynamic characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 18. Symbol Parameter 40 C to +85 C Conditions Min tdis disable time Max 40 C to +125 C Min Max Unit [5] E to Y or Z; see Figure 17 VCC = 1.65 V to 1.95 V 1.0 7.4 10.0 1.0 13.0 ns VCC = 2.3 V to 2.7 V 1.0 4.1 6.9 1.0 9.0 ns VCC = 2.7 V 1.0 4.9 7.5 1.0 9.5 ns VCC = 3.
74LVC1G384 NXP Semiconductors Bilateral switch 9, ( 90 *1' W3/= W3=/ 9&& < RU = RXWSXW /2: WR 2)) 2)) WR /2: 90 9; 92/ W3+= 92+ < RU = W3=+ 9< RXWSXW +,*+ WR 2)) 2)) WR +,*+ 90 *1' VZLWFK HQDEOHG VZLWFK GLVDEOHG VZLWFK HQDEOHG DDD Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 17. Enable and disable times Table 10.
74LVC1G384 NXP Semiconductors Bilateral switch 9(;7 9&& 9, * 5/ 92 '87 57 &/ 5/ PQD Test data is given in Table 11. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. VEXT = External voltage for measuring switching times. Fig 18. Test circuit for measuring switching times Table 11.
74LVC1G384 NXP Semiconductors Bilateral switch Table 12. Additional dynamic characteristics …continued At recommended operating conditions; typical values measured at Tamb = 25 C. Symbol Parameter Conditions f(3dB) 3 dB frequency response RL = 600 ; CL = 50 pF; see Figure 20 Min Typ Max Unit VCC = 1.65 V - 135 - MHz VCC = 2.3 V - 145 - MHz VCC = 3.0 V - 150 - MHz VCC = 4.5 V - 155 - MHz VCC = 1.65 V - > 500 - MHz VCC = 2.3 V - > 500 - MHz VCC = 3.
74LVC1G384 NXP Semiconductors Bilateral switch Table 12. Additional dynamic characteristics …continued At recommended operating conditions; typical values measured at Tamb = 25 C. Symbol Parameter Conditions Min Typ Max Qinj charge injection CL = 0.1 nF; Vgen = 0 V; Rgen = 0 ; fi = 1 MHz; RL = 1 M; see Section 11 Unit VCC = 1.8 V - 3.3 - pC VCC = 2.5 V - 4.1 - pC VCC = 3.3 V - 5.0 - pC VCC = 4.5 V - 6.4 - pC VCC = 5.5 V - 7.5 - pC 11.
74LVC1G384 NXP Semiconductors Bilateral switch 9&& 9&& 5/ 9,+ S) IL 9&& ( 5/ < = = < 92 ȍ &/ G% DDJ Adjust fi voltage to obtain 0 dBm level at input. Fig 21. Test circuit for measuring isolation (OFF-state) 9&& ( < = * ORJLF LQSXW ȍ = < 92 5/ ȍ 9&& &/ 9&& DDJ Fig 22.
74LVC1G384 NXP Semiconductors Bilateral switch 12.
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74LVC1G384 NXP Semiconductors Bilateral switch 13. Abbreviations Table 13. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC1G384 v.5 20150115 Product data sheet - 74LVC1G384 v.4 Modifications: 74LVC1G384 v.
74LVC1G384 NXP Semiconductors Bilateral switch 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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NXP Semiconductors 74LVC1G384 Bilateral switch 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.2 11.3 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . .