Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Buffer, driver TSSOP 8

1. General description

The 74LVC3G17 provides three non-inverting buffers with Schmitt trigger input. It is

capable of transforming slowly changing input signals into sharply defined, jitter-free

output signals.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the

74LVC3G17 as a translator in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing a damaging backflow current through the device

when it is powered down.

2. Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V

 5 V tolerant input/output for interfacing with 5 V logic

 High noise immunity

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 24 mA output drive (V

= 3.0 V)

 CMOS low-power consumption

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Multiple package options

 Specified from 40 C to +85 C and 40 C to +125 C

3. Applications

 Wave and pulse shapers for highly noisy environments

74LVC3G17

Triple non-inverting Schmitt trigger with 5 V tolerant input

Rev. 11 — 9 April 2013 Product data sheet

Summary of content (23 pages)

PAGE 1
74LVC3G17 Triple non-inverting Schmitt trigger with 5 V tolerant input Rev. 11 — 9 April 2013 Product data sheet 1. General description The 74LVC3G17 provides three non-inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC3G17 as a translator in a mixed 3.3 V and 5 V environment.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC3G17DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74LVC3G17DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input 6. Functional diagram 1A 1Y 3Y 3A 2A 2Y 001aah861 001aah860 Fig 1. Logic symbol Fig 2. IEC logic symbol A Y 001aab109 Fig 3. Logic diagram (one gate) 7. Pinning information 7.1 Pinning 74LVC3G17 1A 1 8 VCC 3Y 2 7 1Y 2A 3 6 3A GND 4 5 2Y 74LVC3G17 1A 1 8 VCC 3Y 2 7 1Y 2A 3 6 3A GND 4 5 2Y 001aac023 Transparent top view 001aab106 Fig 4.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input 74LVC3G17 1 8 VCC 3Y 2 7 1Y 2A 3 6 3A GND 4 5 2Y 3A 2Y 8 1 7 1A 2 6 3Y 3 5 2A GND 1A 1Y 4 74LVC3G17 VCC terminal 1 index area 001aai246 Transparent top view Transparent top view Fig 6. 001aag404 Pin configuration SOT996-2 Fig 7. Pin configuration SOT902-2 7.2 Pin description Table 3.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions VI < 0 V [1] Power-down mode Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V - 50 mA [1] 0.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input 11. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Min Typ[1] Max Unit IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.45 V IO = 8 mA; VCC = 2.3 V - - 0.3 V IO = 12 mA; VCC = 2.7 V - - 0.4 V IO = 24 mA; VCC = 3.0 V - - 0.55 V IO = 32 mA; VCC = 4.
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4LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max Unit IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - 20 A ICC supply current VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V - - 40 A ICC additional supply current VI = VCC  0.6 V; IO = 0 A; VCC = 2.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input 13. Waveforms VI nA input VM VM GND tPLH tPHL VOH VM nY output VM VOL mnb072 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Table 9. The input (nA) to output (nY) propagation delays and the output transition times Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5  VCC 0.5  VCC 2.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input VEXT VCC VI RL VO G DUT RT CL RL mna616 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Table 10.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input 14. Transfer characteristics Table 11. Transfer characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter positive-going threshold voltage VT+ negative-going threshold voltage VT 40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 1.8 V 0.70 1.10 1.50 0.70 1.70 V VCC = 2.3 V 1.00 1.40 1.80 1.00 2.00 V VCC = 3.0 V 1.30 1.76 2.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input mnb071 14 ICC (mA) 12 10 8 6 4 2 0 0 0.5 1 1.5 2 VI (V) VCC = 3.0 V. Fig 12. Typical transfer characteristic mnb156 50 ICC (mA) (1) 40 30 20 (2) 10 0 2 3 4 5 VCC (V) 6 (1) Positive-going edge. (2) Negative-going edge. Linear change of VI between 0.8 V to 2.0 V. All values given are typical unless otherwise specified. Fig 13.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input 16. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm SOT1089 E terminal 1 index area D A A1 detail X (4×)(2) e L (8×)(2) b 4 5 e1 1 terminal 1 index area 8 L1 X 0 0.5 scale Dimensions Unit mm max nom min 1 mm A(1) 0.5 A1 b D E e e1 L L1 0.35 0.40 0.04 0.20 1.40 1.05 0.15 1.35 1.00 0.55 0.35 0.30 0.35 0.27 0.32 0.12 1.30 0.95 Note 1.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm B D SOT996-2 A E A A1 detail X terminal 1 index area e1 1 4 8 5 C C A B C v w b e L1 y y1 C L2 L X 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit(1) mm max nom min A A1 b 0.05 0.35 D E 2.1 3.1 0.5 0.00 0.15 1.9 e e1 0.5 1.5 2.9 L L1 L2 0.5 0.15 0.6 0.3 0.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input XQFN8: plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-2 X A B D terminal 1 index area E A A1 detail X e v w b 4 3 C C A B C y y1 C 5 e1 2 6 1 7 terminal 1 index area 8 L metal area not for soldering L1 0 1 Dimensions Unit(1) mm max nom min 2 mm scale A 0.5 A1 b D E e e1 0.05 0.25 1.65 1.65 0.20 1.60 1.60 0.55 0.00 0.15 1.55 1.55 0.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1.0 x 0.35 mm 1 2 SOT1116 b 4 3 (4×)(2) L L1 e 8 7 e1 6 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 max 0.35 0.04 0.20 1.25 1.05 nom 0.15 1.20 1.00 0.55 min 0.12 1.15 0.95 0.3 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203 b 2 1 3 (4×)(2) 4 L L1 e 8 7 6 e1 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.40 1.05 0.35 0.40 nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35 min 0.12 1.30 0.95 0.27 0.32 Note 1.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input 17. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 18. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC3G17 v.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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74LVC3G17 NXP Semiconductors Triple non-inverting Schmitt trigger with 5 V tolerant input 21. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 12 13 14 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . .