Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Buffer, driver SO 14

1. General description

The 74LVT125; 74LVTH125 is a high-performance BiCMOS product designed for V

operation at 3.3 V.

This device combines low static and dynamic power dissipation with high speed and high

output drive. The 74LVT125; 74LVTH125 device is a quad buffer that is ideal for driving

bus lines. The device features four output enable inputs (1OE, 2OE, 3OE and 4OE), each

controlling one of the 3-state outputs.

2. Features

n Quad bus interface

n 3-state buffers

n Output capability: +64 mA and −32 mA

n TTL input and output switching levels

n Input and output interface capability to systems at 5 V supply

n Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs

n Live insertion and extraction permitted

n No bus current loading when output is tied to 5 V bus

n Power-up 3-state

n Latch-up protection:

u JESD78: exceeds 500 mA

n ESD protection:

u MIL STD 883 method 3015: exceeds 2000 V

u Machine model: exceeds 200 V

3. Quick reference data

74LVT125; 74LVTH125

3.3 V quad buffer; 3-state

Rev. 06 — 6 March 2006 Product data sheet

Table 1. Quick reference data

GND = 0 V; T

amb

=25

Symbol Parameter Conditions Min Typ Max Unit

PLH

LOW-to-HIGH propagation

delay nA to nY

= 50 pF; V

= 3.3 V - 2.7 - ns

PHL

HIGH-to-LOW propagation

delay nA to nY

= 50 pF; V

= 3.3 V - 2.9 - ns

Summary of content (16 pages)

PAGE 1
74LVT125; 74LVTH125 3.3 V quad buffer; 3-state Rev. 06 — 6 March 2006 Product data sheet 1. General description The 74LVT125; 74LVTH125 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device combines low static and dynamic power dissipation with high speed and high output drive. The 74LVT125; 74LVTH125 device is a quad buffer that is ideal for driving bus lines.
PAGE 2
74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state Table 1. Quick reference data …continued GND = 0 V; Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit Ci input capacitance VI = 0 V or 3.0 V - 4 - pF Co output capacitance outputs disabled; VO = 0 V or 3.0 V - 8 - pF ICC quiescent supply current outputs disabled; VCC = 3.6 V - 0.13 - mA 4. Ordering information Table 2.
PAGE 3
74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state 5. Functional diagram 2 1A 1 1OE 5 2A 4 2OE 9 3A 1Y 3 2 1 1 2Y 3 EN1 5 6 6 4 3Y 9 8 8 10 10 3OE 12 4A 12 4Y 11 11 13 13 4OE mna229 mna228 Fig 1. Logic symbol Fig 2. IEC logic symbol nY nA nOE mna227 Fig 3. Logic diagram 6. Pinning information terminal 1 index area 14 VCC 1OE 6.
PAGE 4
74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state 6.2 Pin description Table 3.
PAGE 5
74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit −0.5 +4.6 V [1] −0.5 +7.0 V [1] −0.5 +7.
PAGE 6
74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 Conditions Min Typ Max −0.9 −1.2 Unit °C[1] VIK input clamping voltage IIK = −18 mA; VCC = 2.7 V - VOH HIGH-state output voltage IOH = −100 µA; VCC = 2.7 V to 3.6 V VCC − 0.2 VCC − 0.1 - V IOH = −8 mA; VCC = 2.7 V 2.4 2.
PAGE 7
4LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit - 0.1 0.2 mA ∆ICC additional quiescent supply current per input pin; VCC = 3 V to 3.6 V; one input at VCC − 0.6 V and other inputs at VCC or GND Ci input capacitance VI = 0 V or 3.
PAGE 8
74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state 12. Waveforms VI nA input VM VM GND tPLH tPHL VOH VM nY output VM VOL mnb072 VM = 1.5 V. VOL and VOH are typical voltage output drop that occur with the output load. Fig 6. Propagation delay input (nA) to output (nY) VI nOE input VM GND tPZL tPLZ VCC VM nY output VOL + 0.3 V VOL t PZH t PHZ VOH nY output VM VOH − 0.3 V 0V 001aac475 VM = 1.5 V.
PAGE 9
74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae235 Test data is given in Table 9. Definitions test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times.
PAGE 10
74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state 13. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.
PAGE 11
74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.
PAGE 12
74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.
PAGE 13
74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.
PAGE 14
74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state 14. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge TTL Transistor-Transistor Logic 15. Revision history Table 11.
PAGE 15
74LVT125; 74LVTH125 Philips Semiconductors 3.3 V quad buffer; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 16
Philips Semiconductors 74LVT125; 74LVTH125 3.3 V quad buffer; 3-state 18. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . .