Datasheet

ADC1015S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 20 December 2010 23 of 42
NXP Semiconductors
ADC1015S series
Single 10-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
11.4 Clock input
11.4.1 Drive modes
The ADC1015S can be driven differentially (LVPECL). It can also be driven by a
single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal
connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or
CLKM (pin CLKP should be connected to ground via a capacitor).
a. Rising edge LVCMOS b. Falling edge LVCMOS
Fig 22. LVCMOS single-ended clock input
a. Sine clock input b. Sine clock input (with transformer)
c. LVPECL clock input
Fig 23. Differential clock input
LVCMOS
clock input
CLKP
CLKM
005aaa174
005aaa053
LVCMOS
clock input
CLKP
CLKM
Sine
clock input
CLKP
CLKM
005aaa173
Sine
clock input
CLKP
CLKM
005aaa054
LVPECL
clock input
005aaa172
CLKP
CLKM