Datasheet

Product data sheet Rev. 2 — 20 December 2010 29 of 42

NXP Semiconductors

ADC1015S series

Single 10-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

Bits A12 to A0 indicate the address of the register being accessed. In the case of a

multiple byte transfer, this address is the first register to be accessed. An address counter

is increased to access subsequent addresses.

The steps involved in a data transfer are as follows:

1. A falling edge on CS

in combination with a rising edge on SCLK determine the start of

communications.

2. The first phase is the transfer of the 2-byte instruction.

3. The second phase is the transfer of the data which can vary in length but is always a

multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).

4. A rising edge on CS

indicates the end of data transmission.

11.6.2 Default modes at start-up

During circuit initialization it does not matter which output data standard has been

selected. At power-up, the device enters Pin control mode.

A falling edge on CS

triggers a transition to SPI control mode. When the ADC1015S

enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by

the level on pin SDIO (see Figure 29

). Once in SPI control mode, the output data standard

can be changed via bit LVDS/CMOS in Table 23

When the ADC1015S enters SPI control mode, the output data format (two’s complement

or offset binary) is determined by the level on pin SCLK (gray code can only be selected

via the SPI). Once in SPI control mode, the output data format can be changed via bit

DATA_FORMAT[1:0] in Table 23

Table 17. Number of data bytes to be transferred after the instruction bytes

W1 W0 Number of bytes transmitted

001 byte

012 bytes

103 bytes

1 1 4 bytes or more

Fig 28. SPI mode timing

SCLK

SDIO

R/W

W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D3 D2 D1 D0D0 D7 D6 D5 D4

Instruction bytes Register N (data) Register N + 1 (data)

005aaa062