Datasheet

ADC1015S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 20 December 2010 5 of 42
NXP Semiconductors
ADC1015S series
Single 10-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
D9 17 O data output bit 9 (Most Significant Bit (MSB))
D8 18 O data output bit 8
D7 19 O data output bit 7
D6 20 O data output bit 6
D5 21 O data output bit 5
D4 22 O data output bit 4
D3 23 O data output bit 3
D2 24 O data output bit 2
D1 25 O data output bit 1
D0 26 O data output bit 0 (Least Significant Bit (LSB))
n.c. 27 - not connected
n.c. 28 - not connected
n.c. 29 - not connected
n.c. 30 - not connected
DAV 31 O data valid output clock
n.c. 32 - not connected
VDDO 33 P output power supply
OGND 34 G output ground
OTR 35 O out of range
SCLK/DFS 36 I SPI clock / data format select
SDIO/ODS 37 I/O SPI data IO / output data standard
CS
38 I SPI chip select
SENSE 39 I reference programming pin
VREF 40 I/O voltage reference input/output
Table 3. Pin description (LVDS/DDR) digital outputs)
Symbol Pin
[1]
Type
[2]
Description
D8_D9_M 17 O differential output data D8 and D9 multiplexed, complement
D8_D9_P 18 O differential output data D8 and D9 multiplexed, true
D6_D7_M 19 O differential output data D6 and D7 multiplexed, complement
D6_D7_P 20 O differential output data D6 and D7 multiplexed, true
D4_D5_M 21 O differential output data D4 and D5 multiplexed, complement
D4_D5_P 22 O differential output data D4 and D5 multiplexed, true
D2_D3_M 23 O differential output data D2 and D3 multiplexed, complement
D2_D3_P 24 O differential output data D2 and D3 multiplexed, true
D0_D1_M 25 O differential output data D0 and D1 multiplexed, complement
D0_D1_P 26 O differential output data D0 and D1 multiplexed, true
n.c. 27 - not connected
n.c. 28 - not connected
n.c. 29 - not connected
Table 2. Pin description (CMOS digital outputs)
Symbol Pin Type
[1]
Description