Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsFETsBUK9608-55A,118, MOSFET

BUK95/9608-55A

TrenchMOS™ logic level FET

Rev. 03 — 6 May 2002 Product data

1. Description

N-channel enhancement mode ﬁeld-effect power transistor in a plastic package using

TrenchMOS™ technology, featuring very low on-state resistance.

Product availability:

BUK9508-55A in SOT78 (TO-220AB)

BUK9608-55A in SOT404 (D

-PAK).

2. Features

■ TrenchMOS™ technology

■ Q101 compliant

■ 175 °C rated

■ Logic level compatible.

3. Applications

■ Automotive and general purpose power switching:

◆ 12 V and 24 V loads

◆ Motors, lamps and solenoids.

4. Pinning information

[1] It is not possible to make connection to pin 2 of the SOT404 package.

Table 1: Pinning - SOT78 and SOT404, simpliﬁed outline and symbol

Pin Description Simpliﬁed outline Symbol

1 gate (g)

SOT78 (TO-220AB)

SOT404 (D

-PAK)

2 drain (d)

[1]

3 source (s)

mb mounting base;

connected to drain (d)

MBK106

MBK116

MBB076

Summary of content (14 pages)

PAGE 1
BUK95/9608-55A TrenchMOS™ logic level FET Rev. 03 — 6 May 2002 Product data 1. Description N-channel enhancement mode field-effect power transistor in a plastic package using TrenchMOS™ technology, featuring very low on-state resistance. Product availability: BUK9508-55A in SOT78 (TO-220AB) BUK9608-55A in SOT404 (D2-PAK). 2. Features ■ ■ ■ ■ TrenchMOS™ technology Q101 compliant 175 °C rated Logic level compatible. 3.
PAGE 2
BUK95/9608-55A Philips Semiconductors TrenchMOS™ logic level FET 5. Quick reference data Table 2: Quick reference data Symbol Parameter Conditions Typ Max Unit - 55 V VDS drain-source voltage (DC) ID drain current (DC) Tmb = 25 °C; VGS = 5 V - 125 A Ptot total power dissipation Tmb = 25 °C - 253 W Tj junction temperature - 175 °C RDSon drain-source on-state resistance Tj = 25 °C; VGS = 5 V; ID = 25 A 6.8 8 mΩ Tj = 25 °C; VGS = 4.5 V; ID = 25 A - 8.
PAGE 3
BUK95/9608-55A Philips Semiconductors TrenchMOS™ logic level FET 03na19 120 03ni52 150 ID (A) Pder (%) 80 100 40 50 Capped at 75 A due to package 0 0 0 50 100 150 25 200 Tmb (°C) P tot P der = ----------------------- × 100% P ° 50 75 100 125 150 175 200 Tmb (ºC) VGS ≥ 4.5 V tot ( 25 C ) Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Continuous drain current as a function of mounting base temperature.
PAGE 4
BUK95/9608-55A Philips Semiconductors TrenchMOS™ logic level FET 7. Thermal characteristics Table 4: Thermal characteristics Symbol Parameter Rth(j-mb) thermal resistance from junction to mounting base Rth(j-a) thermal resistance from junction to ambient Conditions Min Typ Max Unit Figure 4 - - 0.59 K/W SOT78 vertical in still air - 60 - K/W SOT404 mounted on a printed circuit board; minimum footprint - 50 - K/W 7.
PAGE 5
BUK95/9608-55A Philips Semiconductors TrenchMOS™ logic level FET 8. Characteristics Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS VGS(th) IDSS drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V Tj = 25 °C 55 - - V Tj = −55 °C 50 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 drain-source leakage current Tj = 25 °C 1 1.5 2 V Tj = 175 °C 0.
PAGE 6
BUK95/9608-55A Philips Semiconductors TrenchMOS™ logic level FET Table 5: Characteristics…continued Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit - 0.85 1.
PAGE 7
BUK95/9608-55A Philips Semiconductors TrenchMOS™ logic level FET 03aa33 2.5 VGS(th) (V) 2 ID (A) 10-2 max 1.5 03aa36 10-1 10-3 typ min max 10-4 min 1 typ 10-5 0.5 10-6 0 -60 0 60 120 180 o 0 1 2 Tj ( C) 3 VGS (V) Tj = 25 °C; VDS = VGS ID = 1 mA; VDS = VGS Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage.
PAGE 8
BUK95/9608-55A Philips Semiconductors TrenchMOS™ logic level FET 03ni45 100 03ni43 5 VGS (V) ID (A) 80 4 60 3 40 2 VDD = 14 V Tj = 175 ºC 20 Tj = 25 ºC VDD = 44 V 1 0 0 0 1 2 3 4 0 20 40 60 VGS (V) 80 100 QG (nC) Tj = 25 °C; ID = 25 A VDS = 25 V Fig 13. Transfer characteristics: drain current as a function of gate-source voltage; typical values. Fig 14. Gate-source voltage as a function of turn-on gate charge; typical values.
PAGE 9
BUK95/9608-55A Philips Semiconductors TrenchMOS™ logic level FET 9. Package outline Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB E SOT78 A A1 p q mounting base D1 D L2 L1(1) Q b1 L 1 2 3 b c e e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 c D D1 E e L L1(1) L2 max. p q Q mm 4.5 4.1 1.39 1.27 0.9 0.7 1.3 1.0 0.7 0.4 15.8 15.2 6.4 5.9 10.3 9.7 2.54 15.0 13.5 3.30 2.79 3.0 3.8 3.6 3.0 2.
PAGE 10
BUK95/9608-55A Philips Semiconductors TrenchMOS™ logic level FET Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D max. D1 E e Lp HD Q mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 11 1.60 1.20 10.30 9.70 2.54 2.90 2.10 15.80 14.80 2.60 2.
PAGE 11
BUK95/9608-55A Philips Semiconductors TrenchMOS™ logic level FET 10. Soldering 10.85 10.60 10.50 handbook, full pagewidth 1.50 7.50 7.40 1.70 2.25 2.15 8.15 8.275 8.35 1.50 4.60 0.30 4.85 5.40 7.95 8.075 3.00 0.20 1.20 1.30 1.55 solder lands solder resist 5.08 MSD057 occupied area solder paste Dimensions in mm. Fig 18. Reflow soldering footprint for SOT404. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09573 Product data Rev.
PAGE 12
BUK95/9608-55A Philips Semiconductors TrenchMOS™ logic level FET 11. Revision history Table 6: Revision history Rev Date 03 20020506 CPCN Description - Product data (9397 750 09573); supersedes Product data of BUK9508_9608-55A_2 of 4 of September 2000. Modifications: • The format of this specification has been redesigned to comply with Philips Semiconductors’ new presentation and information standard. • Thermal resistance figure lowered (j-mb) Section 7.
PAGE 13
BUK95/9608-55A Philips Semiconductors TrenchMOS™ logic level FET 12. Data sheet status Data sheet status[1] Product status[2] Definition Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification.
PAGE 14
Philips Semiconductors BUK95/9608-55A TrenchMOS™ logic level FET Contents 1 2 3 4 5 6 7 7.1 8 9 10 11 12 13 14 15 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . .